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<document scada='0' schema='103' license='1,34201128,Y9T4XA' title='' description='' fcversion='655616' target='PIC.18F.18F25K50' >
	<config data='!0,2923!10,3c5f!20,d300!30,ffa0!40,c00f!50,e00f!60,400f%0,1%1,1%3,0%5,1%8,9%d,1%e,0%f,0%10,1%11,3%13,3%16,1%18,0%1a,f%28,1%29,1%2c,1%2e,1%2f,1%30,0%32,0%36,0%37,1%40,1%41,1%42,1%43,1%4e,1%4f,1%50,1%51,1%52,1%53,1%5d,1%5e,1%5f,1%60,1%61,1%62,1%63,1%6e,1' clkspd='48000000' simspd='0' usewdt='0' constif='1' commport='7' Use3V3='0' />
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	<supplement use='0' head='// Configuration bits: selected in the GUI

// CONFIG1L
#pragma config PLLSEL = PLL3X    // PLL Selection-&gt;3x clock multiplier
#pragma config CFGPLLEN = ON    // PLL Enable Configuration bit-&gt;PLL Enabled
#pragma config CPUDIV = NOCLKDIV    // CPU System Clock Postscaler-&gt;CPU uses system clock (no divide)
#pragma config LS48MHZ = SYS48X8    // Low Speed USB mode with 48 MHz system clock-&gt;System clock at 48 MHz, USB clock divider is set to 8

// CONFIG1H
#pragma config FOSC = INTOSCIO    // Oscillator Selection-&gt;Internal oscillator
#pragma config PCLKEN = ON    // Primary Oscillator Shutdown-&gt;Primary oscillator enabled
#pragma config FCMEN = OFF    // Fail-Safe Clock Monitor-&gt;Fail-Safe Clock Monitor disabled
#pragma config IESO = OFF    // Internal/External Oscillator Switchover-&gt;Oscillator Switchover mode disabled

// CONFIG2L
#pragma config nPWRTEN = OFF    // Power-up Timer Enable-&gt;Power up timer disabled
#pragma config BOREN = SBORDIS    // Brown-out Reset Enable-&gt;BOR enabled in hardware (SBOREN is ignored)
#pragma config BORV = 190    // Brown-out Reset Voltage-&gt;BOR set to 1.9V nominal
#pragma config nLPBOR = OFF    // Low-Power Brown-out Reset-&gt;Low-Power Brown-out Reset disabled

// CONFIG2H
#pragma config WDTEN = OFF    // Watchdog Timer Enable bits-&gt;WDT disabled in hardware (SWDTEN ignored)
#pragma config WDTPS = 32768    // Watchdog Timer Postscaler-&gt;1:32768

// CONFIG3H
#pragma config CCP2MX = RC1    // CCP2 MUX bit-&gt;CCP2 input/output is multiplexed with RC1
#pragma config PBADEN = ON    // PORTB A/D Enable bit-&gt;PORTB&lt;5:0&gt; pins are configured as analog input channels on Reset
#pragma config T3CMX = RC0    // Timer3 Clock Input MUX bit-&gt;T3CKI function is on RC0
#pragma config SDOMX = RB3    // SDO Output MUX bit-&gt;SDO function is on RB3
#pragma config MCLRE = ON    // Master Clear Reset Pin Enable-&gt;MCLR pin enabled; RE3 input disabled

// CONFIG4L
#pragma config STVREN = ON    // Stack Full/Underflow Reset-&gt;Stack full/underflow will cause Reset
#pragma config LVP = OFF    // Single-Supply ICSP Enable bit-&gt;Single-Supply ICSP disabled
#pragma config ICPRT = OFF    // Dedicated In-Circuit Debug/Programming Port Enable-&gt;ICPORT disabled
#pragma config XINST = OFF    // Extended Instruction Set Enable bit-&gt;Instruction set extension and Indexed Addressing mode disabled
#pragma config DEBUG = OFF    // Background Debugger Enable bit-&gt;Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins

// CONFIG5L
#pragma config CP0 = OFF    // Block 0 Code Protect-&gt;Block 0 is not code-protected
#pragma config CP1 = OFF    // Block 1 Code Protect-&gt;Block 1 is not code-protected
#pragma config CP2 = OFF    // Block 2 Code Protect-&gt;Block 2 is not code-protected
#pragma config CP3 = OFF    // Block 3 Code Protect-&gt;Block 3 is not code-protected

// CONFIG5H
#pragma config CPB = OFF    // Boot Block Code Protect-&gt;Boot block is not code-protected
#pragma config CPD = OFF    // Data EEPROM Code Protect-&gt;Data EEPROM is not code-protected

// CONFIG6L
#pragma config WRT0 = OFF    // Block 0 Write Protect-&gt;Block 0 (0800-1FFFh) is not write-protected
#pragma config WRT1 = OFF    // Block 1 Write Protect-&gt;Block 1 (2000-3FFFh) is not write-protected
#pragma config WRT2 = OFF    // Block 2 Write Protect-&gt;Block 2 (04000-5FFFh) is not write-protected
#pragma config WRT3 = OFF    // Block 3 Write Protect-&gt;Block 3 (06000-7FFFh) is not write-protected

// CONFIG6H
#pragma config WRTC = OFF    // Configuration Registers Write Protect-&gt;Configuration registers (300000-3000FFh) are not write-protected
#pragma config WRTB = OFF    // Boot Block Write Protect-&gt;Boot block (0000-7FFh) is not write-protected
#pragma config WRTD = OFF    // Data EEPROM Write Protect-&gt;Data EEPROM is not write-protected

// CONFIG7L
#pragma config EBTR0 = OFF    // Block 0 Table Read Protect-&gt;Block 0 is not protected from table reads executed in other blocks
#pragma config EBTR1 = OFF    // Block 1 Table Read Protect-&gt;Block 1 is not protected from table reads executed in other blocks
#pragma config EBTR2 = OFF    // Block 2 Table Read Protect-&gt;Block 2 is not protected from table reads executed in other blocks
#pragma config EBTR3 = OFF    // Block 3 Table Read Protect-&gt;Block 3 is not protected from table reads executed in other blocks

// CONFIG7H
#pragma config EBTRB = OFF    // Boot Block Table Read Protect-&gt;Boot block is not protected from table reads executed in other blocks' body='' />
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			<data name='DigitalSampleRate' value='100000' />
			<data name='BreakpointCount' value='8' />
			<data name='CallStackDepthCount' value='8' />
			<data name='ClockPort' value='1' />
			<data name='ClockPin' value='7' />
			<data name='DataPort' value='1' />
			<data name='DataPin' value='6' />
			<data name='UseDefaultPins' value='1' />
			<data name='WrapEnabled' value='1' />
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			<data name='CommsDelay' value='4' />
			<data name='CalculatedCommsDelay' value='4' />
			<data name='AnalogEB2PrescaleValue' value='2' />
			<data name='DigitalEB2SampleRate' value='100000' />
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