[General] CfgVersion=2 *************************************************************************** ** PUT THE MORE COMMON CHIPS AT THE START TO GET OVER 64K LIMIT IN WIN98 ** *************************************************************************** ************************************* ** The following chips are missing ** ** ** ************************************* ************************************* ** The following have the same ID *** ** ** 0x0400 = 18F252 & 18F2539 ** 0x0420 = 18F452 & 18F4539 ** 0x0480 = 18F242 & 18F2439 ** 0x04A0 = 18F442 & 18F4439 ** ************************************* * 161008 | ST | Changed mask for 2420, 2520, 4420, 4520 * 230409 | ST | Added a load of new files (see ppp_config_data1.cfg) * 120809 | BR | Changed script info for new files * 310310 | BR | Added new files (18F6xjxx / 18F8xjxx) * 051211 | ST | Added k22 and k80 devices [PIC18F4331] pgmmem=0x0 ~pgmmem=0x1FFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0xff devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x08A0 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004=CONFIG3L 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xC,0xC,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xA,0xA,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xF,0x5,EC-Port on RA6 CONFIG1H~1~8=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xF,0x3,0011 EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xF,0x2,HS CONFIG1H~1~11=0xF,0x1,XT CONFIG1H~1~12=0xF,0x0,LP CONFIG1H~2~1=0x40,0x40,Enabled CONFIG1H~2~2=0x40,0x0,Disabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x2,Brown Out Detect CONFIG2L~3=BODENV,0xC,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x2,0x2,Enabled CONFIG2L~2~2=0x2,0x0,Disabled CONFIG2L~3~1=0xC,0xC,Undefined CONFIG2L~3~2=0xC,0x8,2.7V CONFIG2L~3~3=0xC,0x4,4.2V CONFIG2L~3~4=0xC,0x0,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~3=WINEN,0x20,Watchdog Timer Window CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0xE,1:128 CONFIG2H~2~10=0x1E,0xC,1:64 CONFIG2H~2~11=0x1E,0xA,1:32 CONFIG2H~2~12=0x1E,0x8,1:16 CONFIG2H~2~13=0x1E,0x6,1:8 CONFIG2H~2~14=0x1E,0x4,1:4 CONFIG2H~2~15=0x1E,0x2,1:2 CONFIG2H~2~16=0x1E,0x0,1:1 CONFIG2H~3~1=0x20,0x20,Disabled CONFIG2H~3~2=0x20,0x0,Enabled CONFIG3L_unused=0x0 CONFIG3L~1=PWMPIN,0x4,PWM Output Pin Reset CONFIG3L~2=LPOL,0x8,Low-Side Transistors Polarity CONFIG3L~3=HPOL,0x10,High-Side Transistors Polarity CONFIG3L~4=T1OSCMX,0x20,Timer1 OSC CONFIG3L~1~1=0x4,0x4,PWM outputs disabled upon RESET CONFIG3L~1~2=0x4,0x0,PWM outputs drive active states upon RESET CONFIG3L~2~1=0x8,0x8,PWM 0, 2, 4 and 6 are active high CONFIG3L~2~2=0x8,0x0,PWM 0, 2, 4 and 6 are active low CONFIG3L~3~1=0x10,0x10,PWM 1, 3, 5, and 7 are active high CONFIG3L~3~2=0x10,0x0,PWM 1, 3, 5, and 7 are active low CONFIG3L~4~1=0x20,0x20,Low Power CONFIG3L~4~2=0x20,0x0,Legacy CONFIG3H_unused=0x0 CONFIG3H~1=FLTAMX,0x1,FLTA Mux CONFIG3H~2=SSPMX,0x4,SSP I/O Mux CONFIG3H~3=PWM4MX,0x8,PWM4 Mux CONFIG3H~4=EXCLKMX,0x10,TMR0/T5CKI EXT CLK Mux CONFIG3H~5=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,FLTA input muxed with RC1 CONFIG3H~1~2=0x1,0x0,FLTA input muxed with RD4 CONFIG3H~2~1=0x4,0x0,SCK, SDI, SDO are mux w/ RD3, RD2, RD1 respectively. CONFIG3H~2~2=0x4,0x4,SCK, SDI, SDO are mux w/ RC5, RC4, RC7 respectively. CONFIG3H~3~1=0x8,0x8,PWM4 output muxed w/ RB5 CONFIG3H~3~2=0x8,0x0,PWM4 output muxed w/ RD5 CONFIG3H~4~1=0x10,0x0,TMR0/T5CKI is multiplexed with RD0 CONFIG3H~4~2=0x10,0x10,TMR0/T5CKI is multiplexed with RC3 CONFIG3H~5~1=0x80,0x80,MCLR enabled, RE3 input disabled CONFIG3H~5~2=0x80,0x0,RE3 input enabled, MCLR disabled CONFIG4L_unused=0x0 CONFIG4L~1=BACKBUG,0x80,Background Debug CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=STVR,0x1,Stack Overflow Reset CONFIG4L~1~1=0x80,0x80,Disabled CONFIG4L~1~2=0x80,0x0,Enabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x1,0x1,Enabled CONFIG4L~3~2=0x1,0x0,Disabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00200-00FFF CONFIG5L~2=CP_1,0x2,Code Protect 01000-01FFF CONFIG5L~3=CP_2,0x4,Code Protect 02000-02FFF CONFIG5L~4=CP_3,0x8,Code Protect 03000-03FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EE Read Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00200-00FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 01000-01FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 02000-02FFF CONFIG6L~4=WRT_3,0x8,Table Write Protect 03000-03FFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x00,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EE Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00200-00FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 01000-01FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 02000-02FFF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 03000-03FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x00,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F4431] pgmmem=0x0 ~pgmmem=0x3FFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0xff devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x0880 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004=CONFIG3L 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xC,0xC,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xA,0xA,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xF,0x5,EC-Port on RA6 CONFIG1H~1~8=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xF,0x3,0011 EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xF,0x2,HS CONFIG1H~1~11=0xF,0x1,XT CONFIG1H~1~12=0xF,0x0,LP CONFIG1H~2~1=0x40,0x40,Enabled CONFIG1H~2~2=0x40,0x0,Disabled CONFIG1H~3~1=0x80,0x80,Enabled CONFIG1H~3~2=0x80,0x0,Disabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x2,Brown Out Detect CONFIG2L~3=BODENV,0xC,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x2,0x2,Enabled CONFIG2L~2~2=0x2,0x0,Disabled CONFIG2L~3~1=0xC,0xC,Undefined CONFIG2L~3~2=0xC,0x8,2.7V CONFIG2L~3~3=0xC,0x4,4.2V CONFIG2L~3~4=0xC,0x0,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~3=WINEN,0x20,Watchdog Timer Window CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0xE,1:128 CONFIG2H~2~10=0x1E,0xC,1:64 CONFIG2H~2~11=0x1E,0xA,1:32 CONFIG2H~2~12=0x1E,0x8,1:16 CONFIG2H~2~13=0x1E,0x6,1:8 CONFIG2H~2~14=0x1E,0x4,1:4 CONFIG2H~2~15=0x1E,0x2,1:2 CONFIG2H~2~16=0x1E,0x0,1:1 CONFIG2H~3~1=0x20,0x20,Disabled CONFIG2H~3~2=0x20,0x0,Enabled CONFIG3L_unused=0x0 CONFIG3L~1=PWMPIN,0x4,PWM Output Pin Reset CONFIG3L~2=LPOL,0x8,Low-Side Transistors Polarity CONFIG3L~3=HPOL,0x10,High-Side Transistors Polarity CONFIG3L~4=T1OSCMX,0x20,Timer1 OSC CONFIG3L~1~1=0x4,0x4,PWM outputs disabled upon RESET CONFIG3L~1~2=0x4,0x0,PWM outputs drive active states upon RESET CONFIG3L~2~1=0x8,0x8,PWM 0, 2, 4 and 6 are active high CONFIG3L~2~2=0x8,0x0,PWM 0, 2, 4 and 6 are active low CONFIG3L~3~1=0x10,0x10,PWM 1, 3, 5, and 7 are active high CONFIG3L~3~2=0x10,0x0,PWM 1, 3, 5, and 7 are active low CONFIG3L~4~1=0x20,0x20,Low Power CONFIG3L~4~2=0x20,0x0,Legacy CONFIG3H_unused=0x0 CONFIG3H~1=FLTAMX,0x1,FLTA Mux CONFIG3H~2=SSPMX,0x4,SSP I/O Mux CONFIG3H~3=PWM4MX,0x8,PWM4 Mux CONFIG3H~4=EXCLKMX,0x10,TMR0/T5CKI EXT CLK Mux CONFIG3H~5=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,FLTA input muxed with RC1 CONFIG3H~1~2=0x1,0x0,FLTA input muxed with RD4 CONFIG3H~2~1=0x4,0x4,SCK, SDI, SDO are mux w/ RC5, RC4, RC7 respectively. CONFIG3H~2~2=0x4,0x0,SCK, SDI, SDO are mux w/ RD3, RD2, RD1 respectively. CONFIG3H~3~1=0x8,0x8,PWM4 output muxed w/ RB5 CONFIG3H~3~2=0x8,0x0,PWM4 output muxed w/ RD5 CONFIG3H~4~1=0x10,0x10,TMR0/T5CKI is multiplexed with RC3 CONFIG3H~4~2=0x10,0x0,TMR0/T5CKI is multiplexed with RD0 CONFIG3H~5~1=0x80,0x80,MCLR enabled, RE3 input disabled CONFIG3H~5~2=0x80,0x0,RE3 input enabled, MCLR disabled CONFIG4L_unused=0x0 CONFIG4L~1=BACKBUG,0x80,Background Debug CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=STVR,0x1,Stack Overflow Reset CONFIG4L~1~1=0x80,0x80,Disabled CONFIG4L~1~2=0x80,0x0,Enabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x1,0x1,Enabled CONFIG4L~3~2=0x1,0x0,Disabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00200-00FFF CONFIG5L~2=CP_1,0x2,Code Protect 01000-01FFF CONFIG5L~3=CP_2,0x4,Code Protect 02000-02FFF CONFIG5L~4=CP_3,0x8,Code Protect 03000-03FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EE Read Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00200-00FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 01000-01FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 02000-02FFF CONFIG6L~4=WRT_3,0x8,Table Write Protect 03000-03FFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x00,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EE Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00200-00FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 01000-01FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 02000-02FFF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 03000-03FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x00,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F4410] pgmmem=0x0 ~pgmmem=0x3FFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata= ~eedata= devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x10E0 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xC,0xC,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xA,0xA,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xF,0x5,EC-Port on RA6 CONFIG1H~1~8=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xF,0x3,0011 EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xF,0x2,HS CONFIG1H~1~11=0xF,0x1,XT CONFIG1H~1~12=0xF,0x0,LP CONFIG1H~2~1=0x40,0x40,Enabled CONFIG1H~2~2=0x40,0x0,Disabled CONFIG1H~3~1=0x80,0x80,Enabled CONFIG1H~3~2=0x80,0x0,Disabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x08,4.2V CONFIG2L~3~4=0x18,0x00,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=PBADEN,0x2,PortB A/D Enable CONFIG3H~3=LPT1OSC,0x04,Low Power Timer1 Osc enable CONFIG3H~4=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RB3 CONFIG3H~2~1=0x2,0x2,PORTB<4:0> configured as analog inputs on RESET CONFIG3H~2~2=0x2,0x0,PORTB<4:0> configured as digital I/O on RESET CONFIG3H~3~1=0x04,0x04,Enabled CONFIG3H~3~2=0x04,0x00,Disabled CONFIG3H~4~1=0x80,0x80,MCLR Enabled,RE3 Disabled CONFIG3H~4~2=0x80,0x00,MCLR Disabled,RE3 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=ENHCPU,0x40,Extended CPU Enable CONFIG4L~4=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x40,0x40,Enabled CONFIG4L~3~2=0x40,0x00,Disabled CONFIG4L~4~1=0x80,0x80,Disabled CONFIG4L~4~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-01FFF CONFIG5L~2=CP_1,0x2,Code Protect 02000-03FFF CONFIG5L~3=CP_2,0x4,Code Protect 04000-05FFF CONFIG5L~4=CP_3,0x8,Code Protect 06000-07FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EEPROM Code Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-01FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 02000-03FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 04000-05FFF CONFIG6L~4=WRT_3,0x8,Table Write Protect 06000-07FFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x00,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTC,0x20,Config. Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTD,0x80,Data EEPROM Write Protect CONFIG6H~1~1=0x20,0x20,Disabled CONFIG6H~1~2=0x20,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x80,0x80,Disabled CONFIG6H~3~2=0x80,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-01FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 02000-03FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 04000-05FFF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 06000-07FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x00,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE_24xx05 prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F442] pgmmem=0x0 ~pgmmem=0x3FFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0xff devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x04A0 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0x7,Oscillator CONFIG1H~2=OSCS,0x20,Osc. Switch Enable CONFIG1H~1~1=0x7,0x7,RC-OSC2 as RA6 CONFIG1H~1~2=0x7,0x6,HS-PLL Enabled CONFIG1H~1~3=0x7,0x5,EC-OSC2 as RA6 CONFIG1H~1~4=0x7,0x4,EC-OSC2 as Clock Out CONFIG1H~1~5=0x7,0x3,RC CONFIG1H~1~6=0x7,0x2,HS CONFIG1H~1~7=0x7,0x1,XT CONFIG1H~1~8=0x7,0x0,LP CONFIG1H~2~1=0x20,0x20,Disabled CONFIG1H~2~2=0x20,0x0,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x2,Brown Out Detect CONFIG2L~3=BODENV,0xC,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x2,0x2,Enabled CONFIG2L~2~2=0x2,0x0,Disabled CONFIG2L~3~1=0xC,0xC,2.5V CONFIG2L~3~2=0xC,0x8,2.7V CONFIG2L~3~3=0xC,0x4,4.2V CONFIG2L~3~4=0xC,0x0,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0xE,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0xE,0xE,1:128 CONFIG2H~2~2=0xE,0xC,1:64 CONFIG2H~2~3=0xE,0xA,1:32 CONFIG2H~2~4=0xE,0x8,1:16 CONFIG2H~2~5=0xE,0x6,1:8 CONFIG2H~2~6=0xE,0x4,1:4 CONFIG2H~2~7=0xE,0x2,1:2 CONFIG2H~2~8=0xE,0x0,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RB3 CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x80,0x80,Disabled CONFIG4L~3~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00200-01FFF CONFIG5L~2=CP_1,0x2,Code Protect 02000-03FFF CONFIG5L~3=CP_2,0x4,Code Protect 04000-05FFF CONFIG5L~4=CP_3,0x8,Code Protect 06000-07FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EE Read Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00200-01FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 02000-03FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 04000-05FFF CONFIG6L~4=WRT_3,0x8,Table Write Protect 06000-07FFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x00,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EE Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00200-01FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 02000-03FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 04000-05FFF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 06000-07FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x00,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F4420] pgmmem=0x0 ~pgmmem=0x3FFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata= ~eedata= devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFF0 id=0x10C0 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xC,0xC,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xA,0xA,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xF,0x5,EC-Port on RA6 CONFIG1H~1~8=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xF,0x3,0011 EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xF,0x2,HS CONFIG1H~1~11=0xF,0x1,XT CONFIG1H~1~12=0xF,0x0,LP CONFIG1H~2~1=0x40,0x40,Enabled CONFIG1H~2~2=0x40,0x0,Disabled CONFIG1H~3~1=0x80,0x80,Enabled CONFIG1H~3~2=0x80,0x0,Disabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x08,4.2V CONFIG2L~3~4=0x18,0x00,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=PBADEN,0x2,PortB A/D Enable CONFIG3H~3=LPT1OSC,0x04,Low Power Timer1 Osc enable CONFIG3H~4=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RB3 CONFIG3H~2~1=0x2,0x2,PORTB<4:0> configured as analog inputs on RESET CONFIG3H~2~2=0x2,0x0,PORTB<4:0> configured as digital I/O on RESET CONFIG3H~3~1=0x04,0x04,Enabled CONFIG3H~3~2=0x04,0x00,Disabled CONFIG3H~4~1=0x80,0x80,MCLR Enabled,RE3 Disabled CONFIG3H~4~2=0x80,0x00,MCLR Disabled,RE3 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=ENHCPU,0x40,Extended CPU Enable CONFIG4L~4=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x40,0x40,Enabled CONFIG4L~3~2=0x40,0x00,Disabled CONFIG4L~4~1=0x80,0x80,Disabled CONFIG4L~4~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-01FFF CONFIG5L~2=CP_1,0x2,Code Protect 02000-03FFF CONFIG5L~3=CP_2,0x4,Code Protect 04000-05FFF CONFIG5L~4=CP_3,0x8,Code Protect 06000-07FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EEPROM Code Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-01FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 02000-03FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 04000-05FFF CONFIG6L~4=WRT_3,0x8,Table Write Protect 06000-07FFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x00,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTC,0x20,Config. Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTD,0x80,Data EEPROM Write Protect CONFIG6H~1~1=0x20,0x20,Disabled CONFIG6H~1~2=0x20,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x80,0x80,Disabled CONFIG6H~3~2=0x80,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-01FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 02000-03FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 04000-05FFF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 06000-07FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x00,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE_24xx05 prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F1220] pgmmem=0x0 ~pgmmem=0x0FFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0xff devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x07E0 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xC,0xC,EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~3=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~5=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~6=0xF,0x5,EC-Port on RA6 CONFIG1H~1~7=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~8=0xF,0x2,HS CONFIG1H~1~9=0xF,0x1,XT CONFIG1H~1~10=0xF,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x2,Brown Out Detect CONFIG2L~3=BODENV,0xC,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x2,0x2,Enabled CONFIG2L~2~2=0x2,0x0,Disabled CONFIG2L~3~1=0xC,0xC,2.0V CONFIG2L~3~2=0xC,0x8,2.7V CONFIG2L~3~3=0xC,0x4,4.2V CONFIG2L~3~4=0xC,0x0,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x80,0x80,MCLR enabled, RA5 input disabled CONFIG3H~1~2=0x80,0x00,MCLR disabled, RA5 input enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x80,0x80,Disabled CONFIG4L~3~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 000200-0007FF CONFIG5L~2=CP_1,0x2,Code Protect 000800-000FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EEPROM Code Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00200-007FF CONFIG6L~2=WRT_1,0x2,Table Write Protect 00800-00FFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EEPROM Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00200-007FF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 00800-00FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F1320] pgmmem=0x0 ~pgmmem=0x1FFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0xff devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x07C0 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xC,0xC,EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~3=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~5=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~6=0xF,0x5,EC-Port on RA6 CONFIG1H~1~7=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~8=0xF,0x2,HS CONFIG1H~1~9=0xF,0x1,XT CONFIG1H~1~10=0xF,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x2,Brown Out Detect CONFIG2L~3=BODENV,0xC,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x2,0x2,Enabled CONFIG2L~2~2=0x2,0x0,Disabled CONFIG2L~3~1=0xC,0xC,2.0V CONFIG2L~3~2=0xC,0x8,2.7V CONFIG2L~3~3=0xC,0x4,4.2V CONFIG2L~3~4=0xC,0x0,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x80,0x80,MCLR enabled, RA5 input disabled CONFIG3H~1~2=0x80,0x00,MCLR disabled, RA5 input enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x80,0x80,Disabled CONFIG4L~3~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 000200-000FFF CONFIG5L~2=CP_1,0x2,Code Protect 001000-001FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EEPROM Code Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00200-00FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 01000-01FFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EEPROM Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00200-00FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 01000-01FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F2220] pgmmem=0x0 ~pgmmem=0x0FFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0xff devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x0580 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xC,0xC,EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~3=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~5=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~6=0xF,0x5,EC-Port on RA6 CONFIG1H~1~7=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~8=0xF,0x2,HS CONFIG1H~1~9=0xF,0x1,XT CONFIG1H~1~10=0xF,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x2,Brown Out Detect CONFIG2L~3=BODENV,0xC,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x2,0x2,Enabled CONFIG2L~2~2=0x2,0x0,Disabled CONFIG2L~3~1=0xC,0xC,2.0V CONFIG2L~3~2=0xC,0x8,2.7V CONFIG2L~3~3=0xC,0x4,4.2V CONFIG2L~3~4=0xC,0x0,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=PBADEN,0x2,PortB A/D Enable CONFIG3H~3=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RB3 CONFIG3H~2~1=0x2,0x2,PORTB<4:0> configured as analog inputs on RESET CONFIG3H~2~2=0x2,0x0,PORTB<4:0> configured as digital I/O on RESET CONFIG3H~3~1=0x80,0x80,MCLR Enabled CONFIG3H~3~2=0x80,0x00,MCLR Disabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x80,0x80,Disabled CONFIG4L~3~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 000200-0007FF CONFIG5L~2=CP_1,0x2,Code Protect 000800-000FFF CONFIG5L~3=CP_2,0x4,Code Protect 001000-0017FF CONFIG5L~4=CP_3,0x8,Code Protect 001800-001FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EEPROM Code Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00200-007FF CONFIG6L~2=WRT_1,0x2,Table Write Protect 00800-00FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 01000-017FF CONFIG6L~4=WRT_3,0x8,Table Write Protect 01800-01FFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x00,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EEPROM Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00200-007FF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 00800-00FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 01000-017FF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 01800-01FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x00,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F2320] pgmmem=0x0 ~pgmmem=0x1FFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0xff devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x0500 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xC,0xC,EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~3=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~5=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~6=0xF,0x5,EC-Port on RA6 CONFIG1H~1~7=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~8=0xF,0x2,HS CONFIG1H~1~9=0xF,0x1,XT CONFIG1H~1~10=0xF,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x2,Brown Out Detect CONFIG2L~3=BODENV,0xC,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x2,0x2,Enabled CONFIG2L~2~2=0x2,0x0,Disabled CONFIG2L~3~1=0xC,0xC,2.0V CONFIG2L~3~2=0xC,0x8,2.7V CONFIG2L~3~3=0xC,0x4,4.2V CONFIG2L~3~4=0xC,0x0,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=PBADEN,0x2,PortB A/D Enable CONFIG3H~3=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RB3 CONFIG3H~2~1=0x2,0x2,PORTB<4:0> configured as analog inputs on RESET CONFIG3H~2~2=0x2,0x0,PORTB<4:0> configured as digital I/O on RESET CONFIG3H~3~1=0x80,0x80,MCLR Enabled CONFIG3H~3~2=0x80,0x00,MCLR Disabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x80,0x80,Disabled CONFIG4L~3~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 000200-0007FF CONFIG5L~2=CP_1,0x2,Code Protect 000800-000FFF CONFIG5L~3=CP_2,0x4,Code Protect 001000-0017FF CONFIG5L~4=CP_3,0x8,Code Protect 001800-001FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EEPROM Code Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00200-007FF CONFIG6L~2=WRT_1,0x2,Table Write Protect 00800-00FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 01000-017FF CONFIG6L~4=WRT_3,0x8,Table Write Protect 01800-01FFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x00,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EEPROM Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00200-007FF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 00800-00FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 01000-017FF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 01800-01FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x00,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F2331] pgmmem=0x0 ~pgmmem=0x1FFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0xff devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x08E0 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004=CONFIG3L 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xC,0xC,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xA,0xA,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xF,0x5,EC-Port on RA6 CONFIG1H~1~8=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xF,0x3,0011 EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xF,0x2,HS CONFIG1H~1~11=0xF,0x1,XT CONFIG1H~1~12=0xF,0x0,LP CONFIG1H~2~1=0x40,0x40,Enabled CONFIG1H~2~2=0x40,0x0,Disabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x2,Brown Out Detect CONFIG2L~3=BODENV,0xC,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x2,0x2,Enabled CONFIG2L~2~2=0x2,0x0,Disabled CONFIG2L~3~1=0xC,0xC,Undefined CONFIG2L~3~2=0xC,0x8,2.7V CONFIG2L~3~3=0xC,0x4,4.2V CONFIG2L~3~4=0xC,0x0,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~3=WINEN,0x20,Watchdog Timer Window CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0xE,1:128 CONFIG2H~2~10=0x1E,0xC,1:64 CONFIG2H~2~11=0x1E,0xA,1:32 CONFIG2H~2~12=0x1E,0x8,1:16 CONFIG2H~2~13=0x1E,0x6,1:8 CONFIG2H~2~14=0x1E,0x4,1:4 CONFIG2H~2~15=0x1E,0x2,1:2 CONFIG2H~2~16=0x1E,0x0,1:1 CONFIG2H~3~1=0x20,0x20,Disabled CONFIG2H~3~2=0x20,0x0,Enabled CONFIG3L_unused=0x0 CONFIG3L~1=PWMPIN,0x4,PWM Output Pin Reset CONFIG3L~2=LPOL,0x8,Low-Side Transistors Polarity CONFIG3L~3=HPOL,0x10,High-Side Transistors Polarity CONFIG3L~4=T1OSCMX,0x20,Timer1 OSC CONFIG3L~1~1=0x4,0x4,PWM outputs disabled upon RESET CONFIG3L~1~2=0x4,0x0,PWM outputs drive active states upon RESET CONFIG3L~2~1=0x8,0x8,PWM 0, 2, 4 and 6 are active high CONFIG3L~2~2=0x8,0x0,PWM 0, 2, 4 and 6 are active low CONFIG3L~3~1=0x10,0x10,PWM 1, 3, 5, and 7 are active high CONFIG3L~3~2=0x10,0x0,PWM 1, 3, 5, and 7 are active low CONFIG3L~4~1=0x20,0x20,Low Power CONFIG3L~4~2=0x20,0x0,Legacy CONFIG3H_unused=0x0 CONFIG3H~1=FLTAMX,0x1,FLTA Mux CONFIG3H~2=SSPMX,0x4,SSP I/O Mux CONFIG3H~3=PWM4MX,0x8,PWM4 Mux CONFIG3H~4=EXCLKMX,0x10,TMR0/T5CKI EXT CLK Mux CONFIG3H~5=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,FLTA input muxed with RC1 CONFIG3H~1~2=0x1,0x0,FLTA input muxed with RD4 CONFIG3H~2~1=0x4,0x0,SPI not assigned CONFIG3H~2~2=0x4,0x4,SCK, SDI, SDO are mux w/ RC5, RC4, RC7 respectively. CONFIG3H~3~1=0x8,0x8,PWM4 output muxed w/ RB5 CONFIG3H~3~2=0x8,0x0,PWM4 output muxed w/ RD5 CONFIG3H~4~1=0x10,0x0,TMR0/T5CKI is multiplexed with RD0 CONFIG3H~4~2=0x10,0x10,TMR0/T5CKI is multiplexed with RC3 CONFIG3H~5~1=0x80,0x80,MCLR enabled, RE3 input disabled CONFIG3H~5~2=0x80,0x0,RE3 input enabled, MCLR disabled CONFIG4L_unused=0x0 CONFIG4L~1=BACKBUG,0x80,Background Debug CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=STVR,0x1,Stack Overflow Reset CONFIG4L~1~1=0x80,0x80,Disabled CONFIG4L~1~2=0x80,0x0,Enabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x1,0x1,Enabled CONFIG4L~3~2=0x1,0x0,Disabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00200-00FFF CONFIG5L~2=CP_1,0x2,Code Protect 01000-01FFF CONFIG5L~3=CP_2,0x4,Code Protect 02000-02FFF CONFIG5L~4=CP_3,0x8,Code Protect 03000-03FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EE Read Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00200-00FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 01000-01FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 02000-02FFF CONFIG6L~4=WRT_3,0x8,Table Write Protect 03000-03FFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x00,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EE Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00200-00FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 01000-01FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 02000-02FFF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 03000-03FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x00,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F2410] pgmmem=0x0 ~pgmmem=0x3FFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata= ~eedata= devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x1160 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xC,0xC,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xA,0xA,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xF,0x5,EC-Port on RA6 CONFIG1H~1~8=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xF,0x3,0011 EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xF,0x2,HS CONFIG1H~1~11=0xF,0x1,XT CONFIG1H~1~12=0xF,0x0,LP CONFIG1H~2~1=0x40,0x40,Enabled CONFIG1H~2~2=0x40,0x0,Disabled CONFIG1H~3~1=0x80,0x80,Enabled CONFIG1H~3~2=0x80,0x0,Disabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x08,4.2V CONFIG2L~3~4=0x18,0x00,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=PBADEN,0x2,PortB A/D Enable CONFIG3H~3=LPT1OSC,0x04,Low Power Timer1 Osc enable CONFIG3H~4=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RB3 CONFIG3H~2~1=0x2,0x2,PORTB<4:0> configured as analog inputs on RESET CONFIG3H~2~2=0x2,0x0,PORTB<4:0> configured as digital I/O on RESET CONFIG3H~3~1=0x04,0x04,Enabled CONFIG3H~3~2=0x04,0x00,Disabled CONFIG3H~4~1=0x80,0x80,MCLR Enabled,RE3 Disabled CONFIG3H~4~2=0x80,0x00,MCLR Disabled,RE3 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=ENHCPU,0x40,Extended CPU Enable CONFIG4L~4=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x40,0x40,Enabled CONFIG4L~3~2=0x40,0x00,Disabled CONFIG4L~4~1=0x80,0x80,Disabled CONFIG4L~4~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-01FFF CONFIG5L~2=CP_1,0x2,Code Protect 02000-03FFF CONFIG5L~3=CP_2,0x4,Code Protect 04000-05FFF CONFIG5L~4=CP_3,0x8,Code Protect 06000-07FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EEPROM Code Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-01FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 02000-03FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 04000-05FFF CONFIG6L~4=WRT_3,0x8,Table Write Protect 06000-07FFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x00,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTC,0x20,Config. Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTD,0x80,Data EEPROM Write Protect CONFIG6H~1~1=0x20,0x20,Disabled CONFIG6H~1~2=0x20,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x80,0x80,Disabled CONFIG6H~3~2=0x80,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-01FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 02000-03FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 04000-05FFF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 06000-07FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x00,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE_24xx05 prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F242] pgmmem=0x0 ~pgmmem=0x3FFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0xff devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x0480 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0x7,Oscillator CONFIG1H~2=OSCS,0x20,Osc. Switch Enable CONFIG1H~1~1=0x7,0x7,RC-OSC2 as RA6 CONFIG1H~1~2=0x7,0x6,HS-PLL Enabled CONFIG1H~1~3=0x7,0x5,EC-OSC2 as RA6 CONFIG1H~1~4=0x7,0x4,EC-OSC2 as Clock Out CONFIG1H~1~5=0x7,0x3,RC CONFIG1H~1~6=0x7,0x2,HS CONFIG1H~1~7=0x7,0x1,XT CONFIG1H~1~8=0x7,0x0,LP CONFIG1H~2~1=0x20,0x20,Disabled CONFIG1H~2~2=0x20,0x0,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x2,Brown Out Detect CONFIG2L~3=BODENV,0xC,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x2,0x2,Enabled CONFIG2L~2~2=0x2,0x0,Disabled CONFIG2L~3~1=0xC,0xC,2.5V CONFIG2L~3~2=0xC,0x8,2.7V CONFIG2L~3~3=0xC,0x4,4.2V CONFIG2L~3~4=0xC,0x0,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0xE,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0xE,0xE,1:128 CONFIG2H~2~2=0xE,0xC,1:64 CONFIG2H~2~3=0xE,0xA,1:32 CONFIG2H~2~4=0xE,0x8,1:16 CONFIG2H~2~5=0xE,0x6,1:8 CONFIG2H~2~6=0xE,0x4,1:4 CONFIG2H~2~7=0xE,0x2,1:2 CONFIG2H~2~8=0xE,0x0,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RB3 CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x80,0x80,Disabled CONFIG4L~3~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00200-01FFF CONFIG5L~2=CP_1,0x2,Code Protect 02000-03FFF CONFIG5L~3=CP_2,0x4,Code Protect 04000-05FFF CONFIG5L~4=CP_3,0x8,Code Protect 06000-07FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EE Read Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00200-01FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 02000-03FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 04000-05FFF CONFIG6L~4=WRT_3,0x8,Table Write Protect 06000-07FFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x00,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EE Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00200-01FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 02000-03FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 04000-05FFF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 06000-07FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x00,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F2420] pgmmem=0x0 ~pgmmem=0x3FFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata= ~eedata= devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFF0 id=0x1140 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xC,0xC,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xA,0xA,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xF,0x5,EC-Port on RA6 CONFIG1H~1~8=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xF,0x3,0011 EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xF,0x2,HS CONFIG1H~1~11=0xF,0x1,XT CONFIG1H~1~12=0xF,0x0,LP CONFIG1H~2~1=0x40,0x40,Enabled CONFIG1H~2~2=0x40,0x0,Disabled CONFIG1H~3~1=0x80,0x80,Enabled CONFIG1H~3~2=0x80,0x0,Disabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x08,4.2V CONFIG2L~3~4=0x18,0x00,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=PBADEN,0x2,PortB A/D Enable CONFIG3H~3=LPT1OSC,0x04,Low Power Timer1 Osc enable CONFIG3H~4=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RB3 CONFIG3H~2~1=0x2,0x2,PORTB<4:0> configured as analog inputs on RESET CONFIG3H~2~2=0x2,0x0,PORTB<4:0> configured as digital I/O on RESET CONFIG3H~3~1=0x04,0x04,Enabled CONFIG3H~3~2=0x04,0x00,Disabled CONFIG3H~4~1=0x80,0x80,MCLR Enabled,RE3 Disabled CONFIG3H~4~2=0x80,0x00,MCLR Disabled,RE3 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=ENHCPU,0x40,Extended CPU Enable CONFIG4L~4=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x40,0x40,Enabled CONFIG4L~3~2=0x40,0x00,Disabled CONFIG4L~4~1=0x80,0x80,Disabled CONFIG4L~4~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-01FFF CONFIG5L~2=CP_1,0x2,Code Protect 02000-03FFF CONFIG5L~3=CP_2,0x4,Code Protect 04000-05FFF CONFIG5L~4=CP_3,0x8,Code Protect 06000-07FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EEPROM Code Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-01FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 02000-03FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 04000-05FFF CONFIG6L~4=WRT_3,0x8,Table Write Protect 06000-07FFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x00,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTC,0x20,Config. Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTD,0x80,Data EEPROM Write Protect CONFIG6H~1~1=0x20,0x20,Disabled CONFIG6H~1~2=0x20,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x80,0x80,Disabled CONFIG6H~3~2=0x80,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-01FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 02000-03FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 04000-05FFF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 06000-07FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x00,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE_24xx05 prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F2431] pgmmem=0x0 ~pgmmem=0x3FFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0xff devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x08C0 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004=CONFIG3L 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xC,0xC,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xA,0xA,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xF,0x5,EC-Port on RA6 CONFIG1H~1~8=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xF,0x3,0011 EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xF,0x2,HS CONFIG1H~1~11=0xF,0x1,XT CONFIG1H~1~12=0xF,0x0,LP CONFIG1H~2~1=0x40,0x40,Enabled CONFIG1H~2~2=0x40,0x0,Disabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x2,Brown Out Detect CONFIG2L~3=BODENV,0xC,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x2,0x2,Enabled CONFIG2L~2~2=0x2,0x0,Disabled CONFIG2L~3~1=0xC,0xC,Undefined CONFIG2L~3~2=0xC,0x8,2.7V CONFIG2L~3~3=0xC,0x4,4.2V CONFIG2L~3~4=0xC,0x0,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~3=WINEN,0x20,Watchdog Timer Window CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0xE,1:128 CONFIG2H~2~10=0x1E,0xC,1:64 CONFIG2H~2~11=0x1E,0xA,1:32 CONFIG2H~2~12=0x1E,0x8,1:16 CONFIG2H~2~13=0x1E,0x6,1:8 CONFIG2H~2~14=0x1E,0x4,1:4 CONFIG2H~2~15=0x1E,0x2,1:2 CONFIG2H~2~16=0x1E,0x0,1:1 CONFIG2H~3~1=0x20,0x20,Disabled CONFIG2H~3~2=0x20,0x0,Enabled CONFIG3L_unused=0x0 CONFIG3L~1=PWMPIN,0x4,PWM Output Pin Reset CONFIG3L~2=LPOL,0x8,Low-Side Transistors Polarity CONFIG3L~3=HPOL,0x10,High-Side Transistors Polarity CONFIG3L~4=T1OSCMX,0x20,Timer1 OSC CONFIG3L~1~1=0x4,0x4,PWM outputs disabled upon RESET CONFIG3L~1~2=0x4,0x0,PWM outputs drive active states upon RESET CONFIG3L~2~1=0x8,0x8,PWM 0, 2, 4 and 6 are active high CONFIG3L~2~2=0x8,0x0,PWM 0, 2, 4 and 6 are active low CONFIG3L~3~1=0x10,0x10,PWM 1, 3, 5, and 7 are active high CONFIG3L~3~2=0x10,0x0,PWM 1, 3, 5, and 7 are active low CONFIG3L~4~1=0x20,0x20,Low Power CONFIG3L~4~2=0x20,0x0,Legacy CONFIG3H_unused=0x0 CONFIG3H~1=FLTAMX,0x1,FLTA Mux CONFIG3H~2=SSPMX,0x4,SSP I/O Mux CONFIG3H~3=PWM4MX,0x8,PWM4 Mux CONFIG3H~4=EXCLKMX,0x10,TMR0/T5CKI EXT CLK Mux CONFIG3H~5=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,FLTA input muxed with RC1 CONFIG3H~1~2=0x1,0x0,FLTA input muxed with RD4 CONFIG3H~2~1=0x4,0x0,SPI not assigned CONFIG3H~2~2=0x4,0x4,SCK, SDI, SDO are mux w/ RC5, RC4, RC7 respectively. CONFIG3H~3~1=0x8,0x8,PWM4 output muxed w/ RB5 CONFIG3H~3~2=0x8,0x0,PWM4 output muxed w/ RD5 CONFIG3H~4~1=0x10,0x0,TMR0/T5CKI is multiplexed with RD0 CONFIG3H~4~2=0x10,0x10,TMR0/T5CKI is multiplexed with RC3 CONFIG3H~5~1=0x80,0x80,MCLR enabled, RE3 input disabled CONFIG3H~5~2=0x80,0x0,RE3 input enabled, MCLR disabled CONFIG4L_unused=0x0 CONFIG4L~1=BACKBUG,0x80,Background Debug CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=STVR,0x1,Stack Overflow Reset CONFIG4L~1~1=0x80,0x80,Disabled CONFIG4L~1~2=0x80,0x0,Enabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x1,0x1,Enabled CONFIG4L~3~2=0x1,0x0,Disabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00200-00FFF CONFIG5L~2=CP_1,0x2,Code Protect 01000-01FFF CONFIG5L~3=CP_2,0x4,Code Protect 02000-02FFF CONFIG5L~4=CP_3,0x8,Code Protect 03000-03FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EE Read Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00200-00FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 01000-01FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 02000-02FFF CONFIG6L~4=WRT_3,0x8,Table Write Protect 03000-03FFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x00,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EE Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00200-00FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 01000-01FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 02000-02FFF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 03000-03FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x00,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F2439] pgmmem=0x0 ~pgmmem=0x3FFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0xff devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x0480 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=RESERVED1 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0x7,Oscillator CONFIG1H~2=RES1,0x20,Reserved CONFIG1H~1~1=0x7,0x6,HS-PLL Enabled CONFIG1H~1~2=0x7,0x5,EC-OSC2 as RA6 CONFIG1H~1~3=0x7,0x4,EC-OSC2 as Clock Out CONFIG1H~1~4=0x7,0x2,HS CONFIG1H~2~1=0x20,0x20,Reserved CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x2,Brown Out Detect CONFIG2L~3=BODENV,0xC,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x2,0x2,Enabled CONFIG2L~2~2=0x2,0x0,Disabled CONFIG2L~3~1=0xC,0xC,2.5V CONFIG2L~3~2=0xC,0x8,2.7V CONFIG2L~3~3=0xC,0x4,4.2V CONFIG2L~3~4=0xC,0x0,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0xE,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0xE,0xE,1:128 CONFIG2H~2~2=0xE,0xC,1:64 CONFIG2H~2~3=0xE,0xA,1:32 CONFIG2H~2~4=0xE,0x8,1:16 CONFIG2H~2~5=0xE,0x6,1:8 CONFIG2H~2~6=0xE,0x4,1:4 CONFIG2H~2~7=0xE,0x2,1:2 CONFIG2H~2~8=0xE,0x0,1:1 RESERVED1_unused=0x0 RESERVED1~1=RES1,0x1,Reserved RESERVED1~1~1=0x1,0x1,Reserved CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x80,0x80,Disabled CONFIG4L~3~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00200-01FFF CONFIG5L~2=CP_1,0x2,Code Protect 02000-03FFF CONFIG5L~3=CP_2,0x4,Code Protect 04000-05FFF CONFIG5L~4=RES1,0x8,Reserved CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Reserved CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EE Read Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00200-01FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 02000-03FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 04000-05FFF CONFIG6L~4=RES1,0x8,Reserved CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x00,Enabled CONFIG6L~4~1=0x8,0x8,Reserved CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EE Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00200-01FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 02000-03FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 04000-05FFF CONFIG7L~4=RES1,0x8,Reserved CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x00,Enabled CONFIG7L~4~1=0x8,0x8,Reserved CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F2455] pgmmem=0x0 ~pgmmem=0x5FFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0xff devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x1260 configslots=14 0x300000=CONFIG1L 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1L_unused=0x0 CONFIG1L~1=USBPLL,0x20,USB Clock Selection CONFIG1L~2=CPUDIV,0x18,CPU Sys CLK Select CONFIG1L~3=PLLDIV,0x07,OSC Select CONFIG1L~1~1=0x20,0x20,clk src from 96MHz PLL/2 CONFIG1L~1~2=0x20,0x00,clk src from OSC1/OSC2 CONFIG1L~2~1=0x18,0x18,div by 4 CONFIG1L~2~2=0x18,0x10,div by 3 CONFIG1L~2~3=0x18,0x08,div by 2 CONFIG1L~2~4=0x18,0x00,no divide CONFIG1L~3~1=0x07,0x07,div by 12 {48MHz input} CONFIG1L~3~2=0x07,0x06,div by 10 {40MHz input} CONFIG1L~3~3=0x07,0x05,div by 6 {24MHz input} CONFIG1L~3~4=0x07,0x04,div by 5 {20MHz input} CONFIG1L~3~5=0x07,0x03,div by 4 {16MHz input} CONFIG1L~3~6=0x07,0x02,div by 3 {12MHz input} CONFIG1L~3~7=0x07,0x01,div by 2 {8MHz input} CONFIG1L~3~8=0x07,0x00,no divide {4MHz input} CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xE,0xE,HS: HS+PLL, USB-HS CONFIG1H~1~2=0xE,0xC,HS: USB-HS CONFIG1H~1~3=0xF,0xB,INTOSC: USB-HS CONFIG1H~1~4=0xF,0xA,INTOSC: USB-XT CONFIG1H~1~5=0xF,0x9,INTOSC: INTOSC+CLK0{RA6}, USB-EC CONFIG1H~1~6=0xF,0x8,INTOSC: INTOSC+RA6, USB-EC CONFIG1H~1~7=0xF,0x7,EC: EC+PLL, EC+PLL+CLKO{RA6}, USB-EC CONFIG1H~1~8=0xF,0x6,EC: EC+PLL, EC+PLL+RA6, USB-EC CONFIG1H~1~9=0xF,0x5,EC: EC+CLKO{RA6}, USB-EC CONFIG1H~1~10=0xF,0x4,EC: EC+RA6, USB-EC CONFIG1H~1~11=0xE,0x2,XT: XT+PLL, USB-XT CONFIG1H~1~12=0xE,0x0,XT: USB-XT CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=VREGEN,0x20,USB Voltage Regulator CONFIG2L~2=PUT,0x1,Power Up Timer CONFIG2L~3=BODEN,0x6,Brown Out Detect CONFIG2L~4=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x20,0x20,Enabled CONFIG2L~1~2=0x20,0x00,Disabled CONFIG2L~2~1=0x1,0x1,Disabled CONFIG2L~2~2=0x1,0x0,Enabled CONFIG2L~3~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~3~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~3~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~3~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~4~1=0x18,0x18,2.0V CONFIG2L~4~2=0x18,0x10,2.7V CONFIG2L~4~3=0x18,0x08,4.2V CONFIG2L~4~4=0x18,0x00,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=PBADEN,0x2,PortB A/D Enable CONFIG3H~3=LPT1OSC,0x04,Low Power Timer1 Osc enable CONFIG3H~4=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RB3 CONFIG3H~2~1=0x2,0x2,PORTB<4:0> configured as analog inputs on RESET CONFIG3H~2~2=0x2,0x0,PORTB<4:0> configured as digital I/O on RESET CONFIG3H~3~1=0x04,0x04,Enabled CONFIG3H~3~2=0x04,0x00,Disabled CONFIG3H~4~1=0x80,0x80,MCLR Enabled,RE3 Disabled CONFIG3H~4~2=0x80,0x00,MCLR Disabled,RE3 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=ENICPORT,0x20,Dedicated In-Circuit Port {ICD/ICSP} CONFIG4L~4=ENHCPU,0x40,Extended CPU Enable CONFIG4L~5=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x20,0x20,Enabled CONFIG4L~3~2=0x20,0x00,Disabled CONFIG4L~4~1=0x40,0x40,Enabled CONFIG4L~4~2=0x40,0x00,Disabled CONFIG4L~5~1=0x80,0x80,Disabled CONFIG4L~5~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-01FFF CONFIG5L~2=CP_1,0x2,Code Protect 02000-03FFF CONFIG5L~3=CP_2,0x4,Code Protect 04000-05FFF CONFIG5L~4=CP_3,0x8,Code Protect 06000-07FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EE Read Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-01FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 02000-03FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 04000-05FFF CONFIG6L~4=WRT_3,0x8,Table Write Protect 06000-07FFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x00,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EE Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-01FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 02000-03FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 04000-05FFF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 06000-07FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x00,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE_24xx05 prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F248] pgmmem=0x0 ~pgmmem=0x3FFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0xff devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x0800 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005= 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0x7,Oscillator CONFIG1H~2=OSCS,0x20,Osc. Switch Enable CONFIG1H~1~1=0x7,0x7,RC-OSC2 as RA6 CONFIG1H~1~2=0x7,0x6,HS-PLL Enabled CONFIG1H~1~3=0x7,0x5,EC-OSC2 as RA6 CONFIG1H~1~4=0x7,0x4,EC-OSC2 as Clock Out CONFIG1H~1~5=0x7,0x3,RC CONFIG1H~1~6=0x7,0x2,HS CONFIG1H~1~7=0x7,0x1,XT CONFIG1H~1~8=0x7,0x0,LP CONFIG1H~2~1=0x20,0x20,Disabled CONFIG1H~2~2=0x20,0x0,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x2,Brown Out Detect CONFIG2L~3=BODENV,0xC,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x2,0x2,Enabled CONFIG2L~2~2=0x2,0x0,Disabled CONFIG2L~3~1=0xC,0xC,2.0V CONFIG2L~3~2=0xC,0x8,2.7V CONFIG2L~3~3=0xC,0x4,4.2V CONFIG2L~3~4=0xC,0x0,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0xE,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0xE,0xE,1:128 CONFIG2H~2~2=0xE,0xC,1:64 CONFIG2H~2~3=0xE,0xA,1:32 CONFIG2H~2~4=0xE,0x8,1:16 CONFIG2H~2~5=0xE,0x6,1:8 CONFIG2H~2~6=0xE,0x4,1:4 CONFIG2H~2~7=0xE,0x2,1:2 CONFIG2H~2~8=0xE,0x0,1:1 CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x80,0x80,Disabled CONFIG4L~3~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00200-01FFF CONFIG5L~2=CP_1,0x2,Code Protect 02000-03FFF CONFIG5L~3=CP_2,0x4,Code Protect 04000-05FFF CONFIG5L~4=CP_3,0x8,Code Protect 06000-07FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EE Read Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00200-01FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 02000-03FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 04000-05FFF CONFIG6L~4=WRT_3,0x8,Table Write Protect 06000-07FFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x00,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EE Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00200-01FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 02000-03FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 04000-05FFF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 06000-07FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x00,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F2510] pgmmem=0x0 ~pgmmem=0x3FFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata= ~eedata= devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x1120 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xC,0xC,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xA,0xA,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xF,0x5,EC-Port on RA6 CONFIG1H~1~8=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xF,0x3,0011 EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xF,0x2,HS CONFIG1H~1~11=0xF,0x1,XT CONFIG1H~1~12=0xF,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x08,4.2V CONFIG2L~3~4=0x18,0x00,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=PBADEN,0x2,PortB A/D Enable CONFIG3H~3=LPT1OSC,0x04,Low Power Timer1 Osc enable CONFIG3H~4=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RB3 CONFIG3H~2~1=0x2,0x2,PORTB<4:0> configured as analog inputs on RESET CONFIG3H~2~2=0x2,0x0,PORTB<4:0> configured as digital I/O on RESET CONFIG3H~3~1=0x04,0x04,Enabled CONFIG3H~3~2=0x04,0x00,Disabled CONFIG3H~4~1=0x80,0x80,MCLR Enabled,RE3 Disabled CONFIG3H~4~2=0x80,0x00,MCLR Disabled,RE3 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=ENHCPU,0x40,Extended CPU Enable CONFIG4L~4=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x40,0x40,Enabled CONFIG4L~3~2=0x40,0x00,Disabled CONFIG4L~4~1=0x80,0x80,Disabled CONFIG4L~4~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-01FFF CONFIG5L~2=CP_1,0x2,Code Protect 02000-03FFF CONFIG5L~3=CP_2,0x4,Code Protect 04000-05FFF CONFIG5L~4=CP_3,0x8,Code Protect 06000-07FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EE Read Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-01FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 02000-03FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 04000-05FFF CONFIG6L~4=WRT_3,0x8,Table Write Protect 06000-07FFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x00,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EE Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-01FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 02000-03FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 04000-05FFF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 06000-07FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x00,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE_24xx05 prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F2515] pgmmem=0x0 ~pgmmem=0xBFFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata= ~eedata= devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x0CE0 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xC,0xC,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xA,0xA,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xF,0x5,EC-Port on RA6 CONFIG1H~1~8=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xF,0x3,0011 EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xF,0x2,HS CONFIG1H~1~11=0xF,0x1,XT CONFIG1H~1~12=0xF,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x08,4.2V CONFIG2L~3~4=0x18,0x00,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=PBADEN,0x2,PortB A/D Enable CONFIG3H~3=LPT1OSC,0x04,Low Power Timer1 Osc enable CONFIG3H~4=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RB3 CONFIG3H~2~1=0x2,0x2,PORTB<4:0> configured as analog inputs on RESET CONFIG3H~2~2=0x2,0x0,PORTB<4:0> configured as digital I/O on RESET CONFIG3H~3~1=0x04,0x04,Enabled CONFIG3H~3~2=0x04,0x00,Disabled CONFIG3H~4~1=0x80,0x80,MCLR Enabled,RE3 Disabled CONFIG3H~4~2=0x80,0x00,MCLR Disabled, RE3 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=ENHCPU,0x40,Extended CPU Enable CONFIG4L~4=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x40,0x40,Enabled CONFIG4L~3~2=0x40,0x00,Disabled CONFIG4L~4~1=0x80,0x80,Disabled CONFIG4L~4~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-03FFF CONFIG5L~2=CP_1,0x2,Code Protect 04000-07FFF CONFIG5L~3=CP_2,0x4,Code Protect 08000-0BFFF CONFIG5L~4=CP_3,0x8,Code Protect 0C000-0FFFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EE Read Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-03FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 04000-07FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 08000-0BFFF CONFIG6L~4=WRT_3,0x8,Table Write Protect 0C000-0FFFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x00,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EE Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-03FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 04000-07FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 08000-0BFFF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 0C000-0FFFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x00,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE_24xx05 prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F252] pgmmem=0x0 ~pgmmem=0x7fff cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0xff devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x0400 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0x7,Oscillator CONFIG1H~2=OSCS,0x20,Osc. Switch Enable CONFIG1H~1~1=0x7,0x7,RC-OSC2 as RA6 CONFIG1H~1~2=0x7,0x6,HS-PLL Enabled CONFIG1H~1~3=0x7,0x5,EC-OSC2 as RA6 CONFIG1H~1~4=0x7,0x4,EC-OSC2 as Clock Out CONFIG1H~1~5=0x7,0x3,RC CONFIG1H~1~6=0x7,0x2,HS CONFIG1H~1~7=0x7,0x1,XT CONFIG1H~1~8=0x7,0x0,LP CONFIG1H~2~1=0x20,0x20,Disabled CONFIG1H~2~2=0x20,0x0,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x2,Brown Out Detect CONFIG2L~3=BODENV,0xC,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x2,0x2,Enabled CONFIG2L~2~2=0x2,0x0,Disabled CONFIG2L~3~1=0xC,0xC,2.5V CONFIG2L~3~2=0xC,0x8,2.7V CONFIG2L~3~3=0xC,0x4,4.2V CONFIG2L~3~4=0xC,0x0,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0xE,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0xE,0xE,1:128 CONFIG2H~2~2=0xE,0xC,1:64 CONFIG2H~2~3=0xE,0xA,1:32 CONFIG2H~2~4=0xE,0x8,1:16 CONFIG2H~2~5=0xE,0x6,1:8 CONFIG2H~2~6=0xE,0x4,1:4 CONFIG2H~2~7=0xE,0x2,1:2 CONFIG2H~2~8=0xE,0x0,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RB3 CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x80,0x80,Disabled CONFIG4L~3~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00200-01FFF CONFIG5L~2=CP_1,0x2,Code Protect 02000-03FFF CONFIG5L~3=CP_2,0x4,Code Protect 04000-05FFF CONFIG5L~4=CP_3,0x8,Code Protect 06000-07FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EE Read Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00200-01FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 02000-03FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 04000-05FFF CONFIG6L~4=WRT_3,0x8,Table Write Protect 06000-07FFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x00,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EE Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00200-01FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 02000-03FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 04000-05FFF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 06000-07FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x00,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F2520] pgmmem=0x0 ~pgmmem=0x3FFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0xff devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFF0 id=0x1100 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xC,0xC,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xA,0xA,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xF,0x5,EC-Port on RA6 CONFIG1H~1~8=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xF,0x3,0011 EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xF,0x2,HS CONFIG1H~1~11=0xF,0x1,XT CONFIG1H~1~12=0xF,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x08,4.2V CONFIG2L~3~4=0x18,0x00,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=PBADEN,0x2,PortB A/D Enable CONFIG3H~3=LPT1OSC,0x04,Low Power Timer1 Osc enable CONFIG3H~4=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RB3 CONFIG3H~2~1=0x2,0x2,PORTB<4:0> configured as analog inputs on RESET CONFIG3H~2~2=0x2,0x0,PORTB<4:0> configured as digital I/O on RESET CONFIG3H~3~1=0x04,0x04,Enabled CONFIG3H~3~2=0x04,0x00,Disabled CONFIG3H~4~1=0x80,0x80,MCLR Enabled,RE3 Disabled CONFIG3H~4~2=0x80,0x00,MCLR Disabled,RE3 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=ENHCPU,0x40,Extended CPU Enable CONFIG4L~4=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x40,0x40,Enabled CONFIG4L~3~2=0x40,0x00,Disabled CONFIG4L~4~1=0x80,0x80,Disabled CONFIG4L~4~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-01FFF CONFIG5L~2=CP_1,0x2,Code Protect 02000-03FFF CONFIG5L~3=CP_2,0x4,Code Protect 04000-05FFF CONFIG5L~4=CP_3,0x8,Code Protect 06000-07FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EEPROM Code Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-01FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 02000-03FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 04000-05FFF CONFIG6L~4=WRT_3,0x8,Table Write Protect 06000-07FFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x00,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EEPROM Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-01FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 02000-03FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 04000-05FFF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 06000-07FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x00,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE_24xx05 prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F2525] pgmmem=0x0 ~pgmmem=0xBFFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0x3ff devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x0CC0 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xC,0xC,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xA,0xA,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xF,0x5,EC-Port on RA6 CONFIG1H~1~8=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xF,0x3,0011 EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xF,0x2,HS CONFIG1H~1~11=0xF,0x1,XT CONFIG1H~1~12=0xF,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x08,4.2V CONFIG2L~3~4=0x18,0x00,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=PBADEN,0x2,PortB A/D Enable CONFIG3H~3=LPT1OSC,0x04,Low Power Timer1 Osc enable CONFIG3H~4=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RB3 CONFIG3H~2~1=0x2,0x2,PORTB<4:0> configured as analog inputs on RESET CONFIG3H~2~2=0x2,0x0,PORTB<4:0> configured as digital I/O on RESET CONFIG3H~3~1=0x04,0x04,Enabled CONFIG3H~3~2=0x04,0x00,Disabled CONFIG3H~4~1=0x80,0x80,MCLR Enabled,RE3 Disabled CONFIG3H~4~2=0x80,0x00,MCLR Disabled, RE3 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=ENHCPU,0x40,Extended CPU Enable CONFIG4L~4=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x40,0x40,Enabled CONFIG4L~3~2=0x40,0x00,Disabled CONFIG4L~4~1=0x80,0x80,Disabled CONFIG4L~4~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-03FFF CONFIG5L~2=CP_1,0x2,Code Protect 04000-07FFF CONFIG5L~3=CP_2,0x4,Code Protect 08000-0BFFF CONFIG5L~4=CP_3,0x8,Code Protect 0C000-0FFFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EE Read Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-03FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 04000-07FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 08000-0BFFF CONFIG6L~4=WRT_3,0x8,Table Write Protect 0C000-0FFFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x00,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EE Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-03FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 04000-07FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 08000-0BFFF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 0C000-0FFFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x00,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE_24xx05 prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F2539] pgmmem=0x0 ~pgmmem=0x7fff cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0xff devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x0400 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=RESERVED1 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0x7,Oscillator CONFIG1H~2=RES1,0x20,Reserved CONFIG1H~1~1=0x7,0x6,HS-PLL Enabled CONFIG1H~1~2=0x7,0x5,EC-OSC2 as RA6 CONFIG1H~1~3=0x7,0x4,EC-OSC2 as Clock Out CONFIG1H~1~4=0x7,0x2,HS CONFIG1H~2~1=0x20,0x20,Reserved CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x2,Brown Out Detect CONFIG2L~3=BODENV,0xC,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x2,0x2,Enabled CONFIG2L~2~2=0x2,0x0,Disabled CONFIG2L~3~1=0xC,0xC,2.5V CONFIG2L~3~2=0xC,0x8,2.7V CONFIG2L~3~3=0xC,0x4,4.2V CONFIG2L~3~4=0xC,0x0,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0xE,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0xE,0xE,1:128 CONFIG2H~2~2=0xE,0xC,1:64 CONFIG2H~2~3=0xE,0xA,1:32 CONFIG2H~2~4=0xE,0x8,1:16 CONFIG2H~2~5=0xE,0x6,1:8 CONFIG2H~2~6=0xE,0x4,1:4 CONFIG2H~2~7=0xE,0x2,1:2 CONFIG2H~2~8=0xE,0x0,1:1 RESERVED1_unused=0x0 RESERVED1~1=RES1,0x1,Reserved RESERVED1~1~1=0x1,0x1,Reserved CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x80,0x80,Disabled CONFIG4L~3~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00200-01FFF CONFIG5L~2=CP_1,0x2,Code Protect 02000-03FFF CONFIG5L~3=CP_2,0x4,Code Protect 04000-05FFF CONFIG5L~4=RES1,0x8,Reserved CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Reserved CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EE Read Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00200-01FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 02000-03FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 04000-05FFF CONFIG6L~4=RES1,0x8,Reserved CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x00,Enabled CONFIG6L~4~1=0x8,0x8,Reserved CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EE Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00200-01FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 02000-03FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 04000-05FFF CONFIG7L~4=RES1,0x8,Reserved CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x00,Enabled CONFIG7L~4~1=0x8,0x8,Reserved CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F2550] pgmmem=0x0 ~pgmmem=0x7FFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0xff devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x1240 configslots=14 0x300000=CONFIG1L 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1L_unused=0x0 CONFIG1L~1=USBPLL,0x20,USB Clock Selection CONFIG1L~2=CPUDIV,0x18,CPU Sys CLK Select CONFIG1L~3=PLLDIV,0x07,OSC Select CONFIG1L~1~1=0x20,0x20,clk src from 96MHz PLL/2 CONFIG1L~1~2=0x20,0x00,clk src from OSC1/OSC2 CONFIG1L~2~1=0x18,0x18,div by 4 CONFIG1L~2~2=0x18,0x10,div by 3 CONFIG1L~2~3=0x18,0x08,div by 2 CONFIG1L~2~4=0x18,0x00,no divide CONFIG1L~3~1=0x07,0x07,div by 12 {48MHz input} CONFIG1L~3~2=0x07,0x06,div by 10 {40MHz input} CONFIG1L~3~3=0x07,0x05,div by 6 {24MHz input} CONFIG1L~3~4=0x07,0x04,div by 5 {20MHz input} CONFIG1L~3~5=0x07,0x03,div by 4 {16MHz input} CONFIG1L~3~6=0x07,0x02,div by 3 {12MHz input} CONFIG1L~3~7=0x07,0x01,div by 2 {8MHz input} CONFIG1L~3~8=0x07,0x00,no divide {4MHz input} CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xE,0xE,HS: HS+PLL, USB-HS CONFIG1H~1~2=0xE,0xC,HS: USB-HS CONFIG1H~1~3=0xF,0xB,INTOSC: USB-HS CONFIG1H~1~4=0xF,0xA,INTOSC: USB-XT CONFIG1H~1~5=0xF,0x9,INTOSC: INTOSC+CLK0{RA6}, USB-EC CONFIG1H~1~6=0xF,0x8,INTOSC: INTOSC+RA6, USB-EC CONFIG1H~1~7=0xF,0x7,EC: EC+PLL, EC+PLL+CLKO{RA6}, USB-EC CONFIG1H~1~8=0xF,0x6,EC: EC+PLL, EC+PLL+RA6, USB-EC CONFIG1H~1~9=0xF,0x5,EC: EC+CLKO{RA6}, USB-EC CONFIG1H~1~10=0xF,0x4,EC: EC+RA6, USB-EC CONFIG1H~1~11=0xE,0x2,XT: XT+PLL, USB-XT CONFIG1H~1~12=0xE,0x0,XT: USB-XT CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=VREGEN,0x20,USB Voltage Regulator CONFIG2L~2=PUT,0x1,Power Up Timer CONFIG2L~3=BODEN,0x6,Brown Out Detect CONFIG2L~4=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x20,0x20,Enabled CONFIG2L~1~2=0x20,0x00,Disabled CONFIG2L~2~1=0x1,0x1,Disabled CONFIG2L~2~2=0x1,0x0,Enabled CONFIG2L~3~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~3~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~3~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~3~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~4~1=0x18,0x18,2.0V CONFIG2L~4~2=0x18,0x10,2.7V CONFIG2L~4~3=0x18,0x08,4.2V CONFIG2L~4~4=0x18,0x00,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=PBADEN,0x2,PortB A/D Enable CONFIG3H~3=LPT1OSC,0x04,Low Power Timer1 Osc enable CONFIG3H~4=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RB3 CONFIG3H~2~1=0x2,0x2,PORTB<4:0> configured as analog inputs on RESET CONFIG3H~2~2=0x2,0x0,PORTB<4:0> configured as digital I/O on RESET CONFIG3H~3~1=0x04,0x04,Enabled CONFIG3H~3~2=0x04,0x00,Disabled CONFIG3H~4~1=0x80,0x80,MCLR Enabled,RE3 Disabled CONFIG3H~4~2=0x80,0x00,MCLR Disabled,RE3 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=ENICPORT,0x20,Dedicated In-Circuit Port {ICD/ICSP} CONFIG4L~4=ENHCPU,0x40,Extended CPU Enable CONFIG4L~5=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x20,0x20,Enabled CONFIG4L~3~2=0x20,0x00,Disabled CONFIG4L~4~1=0x40,0x40,Enabled CONFIG4L~4~2=0x40,0x00,Disabled CONFIG4L~5~1=0x80,0x80,Disabled CONFIG4L~5~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-01FFF CONFIG5L~2=CP_1,0x2,Code Protect 02000-03FFF CONFIG5L~3=CP_2,0x4,Code Protect 04000-05FFF CONFIG5L~4=CP_3,0x8,Code Protect 06000-07FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EE Read Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-01FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 02000-03FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 04000-05FFF CONFIG6L~4=WRT_3,0x8,Table Write Protect 06000-07FFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x00,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EE Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-01FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 02000-03FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 04000-05FFF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 06000-07FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x00,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE_24xx05 prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F258] pgmmem=0x0 ~pgmmem=0x7fff cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0xff devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x0840 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005= 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0x7,Oscillator CONFIG1H~2=OSCS,0x20,Osc. Switch Enable CONFIG1H~1~1=0x7,0x7,RC-OSC2 as RA6 CONFIG1H~1~2=0x7,0x6,HS-PLL Enabled CONFIG1H~1~3=0x7,0x5,EC-OSC2 as RA6 CONFIG1H~1~4=0x7,0x4,EC-OSC2 as Clock Out CONFIG1H~1~5=0x7,0x3,RC CONFIG1H~1~6=0x7,0x2,HS CONFIG1H~1~7=0x7,0x1,XT CONFIG1H~1~8=0x7,0x0,LP CONFIG1H~2~1=0x20,0x20,Disabled CONFIG1H~2~2=0x20,0x0,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x2,Brown Out Detect CONFIG2L~3=BODENV,0xC,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x2,0x2,Enabled CONFIG2L~2~2=0x2,0x0,Disabled CONFIG2L~3~1=0xC,0xC,2.0V CONFIG2L~3~2=0xC,0x8,2.7V CONFIG2L~3~3=0xC,0x4,4.2V CONFIG2L~3~4=0xC,0x0,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0xE,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0xE,0xE,1:128 CONFIG2H~2~2=0xE,0xC,1:64 CONFIG2H~2~3=0xE,0xA,1:32 CONFIG2H~2~4=0xE,0x8,1:16 CONFIG2H~2~5=0xE,0x6,1:8 CONFIG2H~2~6=0xE,0x4,1:4 CONFIG2H~2~7=0xE,0x2,1:2 CONFIG2H~2~8=0xE,0x0,1:1 CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x80,0x80,Disabled CONFIG4L~3~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00200-01FFF CONFIG5L~2=CP_1,0x2,Code Protect 02000-03FFF CONFIG5L~3=CP_2,0x4,Code Protect 04000-05FFF CONFIG5L~4=CP_3,0x8,Code Protect 06000-07FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EE Read Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00200-01FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 02000-03FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 04000-05FFF CONFIG6L~4=WRT_3,0x8,Table Write Protect 06000-07FFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x00,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EE Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00200-01FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 02000-03FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 04000-05FFF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 06000-07FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x00,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F2585] pgmmem=0x0 ~pgmmem=0xBFFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0x3ff devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x0EE0 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xC,0xC,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xA,0xA,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xF,0x5,EC-Port on RA6 CONFIG1H~1~8=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xF,0x3,EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xF,0x2,HS CONFIG1H~1~11=0xF,0x1,XT CONFIG1H~1~12=0xF,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x08,4.2V CONFIG2L~3~4=0x18,0x00,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=PBADEN,0x2,PortB A/D Enable CONFIG3H~2=LPT1OSC,0x04,Low Power Timer1 Osc enable CONFIG3H~3=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x2,0x2,PORTB<4> and <1:0> configured as analog inputs on RESET CONFIG3H~1~2=0x2,0x0,PORTB<4> and <1:0> configured as digital I/O on RESET CONFIG3H~2~1=0x04,0x04,Enabled CONFIG3H~2~2=0x04,0x00,Disabled CONFIG3H~3~1=0x80,0x80,MCLR Enabled,RE3 Disabled CONFIG3H~3~2=0x80,0x00,MCLR Disabled, RE3 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=ENHCPU,0x40,Extended CPU Enable CONFIG4L~4=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x40,0x40,Enabled CONFIG4L~3~2=0x40,0x00,Disabled CONFIG4L~4~1=0x80,0x80,Disabled CONFIG4L~4~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-03FFF CONFIG5L~2=CP_1,0x2,Code Protect 04000-07FFF CONFIG5L~3=CP_2,0x4,Code Protect 08000-0BFFF CONFIG5L~4=CP_3,0x8,Code Protect 0C000-0FFFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EE Read Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-03FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 04000-07FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 08000-0BFFF CONFIG6L~4=WRT_3,0x8,Table Write Protect 0C000-0FFFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x00,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EE Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-03FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 04000-07FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 08000-0BFFF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 0C000-0FFFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x00,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE_24xx05 prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F2586] pgmmem=0x0 ~pgmmem=0xBFFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata= ~eedata= devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x0E60 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xC,0xC,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xA,0xA,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xF,0x5,EC-Port on RA6 CONFIG1H~1~8=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xF,0x3,EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xF,0x2,HS CONFIG1H~1~11=0xF,0x1,XT CONFIG1H~1~12=0xF,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x08,4.2V CONFIG2L~3~4=0x18,0x00,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=PBADEN,0x2,PortB A/D Enable CONFIG3H~2=LPT1OSC,0x04,Low Power Timer1 Osc enable CONFIG3H~3=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x2,0x2,PORTB<4> and <1:0> configured as analog inputs on RESET CONFIG3H~1~2=0x2,0x0,PORTB<4> and <1:0> configured as digital I/O on RESET CONFIG3H~2~1=0x04,0x04,Enabled CONFIG3H~2~2=0x04,0x00,Disabled CONFIG3H~3~1=0x80,0x80,MCLR Enabled,RE3 Disabled CONFIG3H~3~2=0x80,0x00,MCLR Disabled, RE3 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=ENHCPU,0x40,Extended CPU Enable CONFIG4L~4=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x40,0x40,Enabled CONFIG4L~3~2=0x40,0x00,Disabled CONFIG4L~4~1=0x80,0x80,Disabled CONFIG4L~4~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-03FFF CONFIG5L~2=CP_1,0x2,Code Protect 04000-07FFF CONFIG5L~3=CP_2,0x4,Code Protect 08000-0BFFF CONFIG5L~4=CP_3,0x8,Code Protect 0C000-0FFFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EE Read Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-03FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 04000-07FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 08000-0BFFF CONFIG6L~4=WRT_3,0x8,Table Write Protect 0C000-0FFFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x00,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EE Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-03FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 04000-07FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 08000-0BFFF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 0C000-0FFFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x00,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F2610] pgmmem=0x0 ~pgmmem=0xFFFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata= ~eedata= devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x0CA0 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xC,0xC,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xA,0xA,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xF,0x5,EC-Port on RA6 CONFIG1H~1~8=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xF,0x3,0011 EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xF,0x2,HS CONFIG1H~1~11=0xF,0x1,XT CONFIG1H~1~12=0xF,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x08,4.2V CONFIG2L~3~4=0x18,0x00,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=PBADEN,0x2,PortB A/D Enable CONFIG3H~3=LPT1OSC,0x04,Low Power Timer1 Osc enable CONFIG3H~4=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RB3 CONFIG3H~2~1=0x2,0x2,PORTB<4:0> configured as analog inputs on RESET CONFIG3H~2~2=0x2,0x0,PORTB<4:0> configured as digital I/O on RESET CONFIG3H~3~1=0x04,0x04,Enabled CONFIG3H~3~2=0x04,0x00,Disabled CONFIG3H~4~1=0x80,0x80,MCLR Enabled,RE3 Disabled CONFIG3H~4~2=0x80,0x00,MCLR Disabled, RE3 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=ENHCPU,0x40,Extended CPU Enable CONFIG4L~4=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x40,0x40,Enabled CONFIG4L~3~2=0x40,0x00,Disabled CONFIG4L~4~1=0x80,0x80,Disabled CONFIG4L~4~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-03FFF CONFIG5L~2=CP_1,0x2,Code Protect 04000-07FFF CONFIG5L~3=CP_2,0x4,Code Protect 08000-0BFFF CONFIG5L~4=CP_3,0x8,Code Protect 0C000-0FFFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EE Read Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-03FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 04000-07FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 08000-0BFFF CONFIG6L~4=WRT_3,0x8,Table Write Protect 0C000-0FFFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x00,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EE Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-03FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 04000-07FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 08000-0BFFF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 0C000-0FFFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x00,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE_24xx05 prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F2620] pgmmem=0x0 ~pgmmem=0xFFFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0x3ff devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x0C80 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xC,0xC,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xA,0xA,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xF,0x5,EC-Port on RA6 CONFIG1H~1~8=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xF,0x3,0011 EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xF,0x2,HS CONFIG1H~1~11=0xF,0x1,XT CONFIG1H~1~12=0xF,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x08,4.2V CONFIG2L~3~4=0x18,0x00,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=PBADEN,0x2,PortB A/D Enable CONFIG3H~3=LPT1OSC,0x04,Low Power Timer1 Osc enable CONFIG3H~4=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RB3 CONFIG3H~2~1=0x2,0x2,PORTB<4:0> configured as analog inputs on RESET CONFIG3H~2~2=0x2,0x0,PORTB<4:0> configured as digital I/O on RESET CONFIG3H~3~1=0x04,0x04,Enabled CONFIG3H~3~2=0x04,0x00,Disabled CONFIG3H~4~1=0x80,0x80,MCLR Enabled,RE3 Disabled CONFIG3H~4~2=0x80,0x00,MCLR Disabled, RE3 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=ENHCPU,0x40,Extended CPU Enable CONFIG4L~4=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x40,0x40,Enabled CONFIG4L~3~2=0x40,0x00,Disabled CONFIG4L~4~1=0x80,0x80,Disabled CONFIG4L~4~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-03FFF CONFIG5L~2=CP_1,0x2,Code Protect 04000-07FFF CONFIG5L~3=CP_2,0x4,Code Protect 08000-0BFFF CONFIG5L~4=CP_3,0x8,Code Protect 0C000-0FFFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EEPROM Code Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-03FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 04000-07FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 08000-0BFFF CONFIG6L~4=WRT_3,0x8,Table Write Protect 0C000-0FFFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x00,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EEPROM Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-03FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 04000-07FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 08000-0BFFF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 0C000-0FFFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x00,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE_24xx05 prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F2680] pgmmem=0x0 ~pgmmem=0xFFFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0x3ff devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x0EC0 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xC,0xC,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xA,0xA,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xF,0x5,EC-Port on RA6 CONFIG1H~1~8=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xF,0x3,EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xF,0x2,HS CONFIG1H~1~11=0xF,0x1,XT CONFIG1H~1~12=0xF,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x08,4.2V CONFIG2L~3~4=0x18,0x00,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=PBADEN,0x2,PortB A/D Enable CONFIG3H~2=LPT1OSC,0x04,Low Power Timer1 Osc enable CONFIG3H~3=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x2,0x2,PORTB<4> and <1:0> configured as analog inputs on RESET CONFIG3H~1~2=0x2,0x0,PORTB<4> and <1:0> configured as digital I/O on RESET CONFIG3H~2~1=0x04,0x04,Enabled CONFIG3H~2~2=0x04,0x00,Disabled CONFIG3H~3~1=0x80,0x80,MCLR Enabled,RE3 Disabled CONFIG3H~3~2=0x80,0x00,MCLR Disabled, RE3 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=ENHCPU,0x40,Extended CPU Enable CONFIG4L~4=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x40,0x40,Enabled CONFIG4L~3~2=0x40,0x00,Disabled CONFIG4L~4~1=0x80,0x80,Disabled CONFIG4L~4~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-03FFF CONFIG5L~2=CP_1,0x2,Code Protect 04000-07FFF CONFIG5L~3=CP_2,0x4,Code Protect 08000-0BFFF CONFIG5L~4=CP_3,0x8,Code Protect 0C000-0FFFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EE Read Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-03FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 04000-07FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 08000-0BFFF CONFIG6L~4=WRT_3,0x8,Table Write Protect 0C000-0FFFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x00,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EE Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-03FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 04000-07FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 08000-0BFFF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 0C000-0FFFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x00,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE_24xx05 prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F2681] pgmmem=0x0 ~pgmmem=0xFFFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata= ~eedata= devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x0E40 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xC,0xC,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xA,0xA,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xF,0x5,EC-Port on RA6 CONFIG1H~1~8=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xF,0x3,EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xF,0x2,HS CONFIG1H~1~11=0xF,0x1,XT CONFIG1H~1~12=0xF,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x08,4.2V CONFIG2L~3~4=0x18,0x00,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=PBADEN,0x2,PortB A/D Enable CONFIG3H~2=LPT1OSC,0x04,Low Power Timer1 Osc enable CONFIG3H~3=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x2,0x2,PORTB<4> and <1:0> configured as analog inputs on RESET CONFIG3H~1~2=0x2,0x0,PORTB<4> and <1:0> configured as digital I/O on RESET CONFIG3H~2~1=0x04,0x04,Enabled CONFIG3H~2~2=0x04,0x00,Disabled CONFIG3H~3~1=0x80,0x80,MCLR Enabled,RE3 Disabled CONFIG3H~3~2=0x80,0x00,MCLR Disabled, RE3 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=ENHCPU,0x40,Extended CPU Enable CONFIG4L~4=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x40,0x40,Enabled CONFIG4L~3~2=0x40,0x00,Disabled CONFIG4L~4~1=0x80,0x80,Disabled CONFIG4L~4~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-03FFF CONFIG5L~2=CP_1,0x2,Code Protect 04000-07FFF CONFIG5L~3=CP_2,0x4,Code Protect 08000-0BFFF CONFIG5L~4=CP_3,0x8,Code Protect 0C000-0FFFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EE Read Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-03FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 04000-07FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 08000-0BFFF CONFIG6L~4=WRT_3,0x8,Table Write Protect 0C000-0FFFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x00,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EE Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-03FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 04000-07FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 08000-0BFFF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 0C000-0FFFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x00,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F4220] pgmmem=0x0 ~pgmmem=0x0FFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0xff devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x05A0 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xC,0xC,EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~3=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~5=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~6=0xF,0x5,EC-Port on RA6 CONFIG1H~1~7=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~8=0xF,0x2,HS CONFIG1H~1~9=0xF,0x1,XT CONFIG1H~1~10=0xF,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x2,Brown Out Detect CONFIG2L~3=BODENV,0xC,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x2,0x2,Enabled CONFIG2L~2~2=0x2,0x0,Disabled CONFIG2L~3~1=0xC,0xC,2.0V CONFIG2L~3~2=0xC,0x8,2.7V CONFIG2L~3~3=0xC,0x4,4.2V CONFIG2L~3~4=0xC,0x0,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=PBADEN,0x2,PortB A/D Enable CONFIG3H~3=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RB3 CONFIG3H~2~1=0x2,0x2,PORTB<4:0> configured as analog inputs on RESET CONFIG3H~2~2=0x2,0x0,PORTB<4:0> configured as digital I/O on RESET CONFIG3H~3~1=0x80,0x80,MCLR Enabled,RE3 Disabled CONFIG3H~3~2=0x80,0x00,MCLR Disabled, RE3 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x80,0x80,Disabled CONFIG4L~3~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 000200-0007FF CONFIG5L~2=CP_1,0x2,Code Protect 000800-000FFF CONFIG5L~3=CP_2,0x4,Code Protect 001000-0017FF CONFIG5L~4=CP_3,0x8,Code Protect 001800-001FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EEPROM Code Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00200-007FF CONFIG6L~2=WRT_1,0x2,Table Write Protect 00800-00FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 01000-017FF CONFIG6L~4=WRT_3,0x8,Table Write Protect 01800-01FFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x00,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EEPROM Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00200-007FF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 00800-00FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 01000-017FF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 01800-01FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x00,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F4320] pgmmem=0x0 ~pgmmem=0x1FFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0xff devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x0520 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xC,0xC,EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~3=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~5=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~6=0xF,0x5,EC-Port on RA6 CONFIG1H~1~7=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~8=0xF,0x2,HS CONFIG1H~1~9=0xF,0x1,XT CONFIG1H~1~10=0xF,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x2,Brown Out Detect CONFIG2L~3=BODENV,0xC,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x2,0x2,Enabled CONFIG2L~2~2=0x2,0x0,Disabled CONFIG2L~3~1=0xC,0xC,2.0V CONFIG2L~3~2=0xC,0x8,2.7V CONFIG2L~3~3=0xC,0x4,4.2V CONFIG2L~3~4=0xC,0x0,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=PBADEN,0x2,PortB A/D Enable CONFIG3H~3=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RB3 CONFIG3H~2~1=0x2,0x2,PORTB<4:0> configured as analog inputs on RESET CONFIG3H~2~2=0x2,0x0,PORTB<4:0> configured as digital I/O on RESET CONFIG3H~3~1=0x80,0x80,MCLR Enabled,RE3 Disabled CONFIG3H~3~2=0x80,0x00,MCLR Disabled, RE3 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x80,0x80,Disabled CONFIG4L~3~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 000200-0007FF CONFIG5L~2=CP_1,0x2,Code Protect 000800-000FFF CONFIG5L~3=CP_2,0x4,Code Protect 001000-0017FF CONFIG5L~4=CP_3,0x8,Code Protect 001800-001FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EEPROM Code Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00200-007FF CONFIG6L~2=WRT_1,0x2,Table Write Protect 00800-00FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 01000-017FF CONFIG6L~4=WRT_3,0x8,Table Write Protect 01800-01FFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x00,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EEPROM Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00200-007FF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 00800-00FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 01000-017FF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 01800-01FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x00,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F4439] pgmmem=0x0 ~pgmmem=0x3FFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0xff devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x04A0 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=RESERVED1 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0x7,Oscillator CONFIG1H~2=RES1,0x20,Reserved CONFIG1H~1~1=0x7,0x6,HS-PLL Enabled CONFIG1H~1~2=0x7,0x5,EC-OSC2 as RA6 CONFIG1H~1~3=0x7,0x4,EC-OSC2 as Clock Out CONFIG1H~1~4=0x7,0x2,HS CONFIG1H~2~1=0x20,0x20,Reserved CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x2,Brown Out Detect CONFIG2L~3=BODENV,0xC,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x2,0x2,Enabled CONFIG2L~2~2=0x2,0x0,Disabled CONFIG2L~3~1=0xC,0xC,2.5V CONFIG2L~3~2=0xC,0x8,2.7V CONFIG2L~3~3=0xC,0x4,4.2V CONFIG2L~3~4=0xC,0x0,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0xE,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0xE,0xE,1:128 CONFIG2H~2~2=0xE,0xC,1:64 CONFIG2H~2~3=0xE,0xA,1:32 CONFIG2H~2~4=0xE,0x8,1:16 CONFIG2H~2~5=0xE,0x6,1:8 CONFIG2H~2~6=0xE,0x4,1:4 CONFIG2H~2~7=0xE,0x2,1:2 CONFIG2H~2~8=0xE,0x0,1:1 RESERVED1_unused=0x0 RESERVED1~1=RES1,0x1,Reserved RESERVED1~1~1=0x1,0x1,Reserved CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x80,0x80,Disabled CONFIG4L~3~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00200-01FFF CONFIG5L~2=CP_1,0x2,Code Protect 02000-03FFF CONFIG5L~3=CP_2,0x4,Code Protect 04000-05FFF CONFIG5L~4=RES1,0x8,Reserved CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Reserved CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EE Read Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00200-01FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 02000-03FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 04000-05FFF CONFIG6L~4=RES1,0x8,Reserved CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x00,Enabled CONFIG6L~4~1=0x8,0x8,Reserved CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EE Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00200-01FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 02000-03FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 04000-05FFF CONFIG7L~4=RES1,0x8,Reserved CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x00,Enabled CONFIG7L~4~1=0x8,0x8,Reserved CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F4455] pgmmem=0x0 ~pgmmem=0x5FFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0xff devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x1220 configslots=14 0x300000=CONFIG1L 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1L_unused=0x0 CONFIG1L~1=USBPLL,0x20,USB Clock Selection CONFIG1L~2=CPUDIV,0x18,CPU Sys CLK Select CONFIG1L~3=PLLDIV,0x07,OSC Select CONFIG1L~1~1=0x20,0x20,clk src from 96MHz PLL/2 CONFIG1L~1~2=0x20,0x00,clk src from OSC1/OSC2 CONFIG1L~2~1=0x18,0x18,div by 4 CONFIG1L~2~2=0x18,0x10,div by 3 CONFIG1L~2~3=0x18,0x08,div by 2 CONFIG1L~2~4=0x18,0x00,no divide CONFIG1L~3~1=0x07,0x07,div by 12 {48MHz input} CONFIG1L~3~2=0x07,0x06,div by 10 {40MHz input} CONFIG1L~3~3=0x07,0x05,div by 6 {24MHz input} CONFIG1L~3~4=0x07,0x04,div by 5 {20MHz input} CONFIG1L~3~5=0x07,0x03,div by 4 {16MHz input} CONFIG1L~3~6=0x07,0x02,div by 3 {12MHz input} CONFIG1L~3~7=0x07,0x01,div by 2 {8MHz input} CONFIG1L~3~8=0x07,0x00,no divide {4MHz input} CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xE,0xE,HS: HS+PLL, USB-HS CONFIG1H~1~2=0xE,0xC,HS: USB-HS CONFIG1H~1~3=0xF,0xB,INTOSC: USB-HS CONFIG1H~1~4=0xF,0xA,INTOSC: USB-XT CONFIG1H~1~5=0xF,0x9,INTOSC: INTOSC+CLK0{RA6}, USB-EC CONFIG1H~1~6=0xF,0x8,INTOSC: INTOSC+RA6, USB-EC CONFIG1H~1~7=0xF,0x7,EC: EC+PLL, EC+PLL+CLKO{RA6}, USB-EC CONFIG1H~1~8=0xF,0x6,EC: EC+PLL, EC+PLL+RA6, USB-EC CONFIG1H~1~9=0xF,0x5,EC: EC+CLKO{RA6}, USB-EC CONFIG1H~1~10=0xF,0x4,EC: EC+RA6, USB-EC CONFIG1H~1~11=0xE,0x2,XT: XT+PLL, USB-XT CONFIG1H~1~12=0xE,0x0,XT: USB-XT CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=VREGEN,0x20,USB Voltage Regulator CONFIG2L~2=PUT,0x1,Power Up Timer CONFIG2L~3=BODEN,0x6,Brown Out Detect CONFIG2L~4=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x20,0x20,Enabled CONFIG2L~1~2=0x20,0x00,Disabled CONFIG2L~2~1=0x1,0x1,Disabled CONFIG2L~2~2=0x1,0x0,Enabled CONFIG2L~3~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~3~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~3~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~3~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~4~1=0x18,0x18,2.0V CONFIG2L~4~2=0x18,0x10,2.7V CONFIG2L~4~3=0x18,0x08,4.2V CONFIG2L~4~4=0x18,0x00,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=PBADEN,0x2,PortB A/D Enable CONFIG3H~3=LPT1OSC,0x04,Low Power Timer1 Osc enable CONFIG3H~4=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RB3 CONFIG3H~2~1=0x2,0x2,PORTB<4:0> configured as analog inputs on RESET CONFIG3H~2~2=0x2,0x0,PORTB<4:0> configured as digital I/O on RESET CONFIG3H~3~1=0x04,0x04,Enabled CONFIG3H~3~2=0x04,0x00,Disabled CONFIG3H~4~1=0x80,0x80,MCLR Enabled,RE3 Disabled CONFIG3H~4~2=0x80,0x00,MCLR Disabled,RE3 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=ENICPORT,0x20,Dedicated In-Circuit Port {ICD/ICSP} CONFIG4L~4=ENHCPU,0x40,Extended CPU Enable CONFIG4L~5=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x20,0x20,Enabled CONFIG4L~3~2=0x20,0x00,Disabled CONFIG4L~4~1=0x40,0x40,Enabled CONFIG4L~4~2=0x40,0x00,Disabled CONFIG4L~5~1=0x80,0x80,Disabled CONFIG4L~5~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-01FFF CONFIG5L~2=CP_1,0x2,Code Protect 02000-03FFF CONFIG5L~3=CP_2,0x4,Code Protect 04000-05FFF CONFIG5L~4=CP_3,0x8,Code Protect 06000-07FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EE Read Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-01FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 02000-03FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 04000-05FFF CONFIG6L~4=WRT_3,0x8,Table Write Protect 06000-07FFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x00,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EE Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-01FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 02000-03FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 04000-05FFF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 06000-07FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x00,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE_24xx05 prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F448] pgmmem=0x0 ~pgmmem=0x3FFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0xff devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x0820 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005= 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0x7,Oscillator CONFIG1H~2=OSCS,0x20,Osc. Switch Enable CONFIG1H~1~1=0x7,0x7,RC-OSC2 as RA6 CONFIG1H~1~2=0x7,0x6,HS-PLL Enabled CONFIG1H~1~3=0x7,0x5,EC-OSC2 as RA6 CONFIG1H~1~4=0x7,0x4,EC-OSC2 as Clock Out CONFIG1H~1~5=0x7,0x3,RC CONFIG1H~1~6=0x7,0x2,HS CONFIG1H~1~7=0x7,0x1,XT CONFIG1H~1~8=0x7,0x0,LP CONFIG1H~2~1=0x20,0x20,Disabled CONFIG1H~2~2=0x20,0x0,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x2,Brown Out Detect CONFIG2L~3=BODENV,0xC,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x2,0x2,Enabled CONFIG2L~2~2=0x2,0x0,Disabled CONFIG2L~3~1=0xC,0xC,2.0V CONFIG2L~3~2=0xC,0x8,2.7V CONFIG2L~3~3=0xC,0x4,4.2V CONFIG2L~3~4=0xC,0x0,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0xE,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0xE,0xE,1:128 CONFIG2H~2~2=0xE,0xC,1:64 CONFIG2H~2~3=0xE,0xA,1:32 CONFIG2H~2~4=0xE,0x8,1:16 CONFIG2H~2~5=0xE,0x6,1:8 CONFIG2H~2~6=0xE,0x4,1:4 CONFIG2H~2~7=0xE,0x2,1:2 CONFIG2H~2~8=0xE,0x0,1:1 CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x80,0x80,Disabled CONFIG4L~3~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00200-01FFF CONFIG5L~2=CP_1,0x2,Code Protect 02000-03FFF CONFIG5L~3=CP_2,0x4,Code Protect 04000-05FFF CONFIG5L~4=CP_3,0x8,Code Protect 06000-07FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EE Read Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00200-01FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 02000-03FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 04000-05FFF CONFIG6L~4=WRT_3,0x8,Table Write Protect 06000-07FFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x00,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EE Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00200-01FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 02000-03FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 04000-05FFF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 06000-07FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x00,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F4510] pgmmem=0x0 ~pgmmem=0x7FFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata= ~eedata= devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x10A0 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xC,0xC,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xA,0xA,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xF,0x5,EC-Port on RA6 CONFIG1H~1~8=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xF,0x3,0011 EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xF,0x2,HS CONFIG1H~1~11=0xF,0x1,XT CONFIG1H~1~12=0xF,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x08,4.2V CONFIG2L~3~4=0x18,0x00,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=PBADEN,0x2,PortB A/D Enable CONFIG3H~3=LPT1OSC,0x04,Low Power Timer1 Osc enable CONFIG3H~4=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RB3 CONFIG3H~2~1=0x2,0x2,PORTB<4:0> configured as analog inputs on RESET CONFIG3H~2~2=0x2,0x0,PORTB<4:0> configured as digital I/O on RESET CONFIG3H~3~1=0x04,0x04,Enabled CONFIG3H~3~2=0x04,0x00,Disabled CONFIG3H~4~1=0x80,0x80,MCLR Enabled,RE3 Disabled CONFIG3H~4~2=0x80,0x00,MCLR Disabled,RE3 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=ENHCPU,0x40,Extended CPU Enable CONFIG4L~4=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x40,0x40,Enabled CONFIG4L~3~2=0x40,0x00,Disabled CONFIG4L~4~1=0x80,0x80,Disabled CONFIG4L~4~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-01FFF CONFIG5L~2=CP_1,0x2,Code Protect 02000-03FFF CONFIG5L~3=CP_2,0x4,Code Protect 04000-05FFF CONFIG5L~4=CP_3,0x8,Code Protect 06000-07FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EE Read Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-01FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 02000-03FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 04000-05FFF CONFIG6L~4=WRT_3,0x8,Table Write Protect 06000-07FFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x00,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EE Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-01FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 02000-03FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 04000-05FFF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 06000-07FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x00,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE_24xx05 prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F4515] pgmmem=0x0 ~pgmmem=0xBFFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata= ~eedata= devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x0C60 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xC,0xC,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xA,0xA,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xF,0x5,EC-Port on RA6 CONFIG1H~1~8=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xF,0x3,0011 EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xF,0x2,HS CONFIG1H~1~11=0xF,0x1,XT CONFIG1H~1~12=0xF,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x08,4.2V CONFIG2L~3~4=0x18,0x00,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=PBADEN,0x2,PortB A/D Enable CONFIG3H~3=LPT1OSC,0x04,Low Power Timer1 Osc enable CONFIG3H~4=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RB3 CONFIG3H~2~1=0x2,0x2,PORTB<4:0> configured as analog inputs on RESET CONFIG3H~2~2=0x2,0x0,PORTB<4:0> configured as digital I/O on RESET CONFIG3H~3~1=0x04,0x04,Enabled CONFIG3H~3~2=0x04,0x00,Disabled CONFIG3H~4~1=0x80,0x80,MCLR Enabled,RE3 Disabled CONFIG3H~4~2=0x80,0x00,MCLR Disabled, RE3 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=ENHCPU,0x40,Extended CPU Enable CONFIG4L~4=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x40,0x40,Enabled CONFIG4L~3~2=0x40,0x00,Disabled CONFIG4L~4~1=0x80,0x80,Disabled CONFIG4L~4~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-03FFF CONFIG5L~2=CP_1,0x2,Code Protect 04000-07FFF CONFIG5L~3=CP_2,0x4,Code Protect 08000-0BFFF CONFIG5L~4=CP_3,0x8,Code Protect 0C000-0FFFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EE Read Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-03FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 04000-07FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 08000-0BFFF CONFIG6L~4=WRT_3,0x8,Table Write Protect 0C000-0FFFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x00,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EE Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-03FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 04000-07FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 08000-0BFFF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 0C000-0FFFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x00,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE_24xx05 prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F452] pgmmem=0x0 ~pgmmem=0x7fff cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0xff devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x0420 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0x7,Oscillator CONFIG1H~2=OSCS,0x20,Osc. Switch Enable CONFIG1H~1~1=0x7,0x7,RC-OSC2 as RA6 CONFIG1H~1~2=0x7,0x6,HS-PLL Enabled CONFIG1H~1~3=0x7,0x5,EC-OSC2 as RA6 CONFIG1H~1~4=0x7,0x4,EC-OSC2 as Clock Out CONFIG1H~1~5=0x7,0x3,RC CONFIG1H~1~6=0x7,0x2,HS CONFIG1H~1~7=0x7,0x1,XT CONFIG1H~1~8=0x7,0x0,LP CONFIG1H~2~1=0x20,0x20,Disabled CONFIG1H~2~2=0x20,0x0,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x2,Brown Out Detect CONFIG2L~3=BODENV,0xC,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x2,0x2,Enabled CONFIG2L~2~2=0x2,0x0,Disabled CONFIG2L~3~1=0xC,0xC,2.5V CONFIG2L~3~2=0xC,0x8,2.7V CONFIG2L~3~3=0xC,0x4,4.2V CONFIG2L~3~4=0xC,0x0,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0xE,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0xE,0xE,1:128 CONFIG2H~2~2=0xE,0xC,1:64 CONFIG2H~2~3=0xE,0xA,1:32 CONFIG2H~2~4=0xE,0x8,1:16 CONFIG2H~2~5=0xE,0x6,1:8 CONFIG2H~2~6=0xE,0x4,1:4 CONFIG2H~2~7=0xE,0x2,1:2 CONFIG2H~2~8=0xE,0x0,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RB3 CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x80,0x80,Disabled CONFIG4L~3~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00200-01FFF CONFIG5L~2=CP_1,0x2,Code Protect 02000-03FFF CONFIG5L~3=CP_2,0x4,Code Protect 04000-05FFF CONFIG5L~4=CP_3,0x8,Code Protect 06000-07FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EE Read Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00200-01FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 02000-03FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 04000-05FFF CONFIG6L~4=WRT_3,0x8,Table Write Protect 06000-07FFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x00,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EE Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00200-01FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 02000-03FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 04000-05FFF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 06000-07FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x00,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F4520] pgmmem=0x0 ~pgmmem=0x7FFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0xff devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFF0 id=0x1080 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xC,0xC,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xA,0xA,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xF,0x5,EC-Port on RA6 CONFIG1H~1~8=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xF,0x3,0011 EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xF,0x2,HS CONFIG1H~1~11=0xF,0x1,XT CONFIG1H~1~12=0xF,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x08,4.2V CONFIG2L~3~4=0x18,0x00,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=PBADEN,0x2,PortB A/D Enable CONFIG3H~3=LPT1OSC,0x04,Low Power Timer1 Osc enable CONFIG3H~4=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RB3 CONFIG3H~2~1=0x2,0x2,PORTB<4:0> configured as analog inputs on RESET CONFIG3H~2~2=0x2,0x0,PORTB<4:0> configured as digital I/O on RESET CONFIG3H~3~1=0x04,0x04,Enabled CONFIG3H~3~2=0x04,0x00,Disabled CONFIG3H~4~1=0x80,0x80,MCLR Enabled,RE3 Disabled CONFIG3H~4~2=0x80,0x00,MCLR Disabled,RE3 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=ENHCPU,0x40,Extended CPU Enable CONFIG4L~4=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x40,0x40,Enabled CONFIG4L~3~2=0x40,0x00,Disabled CONFIG4L~4~1=0x80,0x80,Disabled CONFIG4L~4~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-01FFF CONFIG5L~2=CP_1,0x2,Code Protect 02000-03FFF CONFIG5L~3=CP_2,0x4,Code Protect 04000-05FFF CONFIG5L~4=CP_3,0x8,Code Protect 06000-07FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EEPROM Code Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-01FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 02000-03FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 04000-05FFF CONFIG6L~4=WRT_3,0x8,Table Write Protect 06000-07FFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x00,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EEPROM Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-01FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 02000-03FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 04000-05FFF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 06000-07FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x00,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE_24xx05 prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F4525] pgmmem=0x0 ~pgmmem=0xBFFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0x3ff devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x0C40 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xC,0xC,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xA,0xA,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xF,0x5,EC-Port on RA6 CONFIG1H~1~8=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xF,0x3,0011 EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xF,0x2,HS CONFIG1H~1~11=0xF,0x1,XT CONFIG1H~1~12=0xF,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x08,4.2V CONFIG2L~3~4=0x18,0x00,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=PBADEN,0x2,PortB A/D Enable CONFIG3H~3=LPT1OSC,0x04,Low Power Timer1 Osc enable CONFIG3H~4=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RB3 CONFIG3H~2~1=0x2,0x2,PORTB<4:0> configured as analog inputs on RESET CONFIG3H~2~2=0x2,0x0,PORTB<4:0> configured as digital I/O on RESET CONFIG3H~3~1=0x04,0x04,Enabled CONFIG3H~3~2=0x04,0x00,Disabled CONFIG3H~4~1=0x80,0x80,MCLR Enabled,RE3 Disabled CONFIG3H~4~2=0x80,0x00,MCLR Disabled, RE3 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=ENHCPU,0x40,Extended CPU Enable CONFIG4L~4=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x40,0x40,Enabled CONFIG4L~3~2=0x40,0x00,Disabled CONFIG4L~4~1=0x80,0x80,Disabled CONFIG4L~4~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-03FFF CONFIG5L~2=CP_1,0x2,Code Protect 04000-07FFF CONFIG5L~3=CP_2,0x4,Code Protect 08000-0BFFF CONFIG5L~4=CP_3,0x8,Code Protect 0C000-0FFFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EE Read Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-03FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 04000-07FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 08000-0BFFF CONFIG6L~4=WRT_3,0x8,Table Write Protect 0C000-0FFFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x00,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EE Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-03FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 04000-07FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 08000-0BFFF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 0C000-0FFFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x00,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE_24xx05 prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F4539] pgmmem=0x0 ~pgmmem=0x7fff cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0xff devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x0420 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=RESERVED1 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0x7,Oscillator CONFIG1H~2=RES1,0x20,Reserved CONFIG1H~1~1=0x7,0x6,HS-PLL Enabled CONFIG1H~1~2=0x7,0x5,EC-OSC2 as RA6 CONFIG1H~1~3=0x7,0x4,EC-OSC2 as Clock Out CONFIG1H~1~4=0x7,0x2,HS CONFIG1H~2~1=0x20,0x20,Reserved CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x2,Brown Out Detect CONFIG2L~3=BODENV,0xC,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x2,0x2,Enabled CONFIG2L~2~2=0x2,0x0,Disabled CONFIG2L~3~1=0xC,0xC,2.5V CONFIG2L~3~2=0xC,0x8,2.7V CONFIG2L~3~3=0xC,0x4,4.2V CONFIG2L~3~4=0xC,0x0,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0xE,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0xE,0xE,1:128 CONFIG2H~2~2=0xE,0xC,1:64 CONFIG2H~2~3=0xE,0xA,1:32 CONFIG2H~2~4=0xE,0x8,1:16 CONFIG2H~2~5=0xE,0x6,1:8 CONFIG2H~2~6=0xE,0x4,1:4 CONFIG2H~2~7=0xE,0x2,1:2 CONFIG2H~2~8=0xE,0x0,1:1 RESERVED1_unused=0x0 RESERVED1~1=RES1,0x1,Reserved RESERVED1~1~1=0x1,0x1,Reserved CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x80,0x80,Disabled CONFIG4L~3~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00200-01FFF CONFIG5L~2=CP_1,0x2,Code Protect 02000-03FFF CONFIG5L~3=CP_2,0x4,Code Protect 04000-05FFF CONFIG5L~4=RES1,0x8,Reserved CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Reserved CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EE Read Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00200-01FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 02000-03FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 04000-05FFF CONFIG6L~4=RES1,0x8,Reserved CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x00,Enabled CONFIG6L~4~1=0x8,0x8,Reserved CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EE Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00200-01FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 02000-03FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 04000-05FFF CONFIG7L~4=RES1,0x8,Reserved CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x00,Enabled CONFIG7L~4~1=0x8,0x8,Reserved CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F4550] pgmmem=0x0 ~pgmmem=0x7FFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0xff devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x1200 configslots=14 0x300000=CONFIG1L 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1L_unused=0x0 CONFIG1L~1=USBPLL,0x20,USB Clock Selection CONFIG1L~2=CPUDIV,0x18,CPU Sys CLK Select CONFIG1L~3=PLLDIV,0x07,OSC Select CONFIG1L~1~1=0x20,0x20,clk src from 96MHz PLL/2 CONFIG1L~1~2=0x20,0x00,clk src from OSC1/OSC2 CONFIG1L~2~1=0x18,0x18,div by 4 CONFIG1L~2~2=0x18,0x10,div by 3 CONFIG1L~2~3=0x18,0x08,div by 2 CONFIG1L~2~4=0x18,0x00,no divide CONFIG1L~3~1=0x07,0x07,div by 12 {48MHz input} CONFIG1L~3~2=0x07,0x06,div by 10 {40MHz input} CONFIG1L~3~3=0x07,0x05,div by 6 {24MHz input} CONFIG1L~3~4=0x07,0x04,div by 5 {20MHz input} CONFIG1L~3~5=0x07,0x03,div by 4 {16MHz input} CONFIG1L~3~6=0x07,0x02,div by 3 {12MHz input} CONFIG1L~3~7=0x07,0x01,div by 2 {8MHz input} CONFIG1L~3~8=0x07,0x00,no divide {4MHz input} CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xE,0xE,HS: HS+PLL, USB-HS CONFIG1H~1~2=0xE,0xC,HS: USB-HS CONFIG1H~1~3=0xF,0xB,INTOSC: USB-HS CONFIG1H~1~4=0xF,0xA,INTOSC: USB-XT CONFIG1H~1~5=0xF,0x9,INTOSC: INTOSC+CLK0{RA6}, USB-EC CONFIG1H~1~6=0xF,0x8,INTOSC: INTOSC+RA6, USB-EC CONFIG1H~1~7=0xF,0x7,EC: EC+PLL, EC+PLL+CLKO{RA6}, USB-EC CONFIG1H~1~8=0xF,0x6,EC: EC+PLL, EC+PLL+RA6, USB-EC CONFIG1H~1~9=0xF,0x5,EC: EC+CLKO{RA6}, USB-EC CONFIG1H~1~10=0xF,0x4,EC: EC+RA6, USB-EC CONFIG1H~1~11=0xE,0x2,XT: XT+PLL, USB-XT CONFIG1H~1~12=0xE,0x0,XT: USB-XT CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=VREGEN,0x20,USB Voltage Regulator CONFIG2L~2=PUT,0x1,Power Up Timer CONFIG2L~3=BODEN,0x6,Brown Out Detect CONFIG2L~4=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x20,0x20,Enabled CONFIG2L~1~2=0x20,0x00,Disabled CONFIG2L~2~1=0x1,0x1,Disabled CONFIG2L~2~2=0x1,0x0,Enabled CONFIG2L~3~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~3~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~3~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~3~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~4~1=0x18,0x18,2.0V CONFIG2L~4~2=0x18,0x10,2.7V CONFIG2L~4~3=0x18,0x08,4.2V CONFIG2L~4~4=0x18,0x00,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=PBADEN,0x2,PortB A/D Enable CONFIG3H~3=LPT1OSC,0x04,Low Power Timer1 Osc enable CONFIG3H~4=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RB3 CONFIG3H~2~1=0x2,0x2,PORTB<4:0> configured as analog inputs on RESET CONFIG3H~2~2=0x2,0x0,PORTB<4:0> configured as digital I/O on RESET CONFIG3H~3~1=0x04,0x04,Enabled CONFIG3H~3~2=0x04,0x00,Disabled CONFIG3H~4~1=0x80,0x80,MCLR Enabled,RE3 Disabled CONFIG3H~4~2=0x80,0x00,MCLR Disabled,RE3 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=ENICPORT,0x20,Dedicated In-Circuit Port {ICD/ICSP} CONFIG4L~4=ENHCPU,0x40,Extended CPU Enable CONFIG4L~5=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x20,0x20,Enabled CONFIG4L~3~2=0x20,0x00,Disabled CONFIG4L~4~1=0x40,0x40,Enabled CONFIG4L~4~2=0x40,0x00,Disabled CONFIG4L~5~1=0x80,0x80,Disabled CONFIG4L~5~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-01FFF CONFIG5L~2=CP_1,0x2,Code Protect 02000-03FFF CONFIG5L~3=CP_2,0x4,Code Protect 04000-05FFF CONFIG5L~4=CP_3,0x8,Code Protect 06000-07FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EE Read Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-01FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 02000-03FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 04000-05FFF CONFIG6L~4=WRT_3,0x8,Table Write Protect 06000-07FFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x00,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EE Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-01FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 02000-03FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 04000-05FFF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 06000-07FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x00,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE_24xx05 prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F458] pgmmem=0x0 ~pgmmem=0x7fff cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0xff devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x0860 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005= 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0x7,Oscillator CONFIG1H~2=OSCS,0x20,Osc. Switch Enable CONFIG1H~1~1=0x7,0x7,RC-OSC2 as RA6 CONFIG1H~1~2=0x7,0x6,HS-PLL Enabled CONFIG1H~1~3=0x7,0x5,EC-OSC2 as RA6 CONFIG1H~1~4=0x7,0x4,EC-OSC2 as Clock Out CONFIG1H~1~5=0x7,0x3,RC CONFIG1H~1~6=0x7,0x2,HS CONFIG1H~1~7=0x7,0x1,XT CONFIG1H~1~8=0x7,0x0,LP CONFIG1H~2~1=0x20,0x20,Disabled CONFIG1H~2~2=0x20,0x0,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x2,Brown Out Detect CONFIG2L~3=BODENV,0xC,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x2,0x2,Enabled CONFIG2L~2~2=0x2,0x0,Disabled CONFIG2L~3~1=0xC,0xC,2.0V CONFIG2L~3~2=0xC,0x8,2.7V CONFIG2L~3~3=0xC,0x4,4.2V CONFIG2L~3~4=0xC,0x0,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0xE,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0xE,0xE,1:128 CONFIG2H~2~2=0xE,0xC,1:64 CONFIG2H~2~3=0xE,0xA,1:32 CONFIG2H~2~4=0xE,0x8,1:16 CONFIG2H~2~5=0xE,0x6,1:8 CONFIG2H~2~6=0xE,0x4,1:4 CONFIG2H~2~7=0xE,0x2,1:2 CONFIG2H~2~8=0xE,0x0,1:1 CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x80,0x80,Disabled CONFIG4L~3~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00200-01FFF CONFIG5L~2=CP_1,0x2,Code Protect 02000-03FFF CONFIG5L~3=CP_2,0x4,Code Protect 04000-05FFF CONFIG5L~4=CP_3,0x8,Code Protect 06000-07FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EE Read Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00200-01FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 02000-03FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 04000-05FFF CONFIG6L~4=WRT_3,0x8,Table Write Protect 06000-07FFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x00,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EE Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00200-01FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 02000-03FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 04000-05FFF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 06000-07FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x00,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F4585] pgmmem=0x0 ~pgmmem=0xBFFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0x3ff devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x0EA0 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xC,0xC,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xA,0xA,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xF,0x5,EC-Port on RA6 CONFIG1H~1~8=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xF,0x3,EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xF,0x2,HS CONFIG1H~1~11=0xF,0x1,XT CONFIG1H~1~12=0xF,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x08,4.2V CONFIG2L~3~4=0x18,0x00,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=PBADEN,0x2,PortB A/D Enable CONFIG3H~2=LPT1OSC,0x04,Low Power Timer1 Osc enable CONFIG3H~3=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x2,0x2,PORTB<4> and <1:0> configured as analog inputs on RESET CONFIG3H~1~2=0x2,0x0,PORTB<4> and <1:0> configured as digital I/O on RESET CONFIG3H~2~1=0x04,0x04,Enabled CONFIG3H~2~2=0x04,0x00,Disabled CONFIG3H~3~1=0x80,0x80,MCLR Enabled,RE3 Disabled CONFIG3H~3~2=0x80,0x00,MCLR Disabled, RE3 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=ENHCPU,0x40,Extended CPU Enable CONFIG4L~4=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x40,0x40,Enabled CONFIG4L~3~2=0x40,0x00,Disabled CONFIG4L~4~1=0x80,0x80,Disabled CONFIG4L~4~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-03FFF CONFIG5L~2=CP_1,0x2,Code Protect 04000-07FFF CONFIG5L~3=CP_2,0x4,Code Protect 08000-0BFFF CONFIG5L~4=CP_3,0x8,Code Protect 0C000-0FFFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EE Read Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-03FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 04000-07FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 08000-0BFFF CONFIG6L~4=WRT_3,0x8,Table Write Protect 0C000-0FFFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x00,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EE Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-03FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 04000-07FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 08000-0BFFF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 0C000-0FFFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x00,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE_24xx05 prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F4586] pgmmem=0x0 ~pgmmem=0xBFFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata= ~eedata= devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x0E20 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xC,0xC,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xA,0xA,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xF,0x5,EC-Port on RA6 CONFIG1H~1~8=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xF,0x3,EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xF,0x2,HS CONFIG1H~1~11=0xF,0x1,XT CONFIG1H~1~12=0xF,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x08,4.2V CONFIG2L~3~4=0x18,0x00,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=PBADEN,0x2,PortB A/D Enable CONFIG3H~2=LPT1OSC,0x04,Low Power Timer1 Osc enable CONFIG3H~3=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x2,0x2,PORTB<4> and <1:0> configured as analog inputs on RESET CONFIG3H~1~2=0x2,0x0,PORTB<4> and <1:0> configured as digital I/O on RESET CONFIG3H~2~1=0x04,0x04,Enabled CONFIG3H~2~2=0x04,0x00,Disabled CONFIG3H~3~1=0x80,0x80,MCLR Enabled,RE3 Disabled CONFIG3H~3~2=0x80,0x00,MCLR Disabled, RE3 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=ENHCPU,0x40,Extended CPU Enable CONFIG4L~4=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x40,0x40,Enabled CONFIG4L~3~2=0x40,0x00,Disabled CONFIG4L~4~1=0x80,0x80,Disabled CONFIG4L~4~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-03FFF CONFIG5L~2=CP_1,0x2,Code Protect 04000-07FFF CONFIG5L~3=CP_2,0x4,Code Protect 08000-0BFFF CONFIG5L~4=CP_3,0x8,Code Protect 0C000-0FFFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EE Read Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-03FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 04000-07FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 08000-0BFFF CONFIG6L~4=WRT_3,0x8,Table Write Protect 0C000-0FFFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x00,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EE Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-03FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 04000-07FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 08000-0BFFF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 0C000-0FFFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x00,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F4610] pgmmem=0x0 ~pgmmem=0xFFFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata= ~eedata= devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x0C20 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xC,0xC,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xA,0xA,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xF,0x5,EC-Port on RA6 CONFIG1H~1~8=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xF,0x3,0011 EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xF,0x2,HS CONFIG1H~1~11=0xF,0x1,XT CONFIG1H~1~12=0xF,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x08,4.2V CONFIG2L~3~4=0x18,0x00,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=PBADEN,0x2,PortB A/D Enable CONFIG3H~3=LPT1OSC,0x04,Low Power Timer1 Osc enable CONFIG3H~4=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RB3 CONFIG3H~2~1=0x2,0x2,PORTB<4:0> configured as analog inputs on RESET CONFIG3H~2~2=0x2,0x0,PORTB<4:0> configured as digital I/O on RESET CONFIG3H~3~1=0x04,0x04,Enabled CONFIG3H~3~2=0x04,0x00,Disabled CONFIG3H~4~1=0x80,0x80,MCLR Enabled,RE3 Disabled CONFIG3H~4~2=0x80,0x00,MCLR Disabled, RE3 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=ENHCPU,0x40,Extended CPU Enable CONFIG4L~4=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x40,0x40,Enabled CONFIG4L~3~2=0x40,0x00,Disabled CONFIG4L~4~1=0x80,0x80,Disabled CONFIG4L~4~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-03FFF CONFIG5L~2=CP_1,0x2,Code Protect 04000-07FFF CONFIG5L~3=CP_2,0x4,Code Protect 08000-0BFFF CONFIG5L~4=CP_3,0x8,Code Protect 0C000-0FFFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EE Read Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-03FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 04000-07FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 08000-0BFFF CONFIG6L~4=WRT_3,0x8,Table Write Protect 0C000-0FFFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x00,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EE Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-03FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 04000-07FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 08000-0BFFF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 0C000-0FFFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x00,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE_24xx05 prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F4620] pgmmem=0x0 ~pgmmem=0xFFFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0x3ff devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x0C00 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xC,0xC,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xA,0xA,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xF,0x5,EC-Port on RA6 CONFIG1H~1~8=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xF,0x3,0011 EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xF,0x2,HS CONFIG1H~1~11=0xF,0x1,XT CONFIG1H~1~12=0xF,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x08,4.2V CONFIG2L~3~4=0x18,0x00,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=PBADEN,0x2,PortB A/D Enable CONFIG3H~3=LPT1OSC,0x04,Low Power Timer1 Osc enable CONFIG3H~4=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RB3 CONFIG3H~2~1=0x2,0x2,PORTB<4:0> configured as analog inputs on RESET CONFIG3H~2~2=0x2,0x0,PORTB<4:0> configured as digital I/O on RESET CONFIG3H~3~1=0x04,0x04,Enabled CONFIG3H~3~2=0x04,0x00,Disabled CONFIG3H~4~1=0x80,0x80,MCLR Enabled,RE3 Disabled CONFIG3H~4~2=0x80,0x00,MCLR Disabled, RE3 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=ENHCPU,0x40,Extended CPU Enable CONFIG4L~4=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x40,0x40,Enabled CONFIG4L~3~2=0x40,0x00,Disabled CONFIG4L~4~1=0x80,0x80,Disabled CONFIG4L~4~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-03FFF CONFIG5L~2=CP_1,0x2,Code Protect 04000-07FFF CONFIG5L~3=CP_2,0x4,Code Protect 08000-0BFFF CONFIG5L~4=CP_3,0x8,Code Protect 0C000-0FFFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EEPROM Code Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-03FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 04000-07FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 08000-0BFFF CONFIG6L~4=WRT_3,0x8,Table Write Protect 0C000-0FFFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x00,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EEPROM Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-03FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 04000-07FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 08000-0BFFF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 0C000-0FFFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x00,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE_24xx05 prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F4680] pgmmem=0x0 ~pgmmem=0xFFFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0x3ff devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x0E80 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xC,0xC,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xA,0xA,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xF,0x5,EC-Port on RA6 CONFIG1H~1~8=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xF,0x3,EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xF,0x2,HS CONFIG1H~1~11=0xF,0x1,XT CONFIG1H~1~12=0xF,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x08,4.2V CONFIG2L~3~4=0x18,0x00,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=PBADEN,0x2,PortB A/D Enable CONFIG3H~2=LPT1OSC,0x04,Low Power Timer1 Osc enable CONFIG3H~3=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x2,0x2,PORTB<4> and <1:0> configured as analog inputs on RESET CONFIG3H~1~2=0x2,0x0,PORTB<4> and <1:0> configured as digital I/O on RESET CONFIG3H~2~1=0x04,0x04,Enabled CONFIG3H~2~2=0x04,0x00,Disabled CONFIG3H~3~1=0x80,0x80,MCLR Enabled,RE3 Disabled CONFIG3H~3~2=0x80,0x00,MCLR Disabled, RE3 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=ENHCPU,0x40,Extended CPU Enable CONFIG4L~4=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x40,0x40,Enabled CONFIG4L~3~2=0x40,0x00,Disabled CONFIG4L~4~1=0x80,0x80,Disabled CONFIG4L~4~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-03FFF CONFIG5L~2=CP_1,0x2,Code Protect 04000-07FFF CONFIG5L~3=CP_2,0x4,Code Protect 08000-0BFFF CONFIG5L~4=CP_3,0x8,Code Protect 0C000-0FFFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EE Read Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-03FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 04000-07FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 08000-0BFFF CONFIG6L~4=WRT_3,0x8,Table Write Protect 0C000-0FFFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x00,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EE Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-03FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 04000-07FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 08000-0BFFF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 0C000-0FFFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x00,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE_24xx05 prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F4681] pgmmem=0x0 ~pgmmem=0xFFFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata= ~eedata= devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x0E00 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xC,0xC,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xA,0xA,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xF,0x5,EC-Port on RA6 CONFIG1H~1~8=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xF,0x3,EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xF,0x2,HS CONFIG1H~1~11=0xF,0x1,XT CONFIG1H~1~12=0xF,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x08,4.2V CONFIG2L~3~4=0x18,0x00,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=PBADEN,0x2,PortB A/D Enable CONFIG3H~2=LPT1OSC,0x04,Low Power Timer1 Osc enable CONFIG3H~3=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x2,0x2,PORTB<4> and <1:0> configured as analog inputs on RESET CONFIG3H~1~2=0x2,0x0,PORTB<4> and <1:0> configured as digital I/O on RESET CONFIG3H~2~1=0x04,0x04,Enabled CONFIG3H~2~2=0x04,0x00,Disabled CONFIG3H~3~1=0x80,0x80,MCLR Enabled,RE3 Disabled CONFIG3H~3~2=0x80,0x00,MCLR Disabled, RE3 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=ENHCPU,0x40,Extended CPU Enable CONFIG4L~4=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x40,0x40,Enabled CONFIG4L~3~2=0x40,0x00,Disabled CONFIG4L~4~1=0x80,0x80,Disabled CONFIG4L~4~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-03FFF CONFIG5L~2=CP_1,0x2,Code Protect 04000-07FFF CONFIG5L~3=CP_2,0x4,Code Protect 08000-0BFFF CONFIG5L~4=CP_3,0x8,Code Protect 0C000-0FFFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EE Read Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-03FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 04000-07FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 08000-0BFFF CONFIG6L~4=WRT_3,0x8,Table Write Protect 0C000-0FFFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x00,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EE Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-03FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 04000-07FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 08000-0BFFF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 0C000-0FFFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x00,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F6310] pgmmem=0x0 ~pgmmem=0xFFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata= ~eedata= devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x0BE0 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004=CONFIG3L 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009= 0x30000A= 0x30000B= 0x30000C=CONFIG7L 0x30000D= CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xC,0xC,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xA,0xA,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xF,0x5,EC-Port on RA6 CONFIG1H~1~8=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xF,0x3,0011 EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xF,0x2,HS CONFIG1H~1~11=0xF,0x1,XT CONFIG1H~1~12=0xF,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x08,4.2V CONFIG2L~3~4=0x18,0x00,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3L_unused=0x0 CONFIG3L~1=WAIT,0x80,External Bus Wait CONFIG3L~2=BW,0x40,Bus Width CONFIG3L~3=PMODE,0x3,Processor Mode CONFIG3L~1~1=0x80,0x80,Disabled CONFIG3L~1~2=0x80,0x0,Enabled CONFIG3L~2~1=0x40,0x40,16-bit external CONFIG3L~2~2=0x40,0x0,8-bit external CONFIG3L~3~1=0x3,0x3,Microcontroller CONFIG3L~3~2=0x3,0x2,Microprocessor CONFIG3L~3~3=0x3,0x1,Microprocessor w/Boot CONFIG3L~3~4=0x3,0x0,Ext Microcontroller CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=LPT1OSC,0x04,Low Power Timer1 Osc enable CONFIG3H~3=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RE7 in microcontroller mode - RB3 in others CONFIG3H~2~1=0x04,0x04,Enabled CONFIG3H~2~2=0x04,0x00,Disabled CONFIG3H~3~1=0x80,0x80,MCLR Enabled, RG5 Disabled CONFIG3H~3~2=0x80,0x00,MCLR Disabled, RG5 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=ENHCPU,0x40,Extended CPU Enable CONFIG4L~3=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x40,0x40,Enabled CONFIG4L~2~2=0x40,0x00,Disabled CONFIG4L~3~1=0x80,0x80,Disabled CONFIG4L~3~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00000-01FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00000-01FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F6390] pgmmem=0x0 ~pgmmem=0xFFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata= ~eedata= devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x0BA0 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004=CONFIG3L 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009= 0x30000A= 0x30000B= 0x30000C=CONFIG7L 0x30000D= CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xC,0xC,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xA,0xA,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xF,0x5,EC-Port on RA6 CONFIG1H~1~8=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xF,0x3,0011 EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xF,0x2,HS CONFIG1H~1~11=0xF,0x1,XT CONFIG1H~1~12=0xF,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x08,4.2V CONFIG2L~3~4=0x18,0x00,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3L_unused=0x0 CONFIG3L~1=WAIT,0x80,External Bus Wait CONFIG3L~2=BW,0x40,Bus Width CONFIG3L~3=PMODE,0x3,Processor Mode CONFIG3L~1~1=0x80,0x80,Disabled CONFIG3L~1~2=0x80,0x0,Enabled CONFIG3L~2~1=0x40,0x40,16-bit external CONFIG3L~2~2=0x40,0x0,8-bit external CONFIG3L~3~1=0x3,0x3,Microcontroller CONFIG3L~3~2=0x3,0x2,Microprocessor CONFIG3L~3~3=0x3,0x1,Microprocessor w/Boot CONFIG3L~3~4=0x3,0x0,Ext Microcontroller CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=LPT1OSC,0x04,Low Power Timer1 Osc enable CONFIG3H~3=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RE7 in microcontroller mode - RB3 in others CONFIG3H~2~1=0x04,0x04,Enabled CONFIG3H~2~2=0x04,0x00,Disabled CONFIG3H~3~1=0x80,0x80,MCLR Enabled, RG5 Disabled CONFIG3H~3~2=0x80,0x00,MCLR Disabled, RG5 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=ENHCPU,0x40,Extended CPU Enable CONFIG4L~3=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x40,0x40,Enabled CONFIG4L~2~2=0x40,0x00,Disabled CONFIG4L~3~1=0x80,0x80,Disabled CONFIG4L~3~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00000-01FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00000-01FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F6410] pgmmem=0x0 ~pgmmem=0x3FFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata= ~eedata= devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x06E0 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004=CONFIG3L 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009= 0x30000A= 0x30000B= 0x30000C=CONFIG7L 0x30000D= CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xC,0xC,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xA,0xA,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xF,0x5,EC-Port on RA6 CONFIG1H~1~8=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xF,0x3,0011 EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xF,0x2,HS CONFIG1H~1~11=0xF,0x1,XT CONFIG1H~1~12=0xF,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x08,4.2V CONFIG2L~3~4=0x18,0x00,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3L_unused=0x0 CONFIG3L~1=WAIT,0x80,External Bus Wait CONFIG3L~2=BW,0x40,Bus Width CONFIG3L~3=PMODE,0x3,Processor Mode CONFIG3L~1~1=0x80,0x80,Disabled CONFIG3L~1~2=0x80,0x0,Enabled CONFIG3L~2~1=0x40,0x40,16-bit external CONFIG3L~2~2=0x40,0x0,8-bit external CONFIG3L~3~1=0x3,0x3,Microcontroller CONFIG3L~3~2=0x3,0x2,Microprocessor CONFIG3L~3~3=0x3,0x1,Microprocessor w/Boot CONFIG3L~3~4=0x3,0x0,Ext Microcontroller CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=LPT1OSC,0x04,Low Power Timer1 Osc enable CONFIG3H~3=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RE7 in microcontroller mode - RB3 in others CONFIG3H~2~1=0x04,0x04,Enabled CONFIG3H~2~2=0x04,0x00,Disabled CONFIG3H~3~1=0x80,0x80,MCLR Enabled, RG5 Disabled CONFIG3H~3~2=0x80,0x00,MCLR Disabled, RG5 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=ENHCPU,0x40,Extended CPU Enable CONFIG4L~3=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x40,0x40,Enabled CONFIG4L~2~2=0x40,0x00,Disabled CONFIG4L~3~1=0x80,0x80,Disabled CONFIG4L~3~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00000-03FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00000-03FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F6490] pgmmem=0x0 ~pgmmem=0x3FFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata= ~eedata= devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x06A0 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004=CONFIG3L 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009= 0x30000A= 0x30000B= 0x30000C=CONFIG7L 0x30000D= CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xC,0xC,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xA,0xA,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xF,0x5,EC-Port on RA6 CONFIG1H~1~8=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xF,0x3,0011 EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xF,0x2,HS CONFIG1H~1~11=0xF,0x1,XT CONFIG1H~1~12=0xF,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x08,4.2V CONFIG2L~3~4=0x18,0x00,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3L_unused=0x0 CONFIG3L~1=WAIT,0x80,External Bus Wait CONFIG3L~2=BW,0x40,Bus Width CONFIG3L~3=PMODE,0x3,Processor Mode CONFIG3L~1~1=0x80,0x80,Disabled CONFIG3L~1~2=0x80,0x0,Enabled CONFIG3L~2~1=0x40,0x40,16-bit external CONFIG3L~2~2=0x40,0x0,8-bit external CONFIG3L~3~1=0x3,0x3,Microcontroller CONFIG3L~3~2=0x3,0x2,Microprocessor CONFIG3L~3~3=0x3,0x1,Microprocessor w/Boot CONFIG3L~3~4=0x3,0x0,Ext Microcontroller CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=LPT1OSC,0x04,Low Power Timer1 Osc enable CONFIG3H~3=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RE7 in microcontroller mode - RB3 in others CONFIG3H~2~1=0x04,0x04,Enabled CONFIG3H~2~2=0x04,0x00,Disabled CONFIG3H~3~1=0x80,0x80,MCLR Enabled, RG5 Disabled CONFIG3H~3~2=0x80,0x00,MCLR Disabled, RG5 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=ENHCPU,0x40,Extended CPU Enable CONFIG4L~3=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x40,0x40,Enabled CONFIG4L~2~2=0x40,0x00,Disabled CONFIG4L~3~1=0x80,0x80,Disabled CONFIG4L~3~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00000-03FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00000-03FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F6520] pgmmem=0x0 ~pgmmem=0x7fff cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0x3ff devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x0B20 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004=CONFIG3L 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0x7,Oscillator CONFIG1H~2=OSCS,0x20,Osc. Switch Enable CONFIG1H~1~1=0x7,0x7,RC-OSC2 as RA6 CONFIG1H~1~2=0x7,0x6,HS-PLL Enabled CONFIG1H~1~3=0x7,0x5,EC-OSC2 as RA6 CONFIG1H~1~4=0x7,0x4,EC-OSC2 as Clock Out CONFIG1H~1~5=0x7,0x3,RC-OSC2 as Clock Out CONFIG1H~1~6=0x7,0x2,HS CONFIG1H~1~7=0x7,0x1,XT CONFIG1H~1~8=0x7,0x0,LP CONFIG1H~2~1=0x20,0x20,Disabled CONFIG1H~2~2=0x20,0x0,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x2,Brown Out Detect CONFIG2L~3=BODENV,0xC,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x2,0x2,Enabled CONFIG2L~2~2=0x2,0x0,Disabled CONFIG2L~3~1=0xC,0xC,2.5V CONFIG2L~3~2=0xC,0x8,2.7V CONFIG2L~3~3=0xC,0x4,4.2V CONFIG2L~3~4=0xC,0x0,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0xE,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0xE,0xE,1:128 CONFIG2H~2~2=0xE,0xC,1:64 CONFIG2H~2~3=0xE,0xA,1:32 CONFIG2H~2~4=0xE,0x8,1:16 CONFIG2H~2~5=0xE,0x6,1:8 CONFIG2H~2~6=0xE,0x4,1:4 CONFIG2H~2~7=0xE,0x2,1:2 CONFIG2H~2~8=0xE,0x0,1:1 CONFIG3L_unused=0x0 CONFIG3L~1=PMODE,0x3,Processor Mode CONFIG3L~2=WAIT,0x80,External Bus Wait CONFIG3L~1~1=0x3,0x3,Microcontroller CONFIG3L~1~2=0x3,0x2,Microprocessor CONFIG3L~1~3=0x3,0x1,Microprocessor w/Boot CONFIG3L~1~4=0x3,0x0,Ext Microcontroller CONFIG3L~2~1=0x80,0x80,Disabled CONFIG3L~2~2=0x80,0x0,Enabled CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=T1OSCMX,0x2,Timer1 OSC CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RE7 CONFIG3H~2~1=0x2,0x2,Legacy CONFIG3H~2~2=0x2,0x0,Low Power CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x80,0x80,Disabled CONFIG4L~3~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-01FFF CONFIG5L~2=CP_1,0x2,Code Protect 02000-03FFF CONFIG5L~3=CP_2,0x4,Code Protect 04000-05FFF CONFIG5L~4=CP_3,0x8,Code Protect 06000-07FFF CONFIG5L~5=CP_4,0x10,Code Protect 10000-13FFF CONFIG5L~6=CP_5,0x20,Code Protect 14000-17FFF CONFIG5L~7=CP_6,0x40,Code Protect 18000-1BFFF CONFIG5L~8=CP_7,0x80,Code Protect 1C000-1FFFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5L~5~1=0x10,0x10,Disabled CONFIG5L~5~2=0x10,0x00,Enabled CONFIG5L~6~1=0x20,0x20,Disabled CONFIG5L~6~2=0x20,0x00,Enabled CONFIG5L~7~1=0x40,0x40,Disabled CONFIG5L~7~2=0x40,0x00,Enabled CONFIG5L~8~1=0x80,0x80,Disabled CONFIG5L~8~2=0x80,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EE Read Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-01FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 02000-03FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 04000-05FFF CONFIG6L~4=WRT_3,0x8,Table Write Protect 06000-07FFF CONFIG6L~5=WRT_4,0x10,Table Write Protect 10000-13FFF CONFIG6L~6=WRT_5,0x20,Table Write Protect 14000-17FFF CONFIG6L~7=WRT_6,0x40,Table Write Protect 18000-1BFFF CONFIG6L~8=WRT_7,0x80,Table Write Protect 1C000-1FFFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x00,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x00,Enabled CONFIG6L~5~1=0x10,0x10,Disabled CONFIG6L~5~2=0x10,0x00,Enabled CONFIG6L~6~1=0x20,0x20,Disabled CONFIG6L~6~2=0x20,0x00,Enabled CONFIG6L~7~1=0x40,0x40,Disabled CONFIG6L~7~2=0x40,0x00,Enabled CONFIG6L~8~1=0x80,0x80,Disabled CONFIG6L~8~2=0x80,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EE Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-01FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 02000-03FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 04000-05FFF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 06000-07FFF CONFIG7L~5=EBTR_4,0x10,Table Read Protect 10000-13FFF CONFIG7L~6=EBTR_5,0x20,Table Read Protect 14000-17FFF CONFIG7L~7=EBTR_6,0x40,Table Read Protect 18000-1BFFF CONFIG7L~8=EBTR_7,0x80,Table Read Protect 1C000-1FFFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x00,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x00,Enabled CONFIG7L~5~1=0x10,0x10,Disabled CONFIG7L~5~2=0x10,0x00,Enabled CONFIG7L~6~1=0x20,0x20,Disabled CONFIG7L~6~2=0x20,0x00,Enabled CONFIG7L~7~1=0x40,0x40,Disabled CONFIG7L~7~2=0x40,0x00,Enabled CONFIG7L~8~1=0x80,0x80,Disabled CONFIG7L~8~2=0x80,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F6525] pgmmem=0x0 ~pgmmem=0xBfff cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0x3ff devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x0AE0 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004=CONFIG3L 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=OSCS,0x20,Osc. Switch Enable CONFIG1H~1~1=0xF,0xF,RC-OSC2 as RA6 CONFIG1H~1~2=0xF,0xE,HS oscillator with SW enabled 4x PLL CONFIG1H~1~3=0xF,0xD,EC-OSC2 as RA6, software enabled 4X PLL CONFIG1H~1~4=0xF,0xC,EC-OSC2 as RA6, hardware enabled 4X PLL CONFIG1H~1~5=0xF,0x7,RC-OSC2 as RA6 CONFIG1H~1~6=0xF,0x6,HS-hardware enabled 4X PLL CONFIG1H~1~7=0xF,0x5,EC-OSC2 as RA6 CONFIG1H~1~8=0xF,0x4,EC-OSC2 as divide by 4 CLKOUT CONFIG1H~1~9=0xF,0x3,RC-OSC2 as divide by 4 CLKOUT CONFIG1H~1~10=0xF,0x2,HS CONFIG1H~1~11=0xF,0x1,XT CONFIG1H~1~12=0xF,0x0,LP CONFIG1H~2~1=0x20,0x0,Enabled CONFIG1H~2~2=0x20,0x20,Disabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x2,Brown Out Detect CONFIG2L~3=BODENV,0xC,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x2,0x2,Enabled CONFIG2L~2~2=0x2,0x0,Disabled CONFIG2L~3~1=0xC,0xC,2.0V CONFIG2L~3~2=0xC,0x8,2.7V CONFIG2L~3~3=0xC,0x4,4.2V CONFIG2L~3~4=0xC,0x0,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3L_unused=0x0 CONFIG3L~1=PMODE,0x3,Processor Mode CONFIG3L~2=WAIT,0x80,External Bus Wait CONFIG3L~1~1=0x3,0x3,Microcontroller CONFIG3L~1~2=0x3,0x2,Microprocessor CONFIG3L~1~3=0x3,0x1,Microprocessor w/Boot CONFIG3L~1~4=0x3,0x0,Ext Microcontroller CONFIG3L~2~1=0x80,0x80,Disabled CONFIG3L~2~2=0x80,0x0,Enabled CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=MCLRE,0x80,MCLR enable CONFIG3H~3=ECCPMX,0x2,ECCP Mux CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RE7 CONFIG3H~2~1=0x80,0x80,MCLR Enabled, RG5 Disabled CONFIG3H~2~2=0x80,0x00,MCLR Disabled, RG5 Enabled CONFIG3H~3~1=0x2,0x2,ECCP1 and ECCP3 are muxed onto RE6-RE3 CONFIG3H~3~2=0x2,0x0,ECCP1 and ECCP3 are muxed onto RH7-RH4 CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x80,0x80,Disabled CONFIG4L~3~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 000800-0003FFF CONFIG5L~2=CP_1,0x2,Code Protect 0004000-007FFF CONFIG5L~3=CP_2,0x4,Code Protect 008000-00BFFF CONFIG5L~4=CP_3,0x8,Code Protect 00C000-00FFFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EE Read Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-003FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 004000-007FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 08000-0BFFF CONFIG6L~4=WRT_3,0x8,Table Write Protect 0C000-0FFFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x00,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EE Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-003FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 004000-07FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 08000-0BFFF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 0C000-0FFFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x00,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F6585] pgmmem=0x0 ~pgmmem=0xBfff cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0x3ff devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x0A60 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004=CONFIG3L 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=OSCS,0x20,Osc. Switch Enable CONFIG1H~1~1=0xF,0xF,RC-OSC2 as RA6 CONFIG1H~1~2=0xF,0xE,HS oscillator with SW enabled 4x PLL CONFIG1H~1~3=0xF,0xD,EC-OSC2 as RA6, software enabled 4X PLL CONFIG1H~1~4=0xF,0xC,EC-OSC2 as RA6, hardware enabled 4X PLL CONFIG1H~1~5=0xF,0x7,RC-OSC2 as RA6 CONFIG1H~1~6=0xF,0x6,HS-hardware enabled 4X PLL CONFIG1H~1~7=0xF,0x5,EC-OSC2 as RA6 CONFIG1H~1~8=0xF,0x4,EC-OSC2 as divide by 4 CLKOUT CONFIG1H~1~9=0xF,0x3,RC-OSC2 as divide by 4 CLKOUT CONFIG1H~1~10=0xF,0x2,HS CONFIG1H~1~11=0xF,0x1,XT CONFIG1H~1~12=0xF,0x0,LP CONFIG1H~2~1=0x20,0x0,Enabled CONFIG1H~2~2=0x20,0x20,Disabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x2,Brown Out Detect CONFIG2L~3=BODENV,0xC,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x2,0x2,Enabled CONFIG2L~2~2=0x2,0x0,Disabled CONFIG2L~3~1=0xC,0xC,2.0V CONFIG2L~3~2=0xC,0x8,2.7V CONFIG2L~3~3=0xC,0x4,4.2V CONFIG2L~3~4=0xC,0x0,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3L_unused=0x0 CONFIG3L~1=PMODE,0x3,Processor Mode CONFIG3L~2=WAIT,0x80,External Bus Wait CONFIG3L~1~1=0x3,0x3,Microcontroller CONFIG3L~1~2=0x3,0x2,Microprocessor CONFIG3L~1~3=0x3,0x1,Microprocessor w/Boot CONFIG3L~1~4=0x3,0x0,Ext Microcontroller CONFIG3L~2~1=0x80,0x80,Disabled CONFIG3L~2~2=0x80,0x0,Enabled CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=MCLRE,0x80,MCLR enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RE7 CONFIG3H~2~1=0x80,0x80,MCLR Enabled, RG5 Disabled CONFIG3H~2~2=0x80,0x00,MCLR Disabled, RG5 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x80,0x80,Disabled CONFIG4L~3~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 000800-0003FFF CONFIG5L~2=CP_1,0x2,Code Protect 0004000-007FFF CONFIG5L~3=CP_2,0x4,Code Protect 008000-00BFFF CONFIG5L~4=CP_3,0x8,Code Protect 00C000-00FFFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EE Read Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-003FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 004000-007FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 08000-0BFFF CONFIG6L~4=WRT_3,0x8,Table Write Protect 0C000-0FFFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x00,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EE Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-003FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 004000-07FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 08000-0BFFF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 0C000-0FFFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x00,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F6620] pgmmem=0x0 ~pgmmem=0xffff cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0x3ff devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x0660 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004=CONFIG3L 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0x7,Oscillator CONFIG1H~2=OSCS,0x20,Osc. Switch Enable CONFIG1H~1~1=0x7,0x7,RC-OSC2 as RA6 CONFIG1H~1~2=0x7,0x6,HS-PLL Enabled CONFIG1H~1~3=0x7,0x5,EC-OSC2 as RA6 CONFIG1H~1~4=0x7,0x4,EC-OSC2 as Clock Out CONFIG1H~1~5=0x7,0x3,RC-OSC2 as Clock Out CONFIG1H~1~6=0x7,0x2,HS CONFIG1H~1~7=0x7,0x1,XT CONFIG1H~1~8=0x7,0x0,LP CONFIG1H~2~1=0x20,0x20,Disabled CONFIG1H~2~2=0x20,0x0,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x2,Brown Out Detect CONFIG2L~3=BODENV,0xC,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x2,0x2,Enabled CONFIG2L~2~2=0x2,0x0,Disabled CONFIG2L~3~1=0xC,0xC,2.5V CONFIG2L~3~2=0xC,0x8,2.7V CONFIG2L~3~3=0xC,0x4,4.2V CONFIG2L~3~4=0xC,0x0,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0xE,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0xE,0xE,1:128 CONFIG2H~2~2=0xE,0xC,1:64 CONFIG2H~2~3=0xE,0xA,1:32 CONFIG2H~2~4=0xE,0x8,1:16 CONFIG2H~2~5=0xE,0x6,1:8 CONFIG2H~2~6=0xE,0x4,1:4 CONFIG2H~2~7=0xE,0x2,1:2 CONFIG2H~2~8=0xE,0x0,1:1 CONFIG3L_unused=0x0 CONFIG3L~1=PMODE,0x3,Processor Mode CONFIG3L~2=WAIT,0x80,External Bus Wait CONFIG3L~1~1=0x3,0x3,Microcontroller CONFIG3L~1~2=0x3,0x2,Microprocessor CONFIG3L~1~3=0x3,0x1,Microprocessor w/Boot CONFIG3L~1~4=0x3,0x0,Ext Microcontroller CONFIG3L~2~1=0x80,0x80,Disabled CONFIG3L~2~2=0x80,0x0,Enabled CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=T1OSCMX,0x2,Timer1 OSC CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RE7 CONFIG3H~2~1=0x2,0x2,Legacy CONFIG3H~2~2=0x2,0x0,Low Power CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x80,0x80,Disabled CONFIG4L~3~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00200-03FFF CONFIG5L~2=CP_1,0x2,Code Protect 04000-07FFF CONFIG5L~3=CP_2,0x4,Code Protect 08000-0BFFF CONFIG5L~4=CP_3,0x8,Code Protect 0C000-0FFFF CONFIG5L~5=CP_4,0x10,Code Protect 10000-13FFF CONFIG5L~6=CP_5,0x20,Code Protect 14000-17FFF CONFIG5L~7=CP_6,0x40,Code Protect 18000-1BFFF CONFIG5L~8=CP_7,0x80,Code Protect 1C000-1FFFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5L~5~1=0x10,0x10,Disabled CONFIG5L~5~2=0x10,0x00,Enabled CONFIG5L~6~1=0x20,0x20,Disabled CONFIG5L~6~2=0x20,0x00,Enabled CONFIG5L~7~1=0x40,0x40,Disabled CONFIG5L~7~2=0x40,0x00,Enabled CONFIG5L~8~1=0x80,0x80,Disabled CONFIG5L~8~2=0x80,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EEPROM Code Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00200-03FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 04000-07FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 08000-0BFFF CONFIG6L~4=WRT_3,0x8,Table Write Protect 0C000-0FFFF CONFIG6L~5=WRT_4,0x10,Table Write Protect 10000-13FFF CONFIG6L~6=WRT_5,0x20,Table Write Protect 14000-17FFF CONFIG6L~7=WRT_6,0x40,Table Write Protect 18000-1BFFF CONFIG6L~8=WRT_7,0x80,Table Write Protect 1C000-1FFFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x00,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x00,Enabled CONFIG6L~5~1=0x10,0x10,Disabled CONFIG6L~5~2=0x10,0x00,Enabled CONFIG6L~6~1=0x20,0x20,Disabled CONFIG6L~6~2=0x20,0x00,Enabled CONFIG6L~7~1=0x40,0x40,Disabled CONFIG6L~7~2=0x40,0x00,Enabled CONFIG6L~8~1=0x80,0x80,Disabled CONFIG6L~8~2=0x80,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EEPROM Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00200-03FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 04000-07FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 08000-0BFFF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 0C000-0FFFF CONFIG7L~5=EBTR_4,0x10,Table Read Protect 10000-13FFF CONFIG7L~6=EBTR_5,0x20,Table Read Protect 14000-17FFF CONFIG7L~7=EBTR_6,0x40,Table Read Protect 18000-1BFFF CONFIG7L~8=EBTR_7,0x80,Table Read Protect 1C000-1FFFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x00,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x00,Enabled CONFIG7L~5~1=0x10,0x10,Disabled CONFIG7L~5~2=0x10,0x00,Enabled CONFIG7L~6~1=0x20,0x20,Disabled CONFIG7L~6~2=0x20,0x00,Enabled CONFIG7L~7~1=0x40,0x40,Disabled CONFIG7L~7~2=0x40,0x00,Enabled CONFIG7L~8~1=0x80,0x80,Disabled CONFIG7L~8~2=0x80,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F6621] pgmmem=0x0 ~pgmmem=0xffff cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0x3ff devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x0AA0 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004=CONFIG3L 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=OSCS,0x20,Osc. Switch Enable CONFIG1H~1~1=0xF,0xF,RC-OSC2 as RA6 CONFIG1H~1~2=0xF,0xE,HS oscillator with SW enabled 4x PLL CONFIG1H~1~3=0xF,0xD,EC-OSC2 as RA6, software enabled 4X PLL CONFIG1H~1~4=0xF,0xC,EC-OSC2 as RA6, hardware enabled 4X PLL CONFIG1H~1~5=0xF,0x7,RC-OSC2 as RA6 CONFIG1H~1~6=0xF,0x6,HS-hardware enabled 4X PLL CONFIG1H~1~7=0xF,0x5,EC-OSC2 as RA6 CONFIG1H~1~8=0xF,0x4,EC-OSC2 as divide by 4 CLKOUT CONFIG1H~1~9=0xF,0x3,RC-OSC2 as divide by 4 CLKOUT CONFIG1H~1~10=0xF,0x2,HS CONFIG1H~1~11=0xF,0x1,XT CONFIG1H~1~12=0xF,0x0,LP CONFIG1H~2~1=0x20,0x0,Enabled CONFIG1H~2~2=0x20,0x20,Disabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x2,Brown Out Detect CONFIG2L~3=BODENV,0xC,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x2,0x2,Enabled CONFIG2L~2~2=0x2,0x0,Disabled CONFIG2L~3~1=0xC,0xC,2.0V CONFIG2L~3~2=0xC,0x8,2.7V CONFIG2L~3~3=0xC,0x4,4.2V CONFIG2L~3~4=0xC,0x0,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3L_unused=0x0 CONFIG3L~1=PMODE,0x3,Processor Mode CONFIG3L~2=WAIT,0x80,External Bus Wait CONFIG3L~1~1=0x3,0x3,Microcontroller CONFIG3L~1~2=0x3,0x2,Microprocessor CONFIG3L~1~3=0x3,0x1,Microprocessor w/Boot CONFIG3L~1~4=0x3,0x0,Ext Microcontroller CONFIG3L~2~1=0x80,0x80,Disabled CONFIG3L~2~2=0x80,0x0,Enabled CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=MCLRE,0x80,MCLR enable CONFIG3H~3=ECCPMX,0x2,ECCP Mux CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RE7 CONFIG3H~2~1=0x80,0x80,MCLR Enabled, RG5 Disabled CONFIG3H~2~2=0x80,0x00,MCLR Disabled, RG5 Enabled CONFIG3H~3~1=0x2,0x2,ECCP1 and ECCP3 are muxed onto RE6-RE3 CONFIG3H~3~2=0x2,0x0,ECCP1 and ECCP3 are muxed onto RH7-RH4 CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x80,0x80,Disabled CONFIG4L~3~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 000800-0003FFF CONFIG5L~2=CP_1,0x2,Code Protect 0004000-007FFF CONFIG5L~3=CP_2,0x4,Code Protect 008000-00BFFF CONFIG5L~4=CP_3,0x8,Code Protect 00C000-00FFFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EE Read Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-003FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 004000-007FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 08000-0BFFF CONFIG6L~4=WRT_3,0x8,Table Write Protect 0C000-0FFFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x00,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EE Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-003FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 004000-07FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 08000-0BFFF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 0C000-0FFFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x00,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F6625] pgmmem=0x0 ~pgmmem=0x17FFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0x3ff devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x13C0 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004=CONFIG3L 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xC,0xC,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xA,0xA,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xF,0x5,EC-Port on RA6 CONFIG1H~1~8=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xF,0x3,0011 EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xF,0x2,HS CONFIG1H~1~11=0xF,0x1,XT CONFIG1H~1~12=0xF,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x08,4.2V CONFIG2L~3~4=0x18,0x00,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3L_unused=0x0 CONFIG3L~1=PMODE,0x3,Processor Mode CONFIG3L~2=ABW,0x30,Address Bus Width CONFIG3L~3=BW,0x40,Bus Width CONFIG3L~4=WAIT,0x80,External Bus Wait CONFIG3L~1~1=0x3,0x3,Microcontroller CONFIG3L~1~2=0x3,0x2,Microprocessor CONFIG3L~1~3=0x3,0x1,Microprocessor w/Boot CONFIG3L~1~4=0x3,0x0,Ext Microcontroller CONFIG3L~2~1=0x30,0x30,20-bit CONFIG3L~2~2=0x30,0x20,16-bit CONFIG3L~2~3=0x30,0x10,12-bit CONFIG3L~2~4=0x30,0x00,8-bit CONFIG3L~3~1=0x40,0x40,16-bit external bus CONFIG3L~3~2=0x40,0x00,8-bit external bus CONFIG3L~4~1=0x80,0x80,Disabled CONFIG3L~4~2=0x80,0x0,Enabled CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=ECCPMX,0x2,ECCP Mux CONFIG3H~3=LPT1OSC,0x04,Low Power Timer1 Osc enable CONFIG3H~4=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RE7-Microcontroller Mode/RB3-All other modes CONFIG3H~2~1=0x2,0x2,Enhanced CCP1 [P1B/P1C] muxed with RE5/RE6 CONFIG3H~2~2=0x2,0x0,Enhanced CCP1 [P1B/P1C] muxed with RH7/RH6 CONFIG3H~3~1=0x04,0x04,Enabled CONFIG3H~3~2=0x04,0x00,Disabled CONFIG3H~4~1=0x80,0x80,MCLR Enabled,RG5 Disabled CONFIG3H~4~2=0x80,0x00,MCLR Disabled, RG5 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=ENHCPU,0x40,Extended CPU Enable CONFIG4L~4=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x40,0x40,Enabled CONFIG4L~3~2=0x40,0x00,Disabled CONFIG4L~4~1=0x80,0x80,Disabled CONFIG4L~4~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-03FFF CONFIG5L~2=CP_1,0x2,Code Protect 04000-07FFF CONFIG5L~3=CP_2,0x4,Code Protect 08000-0BFFF CONFIG5L~4=CP_3,0x8,Code Protect 0C000-0FFFF CONFIG5L~5=CP_4,0x10,Code Protect 10000-13FFF CONFIG5L~6=CP_5,0x20,Code Protect 14000-17FFF CONFIG5L~7=CP_6,0x40,Code Protect 18000-1BFFF CONFIG5L~8=CP_7,0x80,Code Protect 1C000-1FFFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5L~5~1=0x10,0x10,Disabled CONFIG5L~5~2=0x10,0x00,Enabled CONFIG5L~6~1=0x20,0x20,Disabled CONFIG5L~6~2=0x20,0x00,Enabled CONFIG5L~7~1=0x40,0x40,Disabled CONFIG5L~7~2=0x40,0x00,Enabled CONFIG5L~8~1=0x80,0x80,Disabled CONFIG5L~8~2=0x80,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EE Read Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-03FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 04000-07FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 08000-0BFFF CONFIG6L~4=WRT_3,0x8,Table Write Protect 0C000-0FFFF CONFIG6L~5=WRT_4,0x10,Table Write Protect 10000-13FFF CONFIG6L~6=WRT_5,0x20,Table Write Protect 14000-17FFF CONFIG6L~7=WRT_6,0x40,Table Write Protect 18000-1BFFF CONFIG6L~8=WRT_7,0x80,Table Write Protect 1C000-1FFFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x00,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x00,Enabled CONFIG6L~5~1=0x10,0x10,Disabled CONFIG6L~5~2=0x10,0x00,Enabled CONFIG6L~6~1=0x20,0x20,Disabled CONFIG6L~6~2=0x20,0x00,Enabled CONFIG6L~7~1=0x40,0x40,Disabled CONFIG6L~7~2=0x40,0x00,Enabled CONFIG6L~8~1=0x80,0x80,Disabled CONFIG6L~8~2=0x80,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EE Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-03FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 04000-07FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 08000-0BFFF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 0C000-0FFFF CONFIG7L~5=EBTR_4,0x10,Table Read Protect 10000-13FFF CONFIG7L~6=EBTR_5,0x20,Table Read Protect 14000-17FFF CONFIG7L~7=EBTR_6,0x40,Table Read Protect 18000-1BFFF CONFIG7L~8=EBTR_7,0x80,Table Read Protect 1C000-1FFFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x00,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x00,Enabled CONFIG7L~5~1=0x10,0x10,Disabled CONFIG7L~5~2=0x10,0x00,Enabled CONFIG7L~6~1=0x20,0x20,Disabled CONFIG7L~6~2=0x20,0x00,Enabled CONFIG7L~7~1=0x40,0x40,Disabled CONFIG7L~7~2=0x40,0x00,Enabled CONFIG7L~8~1=0x80,0x80,Disabled CONFIG7L~8~2=0x80,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F6680] pgmmem=0x0 ~pgmmem=0xffff cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0x3ff devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x0A20 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004=CONFIG3L 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=OSCS,0x20,Osc. Switch Enable CONFIG1H~1~1=0xF,0xF,RC-OSC2 as RA6 CONFIG1H~1~2=0xF,0xE,HS oscillator with SW enabled 4x PLL CONFIG1H~1~3=0xF,0xD,EC-OSC2 as RA6, software enabled 4X PLL CONFIG1H~1~4=0xF,0xC,EC-OSC2 as RA6, hardware enabled 4X PLL CONFIG1H~1~5=0xF,0x7,RC-OSC2 as RA6 CONFIG1H~1~6=0xF,0x6,HS-hardware enabled 4X PLL CONFIG1H~1~7=0xF,0x5,EC-OSC2 as RA6 CONFIG1H~1~8=0xF,0x4,EC-OSC2 as divide by 4 CLKOUT CONFIG1H~1~9=0xF,0x3,RC-OSC2 as divide by 4 CLKOUT CONFIG1H~1~10=0xF,0x2,HS CONFIG1H~1~11=0xF,0x1,XT CONFIG1H~1~12=0xF,0x0,LP CONFIG1H~2~1=0x20,0x0,Enabled CONFIG1H~2~2=0x20,0x20,Disabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x2,Brown Out Detect CONFIG2L~3=BODENV,0xC,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x2,0x2,Enabled CONFIG2L~2~2=0x2,0x0,Disabled CONFIG2L~3~1=0xC,0xC,2.0V CONFIG2L~3~2=0xC,0x8,2.7V CONFIG2L~3~3=0xC,0x4,4.2V CONFIG2L~3~4=0xC,0x0,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3L_unused=0x0 CONFIG3L~1=PMODE,0x3,Processor Mode CONFIG3L~2=WAIT,0x80,External Bus Wait CONFIG3L~1~1=0x3,0x3,Microcontroller CONFIG3L~1~2=0x3,0x2,Microprocessor CONFIG3L~1~3=0x3,0x1,Microprocessor w/Boot CONFIG3L~1~4=0x3,0x0,Ext Microcontroller CONFIG3L~2~1=0x80,0x80,Disabled CONFIG3L~2~2=0x80,0x0,Enabled CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=MCLRE,0x80,MCLR enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RE7 CONFIG3H~2~1=0x80,0x80,MCLR Enabled, RG5 Disabled CONFIG3H~2~2=0x80,0x00,MCLR Disabled, RG5 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x80,0x80,Disabled CONFIG4L~3~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 000800-0003FFF CONFIG5L~2=CP_1,0x2,Code Protect 0004000-007FFF CONFIG5L~3=CP_2,0x4,Code Protect 008000-00BFFF CONFIG5L~4=CP_3,0x8,Code Protect 00C000-00FFFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EE Read Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-003FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 004000-007FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 08000-0BFFF CONFIG6L~4=WRT_3,0x8,Table Write Protect 0C000-0FFFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x00,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EE Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-003FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 004000-07FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 08000-0BFFF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 0C000-0FFFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x00,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F6720] pgmmem=0x0 ~pgmmem=0x1ffff cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0x3ff devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x0620 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004=CONFIG3L 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0x7,Oscillator CONFIG1H~2=OSCS,0x20,Osc. Switch Enable CONFIG1H~1~1=0x7,0x7,RC-OSC2 as RA6 CONFIG1H~1~2=0x7,0x6,HS-PLL Enabled CONFIG1H~1~3=0x7,0x5,EC-OSC2 as RA6 CONFIG1H~1~4=0x7,0x4,EC-OSC2 as Clock Out CONFIG1H~1~5=0x7,0x3,RC-OSC2 as Clock Out CONFIG1H~1~6=0x7,0x2,HS CONFIG1H~1~7=0x7,0x1,XT CONFIG1H~1~8=0x7,0x0,LP CONFIG1H~2~1=0x20,0x20,Disabled CONFIG1H~2~2=0x20,0x0,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x2,Brown Out Detect CONFIG2L~3=BODENV,0xC,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x2,0x2,Enabled CONFIG2L~2~2=0x2,0x0,Disabled CONFIG2L~3~1=0xC,0xC,2.5V CONFIG2L~3~2=0xC,0x8,2.7V CONFIG2L~3~3=0xC,0x4,4.2V CONFIG2L~3~4=0xC,0x0,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0xE,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0xE,0xE,1:128 CONFIG2H~2~2=0xE,0xC,1:64 CONFIG2H~2~3=0xE,0xA,1:32 CONFIG2H~2~4=0xE,0x8,1:16 CONFIG2H~2~5=0xE,0x6,1:8 CONFIG2H~2~6=0xE,0x4,1:4 CONFIG2H~2~7=0xE,0x2,1:2 CONFIG2H~2~8=0xE,0x0,1:1 CONFIG3L_unused=0x0 CONFIG3L~1=PMODE,0x3,Processor Mode CONFIG3L~2=WAIT,0x80,External Bus Wait CONFIG3L~1~1=0x3,0x3,Microcontroller CONFIG3L~1~2=0x3,0x2,Microprocessor CONFIG3L~1~3=0x3,0x1,Microprocessor w/Boot CONFIG3L~1~4=0x3,0x0,Ext Microcontroller CONFIG3L~2~1=0x80,0x80,Disabled CONFIG3L~2~2=0x80,0x0,Enabled CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=T1OSCMX,0x2,Timer1 OSC CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RE7 CONFIG3H~2~1=0x2,0x2,Legacy CONFIG3H~2~2=0x2,0x0,Low Power CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x80,0x80,Disabled CONFIG4L~3~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00200-03FFF CONFIG5L~2=CP_1,0x2,Code Protect 04000-07FFF CONFIG5L~3=CP_2,0x4,Code Protect 08000-0BFFF CONFIG5L~4=CP_3,0x8,Code Protect 0C000-0FFFF CONFIG5L~5=CP_4,0x10,Code Protect 10000-13FFF CONFIG5L~6=CP_5,0x20,Code Protect 14000-17FFF CONFIG5L~7=CP_6,0x40,Code Protect 18000-1BFFF CONFIG5L~8=CP_7,0x80,Code Protect 1C000-1FFFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5L~5~1=0x10,0x10,Disabled CONFIG5L~5~2=0x10,0x00,Enabled CONFIG5L~6~1=0x20,0x20,Disabled CONFIG5L~6~2=0x20,0x00,Enabled CONFIG5L~7~1=0x40,0x40,Disabled CONFIG5L~7~2=0x40,0x00,Enabled CONFIG5L~8~1=0x80,0x80,Disabled CONFIG5L~8~2=0x80,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EEPROM Code Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00200-03FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 04000-07FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 08000-0BFFF CONFIG6L~4=WRT_3,0x8,Table Write Protect 0C000-0FFFF CONFIG6L~5=WRT_4,0x10,Table Write Protect 10000-13FFF CONFIG6L~6=WRT_5,0x20,Table Write Protect 14000-17FFF CONFIG6L~7=WRT_6,0x40,Table Write Protect 18000-1BFFF CONFIG6L~8=WRT_7,0x80,Table Write Protect 1C000-1FFFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x00,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x00,Enabled CONFIG6L~5~1=0x10,0x10,Disabled CONFIG6L~5~2=0x10,0x00,Enabled CONFIG6L~6~1=0x20,0x20,Disabled CONFIG6L~6~2=0x20,0x00,Enabled CONFIG6L~7~1=0x40,0x40,Disabled CONFIG6L~7~2=0x40,0x00,Enabled CONFIG6L~8~1=0x80,0x80,Disabled CONFIG6L~8~2=0x80,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EEPROM Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00200-03FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 04000-07FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 08000-0BFFF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 0C000-0FFFF CONFIG7L~5=EBTR_4,0x10,Table Read Protect 10000-13FFF CONFIG7L~6=EBTR_5,0x20,Table Read Protect 14000-17FFF CONFIG7L~7=EBTR_6,0x40,Table Read Protect 18000-1BFFF CONFIG7L~8=EBTR_7,0x80,Table Read Protect 1C000-1FFFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x00,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x00,Enabled CONFIG7L~5~1=0x10,0x10,Disabled CONFIG7L~5~2=0x10,0x00,Enabled CONFIG7L~6~1=0x20,0x20,Disabled CONFIG7L~6~2=0x20,0x00,Enabled CONFIG7L~7~1=0x40,0x40,Disabled CONFIG7L~7~2=0x40,0x00,Enabled CONFIG7L~8~1=0x80,0x80,Disabled CONFIG7L~8~2=0x80,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F6721] pgmmem=0x0 ~pgmmem=0x1FFFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0x3ff devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x1400 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004=CONFIG3L 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xC,0xC,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xA,0xA,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xF,0x5,EC-Port on RA6 CONFIG1H~1~8=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xF,0x3,0011 EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xF,0x2,HS CONFIG1H~1~11=0xF,0x1,XT CONFIG1H~1~12=0xF,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x08,4.2V CONFIG2L~3~4=0x18,0x00,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3L_unused=0x0 CONFIG3L~1=PMODE,0x3,Processor Mode CONFIG3L~2=ABW,0x30,Address Bus Width CONFIG3L~3=BW,0x40,Bus Width CONFIG3L~4=WAIT,0x80,External Bus Wait CONFIG3L~1~1=0x3,0x3,Microcontroller CONFIG3L~1~2=0x3,0x2,Microprocessor CONFIG3L~1~3=0x3,0x1,Microprocessor w/Boot CONFIG3L~1~4=0x3,0x0,Ext Microcontroller CONFIG3L~2~1=0x30,0x30,20-bit CONFIG3L~2~2=0x30,0x20,16-bit CONFIG3L~2~3=0x30,0x10,12-bit CONFIG3L~2~4=0x30,0x00,8-bit CONFIG3L~3~1=0x40,0x40,16-bit external bus CONFIG3L~3~2=0x40,0x00,8-bit external bus CONFIG3L~4~1=0x80,0x80,Disabled CONFIG3L~4~2=0x80,0x0,Enabled CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=ECCPMX,0x2,ECCP Mux CONFIG3H~3=LPT1OSC,0x04,Low Power Timer1 Osc enable CONFIG3H~4=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RE7-Microcontroller Mode/RB3-All other modes CONFIG3H~2~1=0x2,0x2,Enhanced CCP1 [P1B/P1C] muxed with RE5/RE6 CONFIG3H~2~2=0x2,0x0,Enhanced CCP1 [P1B/P1C] muxed with RH7/RH6 CONFIG3H~3~1=0x04,0x04,Enabled CONFIG3H~3~2=0x04,0x00,Disabled CONFIG3H~4~1=0x80,0x80,MCLR Enabled,RG5 Disabled CONFIG3H~4~2=0x80,0x00,MCLR Disabled, RG5 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=ENHCPU,0x40,Extended CPU Enable CONFIG4L~4=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x40,0x40,Enabled CONFIG4L~3~2=0x40,0x00,Disabled CONFIG4L~4~1=0x80,0x80,Disabled CONFIG4L~4~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-03FFF CONFIG5L~2=CP_1,0x2,Code Protect 04000-07FFF CONFIG5L~3=CP_2,0x4,Code Protect 08000-0BFFF CONFIG5L~4=CP_3,0x8,Code Protect 0C000-0FFFF CONFIG5L~5=CP_4,0x10,Code Protect 10000-13FFF CONFIG5L~6=CP_5,0x20,Code Protect 14000-17FFF CONFIG5L~7=CP_6,0x40,Code Protect 18000-1BFFF CONFIG5L~8=CP_7,0x80,Code Protect 1C000-1FFFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5L~5~1=0x10,0x10,Disabled CONFIG5L~5~2=0x10,0x00,Enabled CONFIG5L~6~1=0x20,0x20,Disabled CONFIG5L~6~2=0x20,0x00,Enabled CONFIG5L~7~1=0x40,0x40,Disabled CONFIG5L~7~2=0x40,0x00,Enabled CONFIG5L~8~1=0x80,0x80,Disabled CONFIG5L~8~2=0x80,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EE Read Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-03FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 04000-07FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 08000-0BFFF CONFIG6L~4=WRT_3,0x8,Table Write Protect 0C000-0FFFF CONFIG6L~5=WRT_4,0x10,Table Write Protect 10000-13FFF CONFIG6L~6=WRT_5,0x20,Table Write Protect 14000-17FFF CONFIG6L~7=WRT_6,0x40,Table Write Protect 18000-1BFFF CONFIG6L~8=WRT_7,0x80,Table Write Protect 1C000-1FFFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x00,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x00,Enabled CONFIG6L~5~1=0x10,0x10,Disabled CONFIG6L~5~2=0x10,0x00,Enabled CONFIG6L~6~1=0x20,0x20,Disabled CONFIG6L~6~2=0x20,0x00,Enabled CONFIG6L~7~1=0x40,0x40,Disabled CONFIG6L~7~2=0x40,0x00,Enabled CONFIG6L~8~1=0x80,0x80,Disabled CONFIG6L~8~2=0x80,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EE Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-03FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 04000-07FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 08000-0BFFF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 0C000-0FFFF CONFIG7L~5=EBTR_4,0x10,Table Read Protect 10000-13FFF CONFIG7L~6=EBTR_5,0x20,Table Read Protect 14000-17FFF CONFIG7L~7=EBTR_6,0x40,Table Read Protect 18000-1BFFF CONFIG7L~8=EBTR_7,0x80,Table Read Protect 1C000-1FFFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x00,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x00,Enabled CONFIG7L~5~1=0x10,0x10,Disabled CONFIG7L~5~2=0x10,0x00,Enabled CONFIG7L~6~1=0x20,0x20,Disabled CONFIG7L~6~2=0x20,0x00,Enabled CONFIG7L~7~1=0x40,0x40,Disabled CONFIG7L~7~2=0x40,0x00,Enabled CONFIG7L~8~1=0x80,0x80,Disabled CONFIG7L~8~2=0x80,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F8310] pgmmem=0x0 ~pgmmem=0xFFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata= ~eedata= devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x0BC0 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004=CONFIG3L 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009= 0x30000A= 0x30000B= 0x30000C=CONFIG7L 0x30000D= CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xC,0xC,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xA,0xA,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xF,0x5,EC-Port on RA6 CONFIG1H~1~8=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xF,0x3,0011 EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xF,0x2,HS CONFIG1H~1~11=0xF,0x1,XT CONFIG1H~1~12=0xF,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x08,4.2V CONFIG2L~3~4=0x18,0x00,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3L_unused=0x0 CONFIG3L~1=WAIT,0x80,External Bus Wait CONFIG3L~2=BW,0x40,Bus Width CONFIG3L~3=PMODE,0x3,Processor Mode CONFIG3L~1~1=0x80,0x80,Disabled CONFIG3L~1~2=0x80,0x0,Enabled CONFIG3L~2~1=0x40,0x40,16-bit external CONFIG3L~2~2=0x40,0x0,8-bit external CONFIG3L~3~1=0x3,0x3,Microcontroller CONFIG3L~3~2=0x3,0x2,Microprocessor CONFIG3L~3~3=0x3,0x1,Microprocessor w/Boot CONFIG3L~3~4=0x3,0x0,Ext Microcontroller CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=LPT1OSC,0x04,Low Power Timer1 Osc enable CONFIG3H~3=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RE7 in microcontroller mode - RB3 in others CONFIG3H~2~1=0x04,0x04,Enabled CONFIG3H~2~2=0x04,0x00,Disabled CONFIG3H~3~1=0x80,0x80,MCLR Enabled, RG5 Disabled CONFIG3H~3~2=0x80,0x00,MCLR Disabled, RG5 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=ENHCPU,0x40,Extended CPU Enable CONFIG4L~3=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x40,0x40,Enabled CONFIG4L~2~2=0x40,0x00,Disabled CONFIG4L~3~1=0x80,0x80,Disabled CONFIG4L~3~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00000-01FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00000-01FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F8390] pgmmem=0x0 ~pgmmem=0xFFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata= ~eedata= devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x0B80 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004=CONFIG3L 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009= 0x30000A= 0x30000B= 0x30000C=CONFIG7L 0x30000D= CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xC,0xC,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xA,0xA,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xF,0x5,EC-Port on RA6 CONFIG1H~1~8=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xF,0x3,0011 EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xF,0x2,HS CONFIG1H~1~11=0xF,0x1,XT CONFIG1H~1~12=0xF,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x08,4.2V CONFIG2L~3~4=0x18,0x00,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3L_unused=0x0 CONFIG3L~1=WAIT,0x80,External Bus Wait CONFIG3L~2=BW,0x40,Bus Width CONFIG3L~3=PMODE,0x3,Processor Mode CONFIG3L~1~1=0x80,0x80,Disabled CONFIG3L~1~2=0x80,0x0,Enabled CONFIG3L~2~1=0x40,0x40,16-bit external CONFIG3L~2~2=0x40,0x0,8-bit external CONFIG3L~3~1=0x3,0x3,Microcontroller CONFIG3L~3~2=0x3,0x2,Microprocessor CONFIG3L~3~3=0x3,0x1,Microprocessor w/Boot CONFIG3L~3~4=0x3,0x0,Ext Microcontroller CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=LPT1OSC,0x04,Low Power Timer1 Osc enable CONFIG3H~3=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RE7 in microcontroller mode - RB3 in others CONFIG3H~2~1=0x04,0x04,Enabled CONFIG3H~2~2=0x04,0x00,Disabled CONFIG3H~3~1=0x80,0x80,MCLR Enabled, RG5 Disabled CONFIG3H~3~2=0x80,0x00,MCLR Disabled, RG5 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=ENHCPU,0x40,Extended CPU Enable CONFIG4L~3=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x40,0x40,Enabled CONFIG4L~2~2=0x40,0x00,Disabled CONFIG4L~3~1=0x80,0x80,Disabled CONFIG4L~3~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00000-01FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00000-01FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F8410] pgmmem=0x0 ~pgmmem=0x3FFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata= ~eedata= devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x06C0 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004=CONFIG3L 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009= 0x30000A= 0x30000B= 0x30000C=CONFIG7L 0x30000D= CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xC,0xC,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xA,0xA,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xF,0x5,EC-Port on RA6 CONFIG1H~1~8=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xF,0x3,0011 EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xF,0x2,HS CONFIG1H~1~11=0xF,0x1,XT CONFIG1H~1~12=0xF,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x08,4.2V CONFIG2L~3~4=0x18,0x00,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3L_unused=0x0 CONFIG3L~1=WAIT,0x80,External Bus Wait CONFIG3L~2=BW,0x40,Bus Width CONFIG3L~3=PMODE,0x3,Processor Mode CONFIG3L~1~1=0x80,0x80,Disabled CONFIG3L~1~2=0x80,0x0,Enabled CONFIG3L~2~1=0x40,0x40,16-bit external CONFIG3L~2~2=0x40,0x0,8-bit external CONFIG3L~3~1=0x3,0x3,Microcontroller CONFIG3L~3~2=0x3,0x2,Microprocessor CONFIG3L~3~3=0x3,0x1,Microprocessor w/Boot CONFIG3L~3~4=0x3,0x0,Ext Microcontroller CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=LPT1OSC,0x04,Low Power Timer1 Osc enable CONFIG3H~3=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RE7 in microcontroller mode - RB3 in others CONFIG3H~2~1=0x04,0x04,Enabled CONFIG3H~2~2=0x04,0x00,Disabled CONFIG3H~3~1=0x80,0x80,MCLR Enabled, RG5 Disabled CONFIG3H~3~2=0x80,0x00,MCLR Disabled, RG5 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=ENHCPU,0x40,Extended CPU Enable CONFIG4L~3=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x40,0x40,Enabled CONFIG4L~2~2=0x40,0x00,Disabled CONFIG4L~3~1=0x80,0x80,Disabled CONFIG4L~3~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00000-03FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00000-03FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F8490] pgmmem=0x0 ~pgmmem=0x3FFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata= ~eedata= devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x0680 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004=CONFIG3L 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009= 0x30000A= 0x30000B= 0x30000C=CONFIG7L 0x30000D= CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xC,0xC,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xA,0xA,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xF,0x5,EC-Port on RA6 CONFIG1H~1~8=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xF,0x3,0011 EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xF,0x2,HS CONFIG1H~1~11=0xF,0x1,XT CONFIG1H~1~12=0xF,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x08,4.2V CONFIG2L~3~4=0x18,0x00,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3L_unused=0x0 CONFIG3L~1=WAIT,0x80,External Bus Wait CONFIG3L~2=BW,0x40,Bus Width CONFIG3L~3=PMODE,0x3,Processor Mode CONFIG3L~1~1=0x80,0x80,Disabled CONFIG3L~1~2=0x80,0x0,Enabled CONFIG3L~2~1=0x40,0x40,16-bit external CONFIG3L~2~2=0x40,0x0,8-bit external CONFIG3L~3~1=0x3,0x3,Microcontroller CONFIG3L~3~2=0x3,0x2,Microprocessor CONFIG3L~3~3=0x3,0x1,Microprocessor w/Boot CONFIG3L~3~4=0x3,0x0,Ext Microcontroller CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=LPT1OSC,0x04,Low Power Timer1 Osc enable CONFIG3H~3=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RE7 in microcontroller mode - RB3 in others CONFIG3H~2~1=0x04,0x04,Enabled CONFIG3H~2~2=0x04,0x00,Disabled CONFIG3H~3~1=0x80,0x80,MCLR Enabled, RG5 Disabled CONFIG3H~3~2=0x80,0x00,MCLR Disabled, RG5 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=ENHCPU,0x40,Extended CPU Enable CONFIG4L~3=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x40,0x40,Enabled CONFIG4L~2~2=0x40,0x00,Disabled CONFIG4L~3~1=0x80,0x80,Disabled CONFIG4L~3~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00000-03FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00000-03FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F8520] pgmmem=0x0 ~pgmmem=0x7fff cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0x3ff devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x0B00 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004=CONFIG3L 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0x7,Oscillator CONFIG1H~2=OSCS,0x20,Osc. Switch Enable CONFIG1H~1~1=0x7,0x7,RC-OSC2 as RA6 CONFIG1H~1~2=0x7,0x6,HS-PLL Enabled CONFIG1H~1~3=0x7,0x5,EC-OSC2 as RA6 CONFIG1H~1~4=0x7,0x4,EC-OSC2 as Clock Out CONFIG1H~1~5=0x7,0x3,RC-OSC2 as Clock Out CONFIG1H~1~6=0x7,0x2,HS CONFIG1H~1~7=0x7,0x1,XT CONFIG1H~1~8=0x7,0x0,LP CONFIG1H~2~1=0x20,0x20,Disabled CONFIG1H~2~2=0x20,0x0,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x2,Brown Out Detect CONFIG2L~3=BODENV,0xC,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x2,0x2,Enabled CONFIG2L~2~2=0x2,0x0,Disabled CONFIG2L~3~1=0xC,0xC,2.5V CONFIG2L~3~2=0xC,0x8,2.7V CONFIG2L~3~3=0xC,0x4,4.2V CONFIG2L~3~4=0xC,0x0,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0xE,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0xE,0xE,1:128 CONFIG2H~2~2=0xE,0xC,1:64 CONFIG2H~2~3=0xE,0xA,1:32 CONFIG2H~2~4=0xE,0x8,1:16 CONFIG2H~2~5=0xE,0x6,1:8 CONFIG2H~2~6=0xE,0x4,1:4 CONFIG2H~2~7=0xE,0x2,1:2 CONFIG2H~2~8=0xE,0x0,1:1 CONFIG3L_unused=0x0 CONFIG3L~1=PMODE,0x3,Processor Mode CONFIG3L~2=WAIT,0x80,External Bus Wait CONFIG3L~1~1=0x3,0x3,Microcontroller CONFIG3L~1~2=0x3,0x2,Microprocessor CONFIG3L~1~3=0x3,0x1,Microprocessor w/Boot CONFIG3L~1~4=0x3,0x0,Ext Microcontroller CONFIG3L~2~1=0x80,0x80,Disabled CONFIG3L~2~2=0x80,0x0,Enabled CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=T1OSCMX,0x2,Timer1 OSC CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RE7 in Microcontroller Mode / RB3 otherwise CONFIG3H~2~1=0x2,0x2,Legacy CONFIG3H~2~2=0x2,0x0,Low Power CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x80,0x80,Disabled CONFIG4L~3~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-01FFF CONFIG5L~2=CP_1,0x2,Code Protect 02000-03FFF CONFIG5L~3=CP_2,0x4,Code Protect 04000-05FFF CONFIG5L~4=CP_3,0x8,Code Protect 06000-07FFF CONFIG5L~5=CP_4,0x10,Code Protect 10000-13FFF CONFIG5L~6=CP_5,0x20,Code Protect 14000-17FFF CONFIG5L~7=CP_6,0x40,Code Protect 18000-1BFFF CONFIG5L~8=CP_7,0x80,Code Protect 1C000-1FFFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5L~5~1=0x10,0x10,Disabled CONFIG5L~5~2=0x10,0x00,Enabled CONFIG5L~6~1=0x20,0x20,Disabled CONFIG5L~6~2=0x20,0x00,Enabled CONFIG5L~7~1=0x40,0x40,Disabled CONFIG5L~7~2=0x40,0x00,Enabled CONFIG5L~8~1=0x80,0x80,Disabled CONFIG5L~8~2=0x80,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EE Read Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-01FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 02000-03FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 04000-05FFF CONFIG6L~4=WRT_3,0x8,Table Write Protect 06000-07FFF CONFIG6L~5=WRT_4,0x10,Table Write Protect 10000-13FFF CONFIG6L~6=WRT_5,0x20,Table Write Protect 14000-17FFF CONFIG6L~7=WRT_6,0x40,Table Write Protect 18000-1BFFF CONFIG6L~8=WRT_7,0x80,Table Write Protect 1C000-1FFFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x00,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x00,Enabled CONFIG6L~5~1=0x10,0x10,Disabled CONFIG6L~5~2=0x10,0x00,Enabled CONFIG6L~6~1=0x20,0x20,Disabled CONFIG6L~6~2=0x20,0x00,Enabled CONFIG6L~7~1=0x40,0x40,Disabled CONFIG6L~7~2=0x40,0x00,Enabled CONFIG6L~8~1=0x80,0x80,Disabled CONFIG6L~8~2=0x80,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EE Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-01FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 02000-03FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 04000-05FFF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 06000-07FFF CONFIG7L~5=EBTR_4,0x10,Table Read Protect 10000-13FFF CONFIG7L~6=EBTR_5,0x20,Table Read Protect 14000-17FFF CONFIG7L~7=EBTR_6,0x40,Table Read Protect 18000-1BFFF CONFIG7L~8=EBTR_7,0x80,Table Read Protect 1C000-1FFFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x00,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x00,Enabled CONFIG7L~5~1=0x10,0x10,Disabled CONFIG7L~5~2=0x10,0x00,Enabled CONFIG7L~6~1=0x20,0x20,Disabled CONFIG7L~6~2=0x20,0x00,Enabled CONFIG7L~7~1=0x40,0x40,Disabled CONFIG7L~7~2=0x40,0x00,Enabled CONFIG7L~8~1=0x80,0x80,Disabled CONFIG7L~8~2=0x80,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F8525] pgmmem=0x0 ~pgmmem=0xBfff cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0x3ff devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x0AC0 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004=CONFIG3L 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=OSCS,0x20,Osc. Switch Enable CONFIG1H~1~1=0xF,0xF,RC-OSC2 as RA6 CONFIG1H~1~2=0xF,0xE,HS oscillator with SW enabled 4x PLL CONFIG1H~1~3=0xF,0xD,EC-OSC2 as RA6, software enabled 4X PLL CONFIG1H~1~4=0xF,0xC,EC-OSC2 as RA6, hardware enabled 4X PLL CONFIG1H~1~5=0xF,0x7,RC-OSC2 as RA6 CONFIG1H~1~6=0xF,0x6,HS-hardware enabled 4X PLL CONFIG1H~1~7=0xF,0x5,EC-OSC2 as RA6 CONFIG1H~1~8=0xF,0x4,EC-OSC2 as divide by 4 CLKOUT CONFIG1H~1~9=0xF,0x3,RC-OSC2 as divide by 4 CLKOUT CONFIG1H~1~10=0xF,0x2,HS CONFIG1H~1~11=0xF,0x1,XT CONFIG1H~1~12=0xF,0x0,LP CONFIG1H~2~1=0x20,0x0,Enabled CONFIG1H~2~2=0x20,0x20,Disabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x2,Brown Out Detect CONFIG2L~3=BODENV,0xC,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x2,0x2,Enabled CONFIG2L~2~2=0x2,0x0,Disabled CONFIG2L~3~1=0xC,0xC,2.0V CONFIG2L~3~2=0xC,0x8,2.7V CONFIG2L~3~3=0xC,0x4,4.2V CONFIG2L~3~4=0xC,0x0,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3L_unused=0x0 CONFIG3L~1=PMODE,0x3,Processor Mode CONFIG3L~2=WAIT,0x80,External Bus Wait CONFIG3L~1~1=0x3,0x3,Microcontroller CONFIG3L~1~2=0x3,0x2,Microprocessor CONFIG3L~1~3=0x3,0x1,Microprocessor w/Boot CONFIG3L~1~4=0x3,0x0,Ext Microcontroller CONFIG3L~2~1=0x80,0x80,Disabled CONFIG3L~2~2=0x80,0x0,Enabled CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=MCLRE,0x80,MCLR enable CONFIG3H~3=ECCPMX,0x2,ECCP Mux CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RE7 in Microcontroller Mode / RB3 otherwise CONFIG3H~2~1=0x80,0x80,MCLR Enabled, RG5 Disabled CONFIG3H~2~2=0x80,0x00,MCLR Disabled, RG5 Enabled CONFIG3H~3~1=0x2,0x2,ECCP1 and ECCP3 are muxed onto RE6-RE3 CONFIG3H~3~2=0x2,0x0,ECCP1 and ECCP3 are muxed onto RH7-RH4 CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x80,0x80,Disabled CONFIG4L~3~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 000800-0003FFF CONFIG5L~2=CP_1,0x2,Code Protect 0004000-007FFF CONFIG5L~3=CP_2,0x4,Code Protect 008000-00BFFF CONFIG5L~4=CP_3,0x8,Code Protect 00C000-00FFFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EE Read Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-003FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 004000-007FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 08000-0BFFF CONFIG6L~4=WRT_3,0x8,Table Write Protect 0C000-0FFFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x00,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EE Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-003FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 004000-07FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 08000-0BFFF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 0C000-0FFFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x00,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F8585] pgmmem=0x0 ~pgmmem=0xBfff cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0x3ff devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x0A40 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004=CONFIG3L 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=OSCS,0x20,Osc. Switch Enable CONFIG1H~1~1=0xF,0xF,RC-OSC2 as RA6 CONFIG1H~1~2=0xF,0xE,HS oscillator with SW enabled 4x PLL CONFIG1H~1~3=0xF,0xD,EC-OSC2 as RA6, software enabled 4X PLL CONFIG1H~1~4=0xF,0xC,EC-OSC2 as RA6, hardware enabled 4X PLL CONFIG1H~1~5=0xF,0x7,RC-OSC2 as RA6 CONFIG1H~1~6=0xF,0x6,HS-hardware enabled 4X PLL CONFIG1H~1~7=0xF,0x5,EC-OSC2 as RA6 CONFIG1H~1~8=0xF,0x4,EC-OSC2 as divide by 4 CLKOUT CONFIG1H~1~9=0xF,0x3,RC-OSC2 as divide by 4 CLKOUT CONFIG1H~1~10=0xF,0x2,HS CONFIG1H~1~11=0xF,0x1,XT CONFIG1H~1~12=0xF,0x0,LP CONFIG1H~2~1=0x20,0x0,Enabled CONFIG1H~2~2=0x20,0x20,Disabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x2,Brown Out Detect CONFIG2L~3=BODENV,0xC,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x2,0x2,Enabled CONFIG2L~2~2=0x2,0x0,Disabled CONFIG2L~3~1=0xC,0xC,2.0V CONFIG2L~3~2=0xC,0x8,2.7V CONFIG2L~3~3=0xC,0x4,4.2V CONFIG2L~3~4=0xC,0x0,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3L_unused=0x0 CONFIG3L~1=PMODE,0x3,Processor Mode CONFIG3L~2=WAIT,0x80,External Bus Wait CONFIG3L~1~1=0x3,0x3,Microcontroller CONFIG3L~1~2=0x3,0x2,Microprocessor CONFIG3L~1~3=0x3,0x1,Microprocessor w/Boot CONFIG3L~1~4=0x3,0x0,Ext Microcontroller CONFIG3L~2~1=0x80,0x80,Disabled CONFIG3L~2~2=0x80,0x0,Enabled CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=MCLRE,0x80,MCLR enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RE7 in Microcontroller Mode / RB3 otherwise CONFIG3H~2~1=0x80,0x80,MCLR Enabled, RG5 Disabled CONFIG3H~2~2=0x80,0x00,MCLR Disabled, RG5 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x80,0x80,Disabled CONFIG4L~3~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 000800-0003FFF CONFIG5L~2=CP_1,0x2,Code Protect 0004000-007FFF CONFIG5L~3=CP_2,0x4,Code Protect 008000-00BFFF CONFIG5L~4=CP_3,0x8,Code Protect 00C000-00FFFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EE Read Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-003FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 004000-007FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 08000-0BFFF CONFIG6L~4=WRT_3,0x8,Table Write Protect 0C000-0FFFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x00,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EE Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-003FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 004000-07FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 08000-0BFFF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 0C000-0FFFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x00,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F8620] pgmmem=0x0 ~pgmmem=0xffff cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0x3ff devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x0640 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004=CONFIG3L 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0x7,Oscillator CONFIG1H~2=OSCS,0x20,Osc. Switch Enable CONFIG1H~1~1=0x7,0x7,RC-OSC2 as RA6 CONFIG1H~1~2=0x7,0x6,HS-PLL Enabled CONFIG1H~1~3=0x7,0x5,EC-OSC2 as RA6 CONFIG1H~1~4=0x7,0x4,EC-OSC2 as Clock Out CONFIG1H~1~5=0x7,0x3,RC-OSC2 as Clock Out CONFIG1H~1~6=0x7,0x2,HS CONFIG1H~1~7=0x7,0x1,XT CONFIG1H~1~8=0x7,0x0,LP CONFIG1H~2~1=0x20,0x20,Disabled CONFIG1H~2~2=0x20,0x0,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x2,Brown Out Detect CONFIG2L~3=BODENV,0xC,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x2,0x2,Enabled CONFIG2L~2~2=0x2,0x0,Disabled CONFIG2L~3~1=0xC,0xC,2.5V CONFIG2L~3~2=0xC,0x8,2.7V CONFIG2L~3~3=0xC,0x4,4.2V CONFIG2L~3~4=0xC,0x0,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0xE,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0xE,0xE,1:128 CONFIG2H~2~2=0xE,0xC,1:64 CONFIG2H~2~3=0xE,0xA,1:32 CONFIG2H~2~4=0xE,0x8,1:16 CONFIG2H~2~5=0xE,0x6,1:8 CONFIG2H~2~6=0xE,0x4,1:4 CONFIG2H~2~7=0xE,0x2,1:2 CONFIG2H~2~8=0xE,0x0,1:1 CONFIG3L_unused=0x0 CONFIG3L~1=PMODE,0x3,Processor Mode CONFIG3L~2=WAIT,0x80,External Bus Wait CONFIG3L~1~1=0x3,0x3,Microcontroller CONFIG3L~1~2=0x3,0x2,Microprocessor CONFIG3L~1~3=0x3,0x1,Microprocessor w/Boot CONFIG3L~1~4=0x3,0x0,Ext Microcontroller CONFIG3L~2~1=0x80,0x80,Disabled CONFIG3L~2~2=0x80,0x0,Enabled CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=T1OSCMX,0x2,Timer1 OSC CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RE7 / RB3 CONFIG3H~2~1=0x2,0x2,Legacy CONFIG3H~2~2=0x2,0x0,Low Power CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x80,0x80,Disabled CONFIG4L~3~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00200-03FFF CONFIG5L~2=CP_1,0x2,Code Protect 04000-07FFF CONFIG5L~3=CP_2,0x4,Code Protect 08000-0BFFF CONFIG5L~4=CP_3,0x8,Code Protect 0C000-0FFFF CONFIG5L~5=CP_4,0x10,Code Protect 10000-13FFF CONFIG5L~6=CP_5,0x20,Code Protect 14000-17FFF CONFIG5L~7=CP_6,0x40,Code Protect 18000-1BFFF CONFIG5L~8=CP_7,0x80,Code Protect 1C000-1FFFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5L~5~1=0x10,0x10,Disabled CONFIG5L~5~2=0x10,0x00,Enabled CONFIG5L~6~1=0x20,0x20,Disabled CONFIG5L~6~2=0x20,0x00,Enabled CONFIG5L~7~1=0x40,0x40,Disabled CONFIG5L~7~2=0x40,0x00,Enabled CONFIG5L~8~1=0x80,0x80,Disabled CONFIG5L~8~2=0x80,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EEPROM Code Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00200-03FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 04000-07FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 08000-0BFFF CONFIG6L~4=WRT_3,0x8,Table Write Protect 0C000-0FFFF CONFIG6L~5=WRT_4,0x10,Table Write Protect 10000-13FFF CONFIG6L~6=WRT_5,0x20,Table Write Protect 14000-17FFF CONFIG6L~7=WRT_6,0x40,Table Write Protect 18000-1BFFF CONFIG6L~8=WRT_7,0x80,Table Write Protect 1C000-1FFFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x00,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x00,Enabled CONFIG6L~5~1=0x10,0x10,Disabled CONFIG6L~5~2=0x10,0x00,Enabled CONFIG6L~6~1=0x20,0x20,Disabled CONFIG6L~6~2=0x20,0x00,Enabled CONFIG6L~7~1=0x40,0x40,Disabled CONFIG6L~7~2=0x40,0x00,Enabled CONFIG6L~8~1=0x80,0x80,Disabled CONFIG6L~8~2=0x80,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EEPROM Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00200-03FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 04000-07FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 08000-0BFFF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 0C000-0FFFF CONFIG7L~5=EBTR_4,0x10,Table Read Protect 10000-13FFF CONFIG7L~6=EBTR_5,0x20,Table Read Protect 14000-17FFF CONFIG7L~7=EBTR_6,0x40,Table Read Protect 18000-1BFFF CONFIG7L~8=EBTR_7,0x80,Table Read Protect 1C000-1FFFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x00,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x00,Enabled CONFIG7L~5~1=0x10,0x10,Disabled CONFIG7L~5~2=0x10,0x00,Enabled CONFIG7L~6~1=0x20,0x20,Disabled CONFIG7L~6~2=0x20,0x00,Enabled CONFIG7L~7~1=0x40,0x40,Disabled CONFIG7L~7~2=0x40,0x00,Enabled CONFIG7L~8~1=0x80,0x80,Disabled CONFIG7L~8~2=0x80,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F8621] pgmmem=0x0 ~pgmmem=0xffff cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0x3ff devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x0A80 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004=CONFIG3L 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=OSCS,0x20,Osc. Switch Enable CONFIG1H~1~1=0xF,0xF,RC-OSC2 as RA6 CONFIG1H~1~2=0xF,0xE,HS oscillator with SW enabled 4x PLL CONFIG1H~1~3=0xF,0xD,EC-OSC2 as RA6, software enabled 4X PLL CONFIG1H~1~4=0xF,0xC,EC-OSC2 as RA6, hardware enabled 4X PLL CONFIG1H~1~5=0xF,0x7,RC-OSC2 as RA6 CONFIG1H~1~6=0xF,0x6,HS-hardware enabled 4X PLL CONFIG1H~1~7=0xF,0x5,EC-OSC2 as RA6 CONFIG1H~1~8=0xF,0x4,EC-OSC2 as divide by 4 CLKOUT CONFIG1H~1~9=0xF,0x3,RC-OSC2 as divide by 4 CLKOUT CONFIG1H~1~10=0xF,0x2,HS CONFIG1H~1~11=0xF,0x1,XT CONFIG1H~1~12=0xF,0x0,LP CONFIG1H~2~1=0x20,0x0,Enabled CONFIG1H~2~2=0x20,0x20,Disabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x2,Brown Out Detect CONFIG2L~3=BODENV,0xC,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x2,0x2,Enabled CONFIG2L~2~2=0x2,0x0,Disabled CONFIG2L~3~1=0xC,0xC,2.0V CONFIG2L~3~2=0xC,0x8,2.7V CONFIG2L~3~3=0xC,0x4,4.2V CONFIG2L~3~4=0xC,0x0,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3L_unused=0x0 CONFIG3L~1=PMODE,0x3,Processor Mode CONFIG3L~2=WAIT,0x80,External Bus Wait CONFIG3L~1~1=0x3,0x3,Microcontroller CONFIG3L~1~2=0x3,0x2,Microprocessor CONFIG3L~1~3=0x3,0x1,Microprocessor w/Boot CONFIG3L~1~4=0x3,0x0,Ext Microcontroller CONFIG3L~2~1=0x80,0x80,Disabled CONFIG3L~2~2=0x80,0x0,Enabled CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=MCLRE,0x80,MCLR enable CONFIG3H~3=ECCPMX,0x2,ECCP Mux CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RE7 in Microcontroller Mode / RB3 otherwise CONFIG3H~2~1=0x80,0x80,MCLR Enabled, RG5 Disabled CONFIG3H~2~2=0x80,0x00,MCLR Disabled, RG5 Enabled CONFIG3H~3~1=0x2,0x2,ECCP1 and ECCP3 are muxed onto RE6-RE3 CONFIG3H~3~2=0x2,0x0,ECCP1 and ECCP3 are muxed onto RH7-RH4 CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x80,0x80,Disabled CONFIG4L~3~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 000800-0003FFF CONFIG5L~2=CP_1,0x2,Code Protect 0004000-007FFF CONFIG5L~3=CP_2,0x4,Code Protect 008000-00BFFF CONFIG5L~4=CP_3,0x8,Code Protect 00C000-00FFFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EE Read Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-003FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 004000-007FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 08000-0BFFF CONFIG6L~4=WRT_3,0x8,Table Write Protect 0C000-0FFFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x00,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EE Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-003FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 004000-07FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 08000-0BFFF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 0C000-0FFFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x00,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F8625] pgmmem=0x0 ~pgmmem=0x17FFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0x3ff devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x13E0 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004=CONFIG3L 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xC,0xC,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xA,0xA,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xF,0x5,EC-Port on RA6 CONFIG1H~1~8=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xF,0x3,0011 EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xF,0x2,HS CONFIG1H~1~11=0xF,0x1,XT CONFIG1H~1~12=0xF,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x08,4.2V CONFIG2L~3~4=0x18,0x00,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3L_unused=0x0 CONFIG3L~1=PMODE,0x3,Processor Mode CONFIG3L~2=ABW,0x30,Address Bus Width CONFIG3L~3=BW,0x40,Bus Width CONFIG3L~4=WAIT,0x80,External Bus Wait CONFIG3L~1~1=0x3,0x3,Microcontroller CONFIG3L~1~2=0x3,0x2,Microprocessor CONFIG3L~1~3=0x3,0x1,Microprocessor w/Boot CONFIG3L~1~4=0x3,0x0,Ext Microcontroller CONFIG3L~2~1=0x30,0x30,20-bit CONFIG3L~2~2=0x30,0x20,16-bit CONFIG3L~2~3=0x30,0x10,12-bit CONFIG3L~2~4=0x30,0x00,8-bit CONFIG3L~3~1=0x40,0x40,16-bit external bus CONFIG3L~3~2=0x40,0x00,8-bit external bus CONFIG3L~4~1=0x80,0x80,Disabled CONFIG3L~4~2=0x80,0x0,Enabled CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=ECCPMX,0x2,ECCP Mux CONFIG3H~3=LPT1OSC,0x04,Low Power Timer1 Osc enable CONFIG3H~4=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RE7-Microcontroller Mode/RB3-All other modes CONFIG3H~2~1=0x2,0x2,Enhanced CCP1 [P1B/P1C] muxed with RE5/RE6 CONFIG3H~2~2=0x2,0x0,Enhanced CCP1 [P1B/P1C] muxed with RH7/RH6 CONFIG3H~3~1=0x04,0x04,Enabled CONFIG3H~3~2=0x04,0x00,Disabled CONFIG3H~4~1=0x80,0x80,MCLR Enabled, RG5 Disabled CONFIG3H~4~2=0x80,0x00,MCLR Disabled, RG5 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=ENHCPU,0x40,Extended CPU Enable CONFIG4L~4=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x40,0x40,Enabled CONFIG4L~3~2=0x40,0x00,Disabled CONFIG4L~4~1=0x80,0x80,Disabled CONFIG4L~4~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-03FFF CONFIG5L~2=CP_1,0x2,Code Protect 04000-07FFF CONFIG5L~3=CP_2,0x4,Code Protect 08000-0BFFF CONFIG5L~4=CP_3,0x8,Code Protect 0C000-0FFFF CONFIG5L~5=CP_4,0x10,Code Protect 10000-13FFF CONFIG5L~6=CP_5,0x20,Code Protect 14000-17FFF CONFIG5L~7=CP_6,0x40,Code Protect 18000-1BFFF CONFIG5L~8=CP_7,0x80,Code Protect 1C000-1FFFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5L~5~1=0x10,0x10,Disabled CONFIG5L~5~2=0x10,0x00,Enabled CONFIG5L~6~1=0x20,0x20,Disabled CONFIG5L~6~2=0x20,0x00,Enabled CONFIG5L~7~1=0x40,0x40,Disabled CONFIG5L~7~2=0x40,0x00,Enabled CONFIG5L~8~1=0x80,0x80,Disabled CONFIG5L~8~2=0x80,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EE Read Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-03FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 04000-07FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 08000-0BFFF CONFIG6L~4=WRT_3,0x8,Table Write Protect 0C000-0FFFF CONFIG6L~5=WRT_4,0x10,Table Write Protect 10000-13FFF CONFIG6L~6=WRT_5,0x20,Table Write Protect 14000-17FFF CONFIG6L~7=WRT_6,0x40,Table Write Protect 18000-1BFFF CONFIG6L~8=WRT_7,0x80,Table Write Protect 1C000-1FFFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x00,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x00,Enabled CONFIG6L~5~1=0x10,0x10,Disabled CONFIG6L~5~2=0x10,0x00,Enabled CONFIG6L~6~1=0x20,0x20,Disabled CONFIG6L~6~2=0x20,0x00,Enabled CONFIG6L~7~1=0x40,0x40,Disabled CONFIG6L~7~2=0x40,0x00,Enabled CONFIG6L~8~1=0x80,0x80,Disabled CONFIG6L~8~2=0x80,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EE Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-03FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 04000-07FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 08000-0BFFF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 0C000-0FFFF CONFIG7L~5=EBTR_4,0x10,Table Read Protect 10000-13FFF CONFIG7L~6=EBTR_5,0x20,Table Read Protect 14000-17FFF CONFIG7L~7=EBTR_6,0x40,Table Read Protect 18000-1BFFF CONFIG7L~8=EBTR_7,0x80,Table Read Protect 1C000-1FFFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x00,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x00,Enabled CONFIG7L~5~1=0x10,0x10,Disabled CONFIG7L~5~2=0x10,0x00,Enabled CONFIG7L~6~1=0x20,0x20,Disabled CONFIG7L~6~2=0x20,0x00,Enabled CONFIG7L~7~1=0x40,0x40,Disabled CONFIG7L~7~2=0x40,0x00,Enabled CONFIG7L~8~1=0x80,0x80,Disabled CONFIG7L~8~2=0x80,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F8680] pgmmem=0x0 ~pgmmem=0xffff cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0x3ff devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x0A00 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004=CONFIG3L 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=OSCS,0x20,Osc. Switch Enable CONFIG1H~1~1=0xF,0xF,RC-OSC2 as RA6 CONFIG1H~1~2=0xF,0xE,HS oscillator with SW enabled 4x PLL CONFIG1H~1~3=0xF,0xD,EC-OSC2 as RA6, software enabled 4X PLL CONFIG1H~1~4=0xF,0xC,EC-OSC2 as RA6, hardware enabled 4X PLL CONFIG1H~1~5=0xF,0x7,RC-OSC2 as RA6 CONFIG1H~1~6=0xF,0x6,HS-hardware enabled 4X PLL CONFIG1H~1~7=0xF,0x5,EC-OSC2 as RA6 CONFIG1H~1~8=0xF,0x4,EC-OSC2 as divide by 4 CLKOUT CONFIG1H~1~9=0xF,0x3,RC-OSC2 as divide by 4 CLKOUT CONFIG1H~1~10=0xF,0x2,HS CONFIG1H~1~11=0xF,0x1,XT CONFIG1H~1~12=0xF,0x0,LP CONFIG1H~2~1=0x20,0x0,Enabled CONFIG1H~2~2=0x20,0x20,Disabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x2,Brown Out Detect CONFIG2L~3=BODENV,0xC,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x2,0x2,Enabled CONFIG2L~2~2=0x2,0x0,Disabled CONFIG2L~3~1=0xC,0xC,2.0V CONFIG2L~3~2=0xC,0x8,2.7V CONFIG2L~3~3=0xC,0x4,4.2V CONFIG2L~3~4=0xC,0x0,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3L_unused=0x0 CONFIG3L~1=PMODE,0x3,Processor Mode CONFIG3L~2=WAIT,0x80,External Bus Wait CONFIG3L~1~1=0x3,0x3,Microcontroller CONFIG3L~1~2=0x3,0x2,Microprocessor CONFIG3L~1~3=0x3,0x1,Microprocessor w/Boot CONFIG3L~1~4=0x3,0x0,Ext Microcontroller CONFIG3L~2~1=0x80,0x80,Disabled CONFIG3L~2~2=0x80,0x0,Enabled CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=MCLRE,0x80,MCLR enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RE7 in Microcontroller Mode / RB3 otherwise CONFIG3H~2~1=0x80,0x80,MCLR Enabled, RG5 Disabled CONFIG3H~2~2=0x80,0x00,MCLR Disabled, RG5 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x80,0x80,Disabled CONFIG4L~3~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 000800-0003FFF CONFIG5L~2=CP_1,0x2,Code Protect 0004000-007FFF CONFIG5L~3=CP_2,0x4,Code Protect 008000-00BFFF CONFIG5L~4=CP_3,0x8,Code Protect 00C000-00FFFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EE Read Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-003FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 004000-007FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 08000-0BFFF CONFIG6L~4=WRT_3,0x8,Table Write Protect 0C000-0FFFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x00,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EE Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-003FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 004000-07FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 08000-0BFFF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 0C000-0FFFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x00,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F8720] pgmmem=0x0 ~pgmmem=0x1ffff cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0x3ff devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x0600 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004=CONFIG3L 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0x7,Oscillator CONFIG1H~2=OSCS,0x20,Osc. Switch Enable CONFIG1H~1~1=0x7,0x7,RC-OSC2 as RA6 CONFIG1H~1~2=0x7,0x6,HS-PLL Enabled CONFIG1H~1~3=0x7,0x5,EC-OSC2 as RA6 CONFIG1H~1~4=0x7,0x4,EC-OSC2 as Clock Out CONFIG1H~1~5=0x7,0x3,RC-OSC2 as Clock Out CONFIG1H~1~6=0x7,0x2,HS CONFIG1H~1~7=0x7,0x1,XT CONFIG1H~1~8=0x7,0x0,LP CONFIG1H~2~1=0x20,0x20,Disabled CONFIG1H~2~2=0x20,0x0,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x2,Brown Out Detect CONFIG2L~3=BODENV,0xC,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x2,0x2,Enabled CONFIG2L~2~2=0x2,0x0,Disabled CONFIG2L~3~1=0xC,0xC,2.5V CONFIG2L~3~2=0xC,0x8,2.7V CONFIG2L~3~3=0xC,0x4,4.2V CONFIG2L~3~4=0xC,0x0,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0xE,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0xE,0xE,1:128 CONFIG2H~2~2=0xE,0xC,1:64 CONFIG2H~2~3=0xE,0xA,1:32 CONFIG2H~2~4=0xE,0x8,1:16 CONFIG2H~2~5=0xE,0x6,1:8 CONFIG2H~2~6=0xE,0x4,1:4 CONFIG2H~2~7=0xE,0x2,1:2 CONFIG2H~2~8=0xE,0x0,1:1 CONFIG3L_unused=0x0 CONFIG3L~1=PMODE,0x3,Processor Mode CONFIG3L~2=WAIT,0x80,External Bus Wait CONFIG3L~1~1=0x3,0x3,Microcontroller CONFIG3L~1~2=0x3,0x2,Microprocessor CONFIG3L~1~3=0x3,0x1,Microprocessor w/Boot CONFIG3L~1~4=0x3,0x0,Ext Microcontroller CONFIG3L~2~1=0x80,0x80,Disabled CONFIG3L~2~2=0x80,0x0,Enabled CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=T1OSCMX,0x2,Timer1 OSC CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RE7 / RB3 CONFIG3H~2~1=0x2,0x2,Legacy CONFIG3H~2~2=0x2,0x0,Low Power CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x80,0x80,Disabled CONFIG4L~3~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00200-03FFF CONFIG5L~2=CP_1,0x2,Code Protect 04000-07FFF CONFIG5L~3=CP_2,0x4,Code Protect 08000-0BFFF CONFIG5L~4=CP_3,0x8,Code Protect 0C000-0FFFF CONFIG5L~5=CP_4,0x10,Code Protect 10000-13FFF CONFIG5L~6=CP_5,0x20,Code Protect 14000-17FFF CONFIG5L~7=CP_6,0x40,Code Protect 18000-1BFFF CONFIG5L~8=CP_7,0x80,Code Protect 1C000-1FFFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5L~5~1=0x10,0x10,Disabled CONFIG5L~5~2=0x10,0x00,Enabled CONFIG5L~6~1=0x20,0x20,Disabled CONFIG5L~6~2=0x20,0x00,Enabled CONFIG5L~7~1=0x40,0x40,Disabled CONFIG5L~7~2=0x40,0x00,Enabled CONFIG5L~8~1=0x80,0x80,Disabled CONFIG5L~8~2=0x80,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EEPROM Code Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00200-03FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 04000-07FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 08000-0BFFF CONFIG6L~4=WRT_3,0x8,Table Write Protect 0C000-0FFFF CONFIG6L~5=WRT_4,0x10,Table Write Protect 10000-13FFF CONFIG6L~6=WRT_5,0x20,Table Write Protect 14000-17FFF CONFIG6L~7=WRT_6,0x40,Table Write Protect 18000-1BFFF CONFIG6L~8=WRT_7,0x80,Table Write Protect 1C000-1FFFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x00,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x00,Enabled CONFIG6L~5~1=0x10,0x10,Disabled CONFIG6L~5~2=0x10,0x00,Enabled CONFIG6L~6~1=0x20,0x20,Disabled CONFIG6L~6~2=0x20,0x00,Enabled CONFIG6L~7~1=0x40,0x40,Disabled CONFIG6L~7~2=0x40,0x00,Enabled CONFIG6L~8~1=0x80,0x80,Disabled CONFIG6L~8~2=0x80,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EEPROM Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00200-03FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 04000-07FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 08000-0BFFF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 0C000-0FFFF CONFIG7L~5=EBTR_4,0x10,Table Read Protect 10000-13FFF CONFIG7L~6=EBTR_5,0x20,Table Read Protect 14000-17FFF CONFIG7L~7=EBTR_6,0x40,Table Read Protect 18000-1BFFF CONFIG7L~8=EBTR_7,0x80,Table Read Protect 1C000-1FFFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x00,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x00,Enabled CONFIG7L~5~1=0x10,0x10,Disabled CONFIG7L~5~2=0x10,0x00,Enabled CONFIG7L~6~1=0x20,0x20,Disabled CONFIG7L~6~2=0x20,0x00,Enabled CONFIG7L~7~1=0x40,0x40,Disabled CONFIG7L~7~2=0x40,0x00,Enabled CONFIG7L~8~1=0x80,0x80,Disabled CONFIG7L~8~2=0x80,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F8721] pgmmem=0x0 ~pgmmem=0x1FFFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0x3ff devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x1420 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004=CONFIG3L 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xC,0xC,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xA,0xA,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xF,0x5,EC-Port on RA6 CONFIG1H~1~8=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xF,0x3,0011 EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xF,0x2,HS CONFIG1H~1~11=0xF,0x1,XT CONFIG1H~1~12=0xF,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x08,4.2V CONFIG2L~3~4=0x18,0x00,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3L_unused=0x0 CONFIG3L~1=PMODE,0x3,Processor Mode CONFIG3L~2=ABW,0x30,Address Bus Width CONFIG3L~3=BW,0x40,Bus Width CONFIG3L~4=WAIT,0x80,External Bus Wait CONFIG3L~1~1=0x3,0x3,Microcontroller CONFIG3L~1~2=0x3,0x2,Microprocessor CONFIG3L~1~3=0x3,0x1,Microprocessor w/Boot CONFIG3L~1~4=0x3,0x0,Ext Microcontroller CONFIG3L~2~1=0x30,0x30,20-bit CONFIG3L~2~2=0x30,0x20,16-bit CONFIG3L~2~3=0x30,0x10,12-bit CONFIG3L~2~4=0x30,0x00,8-bit CONFIG3L~3~1=0x40,0x40,16-bit external bus CONFIG3L~3~2=0x40,0x00,8-bit external bus CONFIG3L~4~1=0x80,0x80,Disabled CONFIG3L~4~2=0x80,0x0,Enabled CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=ECCPMX,0x2,ECCP Mux CONFIG3H~3=LPT1OSC,0x04,Low Power Timer1 Osc enable CONFIG3H~4=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RE7-Microcontroller Mode/RB3-All other modes CONFIG3H~2~1=0x2,0x2,Enhanced CCP1 [P1B/P1C] muxed with RE5/RE6 CONFIG3H~2~2=0x2,0x0,Enhanced CCP1 [P1B/P1C] muxed with RH7/RH6 CONFIG3H~3~1=0x04,0x04,Enabled CONFIG3H~3~2=0x04,0x00,Disabled CONFIG3H~4~1=0x80,0x80,MCLR Enabled,RG5 Disabled CONFIG3H~4~2=0x80,0x00,MCLR Disabled, RG5 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=ENHCPU,0x40,Extended CPU Enable CONFIG4L~4=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x40,0x40,Enabled CONFIG4L~3~2=0x40,0x00,Disabled CONFIG4L~4~1=0x80,0x80,Disabled CONFIG4L~4~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-03FFF CONFIG5L~2=CP_1,0x2,Code Protect 04000-07FFF CONFIG5L~3=CP_2,0x4,Code Protect 08000-0BFFF CONFIG5L~4=CP_3,0x8,Code Protect 0C000-0FFFF CONFIG5L~5=CP_4,0x10,Code Protect 10000-13FFF CONFIG5L~6=CP_5,0x20,Code Protect 14000-17FFF CONFIG5L~7=CP_6,0x40,Code Protect 18000-1BFFF CONFIG5L~8=CP_7,0x80,Code Protect 1C000-1FFFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5L~5~1=0x10,0x10,Disabled CONFIG5L~5~2=0x10,0x00,Enabled CONFIG5L~6~1=0x20,0x20,Disabled CONFIG5L~6~2=0x20,0x00,Enabled CONFIG5L~7~1=0x40,0x40,Disabled CONFIG5L~7~2=0x40,0x00,Enabled CONFIG5L~8~1=0x80,0x80,Disabled CONFIG5L~8~2=0x80,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EE Read Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-03FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 04000-07FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 08000-0BFFF CONFIG6L~4=WRT_3,0x8,Table Write Protect 0C000-0FFFF CONFIG6L~5=WRT_4,0x10,Table Write Protect 10000-13FFF CONFIG6L~6=WRT_5,0x20,Table Write Protect 14000-17FFF CONFIG6L~7=WRT_6,0x40,Table Write Protect 18000-1BFFF CONFIG6L~8=WRT_7,0x80,Table Write Protect 1C000-1FFFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x00,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x00,Enabled CONFIG6L~5~1=0x10,0x10,Disabled CONFIG6L~5~2=0x10,0x00,Enabled CONFIG6L~6~1=0x20,0x20,Disabled CONFIG6L~6~2=0x20,0x00,Enabled CONFIG6L~7~1=0x40,0x40,Disabled CONFIG6L~7~2=0x40,0x00,Enabled CONFIG6L~8~1=0x80,0x80,Disabled CONFIG6L~8~2=0x80,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EE Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-03FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 04000-07FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 08000-0BFFF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 0C000-0FFFF CONFIG7L~5=EBTR_4,0x10,Table Read Protect 10000-13FFF CONFIG7L~6=EBTR_5,0x20,Table Read Protect 14000-17FFF CONFIG7L~7=EBTR_6,0x40,Table Read Protect 18000-1BFFF CONFIG7L~8=EBTR_7,0x80,Table Read Protect 1C000-1FFFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x00,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x00,Enabled CONFIG7L~5~1=0x10,0x10,Disabled CONFIG7L~5~2=0x10,0x00,Enabled CONFIG7L~6~1=0x20,0x20,Disabled CONFIG7L~6~2=0x20,0x00,Enabled CONFIG7L~7~1=0x40,0x40,Disabled CONFIG7L~7~2=0x40,0x00,Enabled CONFIG7L~8~1=0x80,0x80,Disabled CONFIG7L~8~2=0x80,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F1230] pgmmem=0x0 ~pgmmem=0x0FFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0x7f devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x1E00 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004=CONFIG3L 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xC,0xC,EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xE,0xA,EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xF,0x5,EC-Port on RA6 CONFIG1H~1~8=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xF,0x2,HS CONFIG1H~1~10=0xF,0x1,XT CONFIG1H~1~11=0xF,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,BOR Enabled - SBOREN Disabled CONFIG2L~2~2=0x6,0x4,BOR when device active - SBOREN Disabled CONFIG2L~2~3=0x6,0x2,BOR controlled with SBOREN CONFIG2L~2~4=0x6,0x0,BOR Disabled - SBOREN Disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x08,4.2V CONFIG2L~3~4=0x18,0x00,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3L_unused=0x0 CONFIG3L~1=PWMPIN,0x2,PWM Output Pin Reset CONFIG3L~2=LPOL,0x4,Low-Side Transistors Polarity CONFIG3L~3=HPOL,0x8,High-Side Transistors Polarity CONFIG3L~1~1=0x2,0x2,PWM outputs disabled upon RESET CONFIG3L~1~2=0x2,0x0,PWM outputs drive active states upon RESET CONFIG3L~2~1=0x4,0x4,PWM 0, 2, 4 and 6 are active high CONFIG3L~2~2=0x4,0x0,PWM 0, 2, 4 and 6 are active low CONFIG3L~3~1=0x8,0x8,PWM 1, 3, 5, and 7 are active high CONFIG3L~3~2=0x8,0x0,PWM 1, 3, 5, and 7 are active low CONFIG3H_unused=0x0 CONFIG3H~1=MCLRE,0x80,Master Clear Enable CONFIG3H~2=T1OSCMX,0x08,T1OSC Mux bit CONFIG3H~3=FLTAMX,0x01,FLTA Mux bit CONFIG3H~1~1=0x80,0x80,MCLR enabled, RA5 input disabled CONFIG3H~1~2=0x80,0x00,MCLR disabled, RA5 input enabled CONFIG3H~2~1=0x08,0x08,T1OSC reside on RA6 and RA7 CONFIG3H~2~2=0x08,0x00,T1OSC reside on RB2 and RB3 CONFIG3H~3~1=0x01,0x01,FLTA is muxed onto RA5 CONFIG3H~3~2=0x01,0x00,FLTA is muxed onto RA7 CONFIG4L_unused=0x0 CONFIG4L~1=STVREN,0x1,Stack Overflow Reset CONFIG4L~2=ENICPORT,0x08,ICD/ICSP Port Enable bit CONFIG4L~3=BBSIZ,0x30,Boot Block Select bits CONFIG4L~4=ENHCPU,0x40,Enhanced CPU Enable bit CONFIG4L~5=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x08,0x08,Enabled CONFIG4L~2~2=0x08,0x00,Disabled CONFIG4L~3~1=0x30,0x30,Boot Block size is 512 W CONFIG4L~3~2=0x30,0x20,Boot Block size is 512 W CONFIG4L~3~3=0x30,0x10,Boot Block size is 512 W CONFIG4L~3~4=0x30,0x00,Boot Block size is 256 W CONFIG4L~4~1=0x40,0x40,Enabled CONFIG4L~4~2=0x40,0x0,Disabled CONFIG4L~5~1=0x80,0x80,Disabled CONFIG4L~5~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 000200-000FFF CONFIG5L~2=CP_1,0x2,Code Protect 001000-001FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EEPROM Code Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00200-00FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 01000-01FFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EEPROM Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00200-00FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 01000-01FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F1231] pgmmem=0x0 ~pgmmem=0x0FFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0x7f devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x1E80 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004=CONFIG3L 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xC,0xC,EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xE,0xA,EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xF,0x5,EC-Port on RA6 CONFIG1H~1~8=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xF,0x2,HS CONFIG1H~1~10=0xF,0x1,XT CONFIG1H~1~11=0xF,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,BOR Enabled - SBOREN Disabled CONFIG2L~2~2=0x6,0x4,BOR when device active - SBOREN Disabled CONFIG2L~2~3=0x6,0x2,BOR controlled with SBOREN CONFIG2L~2~4=0x6,0x0,BOR Disabled - SBOREN Disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x08,4.2V CONFIG2L~3~4=0x18,0x00,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3L_unused=0x0 CONFIG3L~1=PWMPIN,0x2,PWM Output Pin Reset CONFIG3L~2=LPOL,0x4,Low-Side Transistors Polarity CONFIG3L~3=HPOL,0x8,High-Side Transistors Polarity CONFIG3L~1~1=0x2,0x2,PWM outputs disabled upon RESET CONFIG3L~1~2=0x2,0x0,PWM outputs drive active states upon RESET CONFIG3L~2~1=0x4,0x4,PWM 0, 2, 4 and 6 are active high CONFIG3L~2~2=0x4,0x0,PWM 0, 2, 4 and 6 are active low CONFIG3L~3~1=0x8,0x8,PWM 1, 3, 5, and 7 are active high CONFIG3L~3~2=0x8,0x0,PWM 1, 3, 5, and 7 are active low CONFIG3H_unused=0x0 CONFIG3H~1=MCLRE,0x80,Master Clear Enable CONFIG3H~2=T1OSCMX,0x08,T1OSC Mux bit CONFIG3H~3=FLTAMX,0x01,FLTA Mux bit CONFIG3H~1~1=0x80,0x80,MCLR enabled, RA5 input disabled CONFIG3H~1~2=0x80,0x00,MCLR disabled, RA5 input enabled CONFIG3H~2~1=0x08,0x08,T1OSC reside on RA6 and RA7 CONFIG3H~2~2=0x08,0x00,T1OSC reside on RB2 and RB3 CONFIG3H~3~1=0x01,0x01,FLTA is muxed onto RA5 CONFIG3H~3~2=0x01,0x00,FLTA is muxed onto RA7 CONFIG4L_unused=0x0 CONFIG4L~1=STVREN,0x1,Stack Overflow Reset CONFIG4L~2=ENICPORT,0x08,ICD/ICSP Port Enable bit CONFIG4L~3=BBSIZ,0x30,Boot Block Select bits CONFIG4L~4=ENHCPU,0x40,Enhanced CPU Enable bit CONFIG4L~5=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x08,0x08,Enabled CONFIG4L~2~2=0x08,0x00,Disabled CONFIG4L~3~1=0x30,0x30,Boot Block size is 1 KW if EN8K = 1/ 512 W if EN8K = 0 CONFIG4L~3~2=0x30,0x20,Boot Block size is 1 KW if EN8K = 1/ 512 W if EN8K = 0 CONFIG4L~3~3=0x30,0x10,Boot Block size is 512 W CONFIG4L~3~4=0x30,0x00,Boot Block size is 256 W CONFIG4L~4~1=0x40,0x40,Enabled CONFIG4L~4~2=0x40,0x0,Disabled CONFIG4L~5~1=0x80,0x80,Disabled CONFIG4L~5~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 000200-000FFF CONFIG5L~2=CP_1,0x2,Code Protect 001000-001FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EEPROM Code Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00200-00FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 01000-01FFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EEPROM Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00200-00FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 01000-01FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F1330] pgmmem=0x0 ~pgmmem=0x1FFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0x7f devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x1E20 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004=CONFIG3L 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xC,0xC,EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xE,0xA,EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xF,0x5,EC-Port on RA6 CONFIG1H~1~8=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xF,0x2,HS CONFIG1H~1~10=0xF,0x1,XT CONFIG1H~1~11=0xF,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,BOR Enabled - SBOREN Disabled CONFIG2L~2~2=0x6,0x4,BOR when device active - SBOREN Disabled CONFIG2L~2~3=0x6,0x2,BOR controlled with SBOREN CONFIG2L~2~4=0x6,0x0,BOR Disabled - SBOREN Disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x08,4.2V CONFIG2L~3~4=0x18,0x00,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3L_unused=0x0 CONFIG3L~1=PWMPIN,0x2,PWM Output Pin Reset CONFIG3L~2=LPOL,0x4,Low-Side Transistors Polarity CONFIG3L~3=HPOL,0x8,High-Side Transistors Polarity CONFIG3L~1~1=0x2,0x2,PWM outputs disabled upon RESET CONFIG3L~1~2=0x2,0x0,PWM outputs drive active states upon RESET CONFIG3L~2~1=0x4,0x4,PWM 0, 2, 4 and 6 are active high CONFIG3L~2~2=0x4,0x0,PWM 0, 2, 4 and 6 are active low CONFIG3L~3~1=0x8,0x8,PWM 1, 3, 5, and 7 are active high CONFIG3L~3~2=0x8,0x0,PWM 1, 3, 5, and 7 are active low CONFIG3H_unused=0x0 CONFIG3H~1=MCLRE,0x80,Master Clear Enable CONFIG3H~2=T1OSCMX,0x08,T1OSC Mux bit CONFIG3H~3=FLTAMX,0x01,FLTA Mux bit CONFIG3H~1~1=0x80,0x80,MCLR enabled, RA5 input disabled CONFIG3H~1~2=0x80,0x00,MCLR disabled, RA5 input enabled CONFIG3H~2~1=0x08,0x08,T1OSC reside on RA6 and RA7 CONFIG3H~2~2=0x08,0x00,T1OSC reside on RB2 and RB3 CONFIG3H~3~1=0x01,0x01,FLTA is muxed onto RA5 CONFIG3H~3~2=0x01,0x00,FLTA is muxed onto RA7 CONFIG4L_unused=0x0 CONFIG4L~1=STVREN,0x1,Stack Overflow Reset CONFIG4L~2=ENICPORT,0x08,ICD/ICSP Port Enable bit CONFIG4L~3=BBSIZ,0x30,Boot Block Select bits CONFIG4L~4=ENHCPU,0x40,Enhanced CPU Enable bit CONFIG4L~5=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x08,0x08,Enabled CONFIG4L~2~2=0x08,0x00,Disabled CONFIG4L~3~1=0x30,0x30,Boot Block size is 1 KW CONFIG4L~3~2=0x30,0x20,Boot Block size is 1 KW CONFIG4L~3~3=0x30,0x10,Boot Block size is 512 W CONFIG4L~3~4=0x30,0x00,Boot Block size is 256 W CONFIG4L~4~1=0x40,0x40,Enabled CONFIG4L~4~2=0x40,0x0,Disabled CONFIG4L~5~1=0x80,0x80,Disabled CONFIG4L~5~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 000200-000FFF CONFIG5L~2=CP_1,0x2,Code Protect 001000-001FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EEPROM Code Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00200-00FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 01000-01FFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EEPROM Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00200-00FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 01000-01FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F1331] pgmmem=0x0 ~pgmmem=0x1FFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0x7f devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x1EA0 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004=CONFIG3L 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xC,0xC,EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xE,0xA,EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xF,0x5,EC-Port on RA6 CONFIG1H~1~8=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xF,0x2,HS CONFIG1H~1~10=0xF,0x1,XT CONFIG1H~1~11=0xF,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,BOR Enabled - SBOREN Disabled CONFIG2L~2~2=0x6,0x4,BOR when device active - SBOREN Disabled CONFIG2L~2~3=0x6,0x2,BOR controlled with SBOREN CONFIG2L~2~4=0x6,0x0,BOR Disabled - SBOREN Disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x08,4.2V CONFIG2L~3~4=0x18,0x00,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3L_unused=0x0 CONFIG3L~1=PWMPIN,0x2,PWM Output Pin Reset CONFIG3L~2=LPOL,0x4,Low-Side Transistors Polarity CONFIG3L~3=HPOL,0x8,High-Side Transistors Polarity CONFIG3L~1~1=0x2,0x2,PWM outputs disabled upon RESET CONFIG3L~1~2=0x2,0x0,PWM outputs drive active states upon RESET CONFIG3L~2~1=0x4,0x4,PWM 0, 2, 4 and 6 are active high CONFIG3L~2~2=0x4,0x0,PWM 0, 2, 4 and 6 are active low CONFIG3L~3~1=0x8,0x8,PWM 1, 3, 5, and 7 are active high CONFIG3L~3~2=0x8,0x0,PWM 1, 3, 5, and 7 are active low CONFIG3H_unused=0x0 CONFIG3H~1=MCLRE,0x80,Master Clear Enable CONFIG3H~2=T1OSCMX,0x08,T1OSC Mux bit CONFIG3H~3=FLTAMX,0x01,FLTA Mux bit CONFIG3H~1~1=0x80,0x80,MCLR enabled, RA5 input disabled CONFIG3H~1~2=0x80,0x00,MCLR disabled, RA5 input enabled CONFIG3H~2~1=0x08,0x08,T1OSC reside on RA6 and RA7 CONFIG3H~2~2=0x08,0x00,T1OSC reside on RB2 and RB3 CONFIG3H~3~1=0x01,0x01,FLTA is muxed onto RA5 CONFIG3H~3~2=0x01,0x00,FLTA is muxed onto RA7 CONFIG4L_unused=0x0 CONFIG4L~1=STVREN,0x1,Stack Overflow Reset CONFIG4L~2=ENICPORT,0x08,ICD/ICSP Port Enable bit CONFIG4L~3=BBSIZ,0x30,Boot Block Select bits CONFIG4L~4=ENHCPU,0x40,Enhanced CPU Enable bit CONFIG4L~5=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x08,0x08,Enabled CONFIG4L~2~2=0x08,0x00,Disabled CONFIG4L~3~1=0x30,0x30,Boot Block size is 1 KW if EN8K = 1/ 512 W if EN8K = 0 CONFIG4L~3~2=0x30,0x20,Boot Block size is 1 KW if EN8K = 1/ 512 W if EN8K = 0 CONFIG4L~3~3=0x30,0x10,Boot Block size is 512 W CONFIG4L~3~4=0x30,0x00,Boot Block size is 256 W CONFIG4L~4~1=0x40,0x40,Enabled CONFIG4L~4~2=0x40,0x0,Disabled CONFIG4L~5~1=0x80,0x80,Disabled CONFIG4L~5~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 000200-000FFF CONFIG5L~2=CP_1,0x2,Code Protect 001000-001FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EEPROM Code Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00200-00FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 01000-01FFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EEPROM Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00200-00FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 01000-01FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F2221] pgmmem=0x0 ~pgmmem=0xFFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0xff devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x2160 configslots=14 0x300000=CONFIG1L 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004=CONFIG3L 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007=CONFIG4H 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A= 0x30000B= 0x30000C= 0x30000D= CONFIG1L_unused=0x00 CONFIG1H_unused=0x00 CONFIG1H~1=FOSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail Safe Monitor Clock Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Enable CONFIG1H~1~1=0xC,0xC,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xF,0xA,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xF,0x5,EC-Port on RA6 CONFIG1H~1~8=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xF,0x3,0011 EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xF,0x2,HS CONFIG1H~1~11=0xF,0x1,XT CONFIG1H~1~12=0xF,0x0,LP CONFIG1H~2~1=0x40,0x40,Enabled CONFIG1H~2~2=0x40,0x00,Disabled CONFIG1H~3~1=0x80,0x80,Enabled CONFIG1H~3~2=0x80,0x00,Disabled CONFIG2L_unused=0x00 CONFIG2L~1=PWRTEN,0x01,Power-up Timer Enable CONFIG2L~2=BOREN,0x06,Brown-out Reset Enable CONFIG2L~3=BORV,0x18,Brown-out Reset Voltage CONFIG2L~1~1=0x01,0x01,Disabled CONFIG2L~1~2=0x01,0x00,Enabled CONFIG2L~2~1=0x06,0x06,Enabled In Hardware, SBOREN Ignored CONFIG2L~2~2=0x06,0x04,Enabled When Not In SLEEP, SBOREN Ignored CONFIG2L~2~3=0x06,0x02,Controlled By SBOREN CONFIG2L~2~4=0x06,0x00,Disabled, SBOREN Ignored CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x08,4.2V CONFIG2L~3~4=0x18,0x00,4.5V CONFIG2H_unused=0x00 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Timer Postscale CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x001e,0x001e,1:32,768 CONFIG2H~2~2=0x001e,0x001c,1:16,384 CONFIG2H~2~3=0x001e,0x001a,1:8,192 CONFIG2H~2~4=0x001e,0x0018,1:4,096 CONFIG2H~2~5=0x001e,0x0016,1:2,048 CONFIG2H~2~6=0x001e,0x0014,1:1,024 CONFIG2H~2~7=0x001e,0x0012,1:512 CONFIG2H~2~8=0x001e,0x0010,1:256 CONFIG2H~2~9=0x001e,0x000e,1:128 CONFIG2H~2~10=0x001e,0x000c,1:64 CONFIG2H~2~11=0x001e,0x000a,1:32 CONFIG2H~2~12=0x001e,0x0008,1:16 CONFIG2H~2~13=0x001e,0x0006,1:8 CONFIG2H~2~14=0x001e,0x0004,1:4 CONFIG2H~2~15=0x001e,0x0002,1:2 CONFIG2H~2~16=0x001e,0x0000,1:1 CONFIG3L_unused=0x00 CONFIG3H_unused=0x00 CONFIG3H~1=CCP2MX,0x01,CCP2 Mux CONFIG3H~2=PBADEN,0x02,Port B A/D Enable CONFIG3H~3=LPT1OSC,0x04,Low Power Timer1 Osc Enable CONFIG3H~4=MCLRE,0x80,MCLR Pin Enable CONFIG3H~1~1=0x01,0x01,CCP2 I/O Muxed With RC1 CONFIG3H~1~2=0x01,0x00,CCP2 I/O Muxed With RB3 CONFIG3H~2~1=0x02,0x02,Port B[4:0] Are Analog Inputs on Reset CONFIG3H~2~2=0x02,0x00,Port B[4:0] Are Digital I/O on Reset CONFIG3H~3~1=0x04,0x04,Low Power Consumption, Low Noise Immunity CONFIG3H~3~2=0x04,0x00,High Power Consumption, High Noise Immunity CONFIG3H~4~1=0x80,0x80,MCLR Enabled, RE3 Input Pin Disabled CONFIG3H~4~2=0x80,0x00,MCLR Disabled, RE3 Input Pin Enabled CONFIG4L_unused=0x00 CONFIG4L~1=STVREN,0x01,Stack Overflow Reset Enable CONFIG4L~2=LVP,0x04,Low Voltage Programming Enable CONFIG4L~3=BBSIZ,0x30,Boot Block Size Select CONFIG4L~4=ENHCPU,0x40,Enhanced CPU Enable CONFIG4L~5=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x01,0x01,Enabled CONFIG4L~1~2=0x01,0x00,Disabled CONFIG4L~2~1=0x04,0x04,Enabled CONFIG4L~2~2=0x04,0x00,Disabled CONFIG4L~3~1=0x30,0x30,512 W (512 W) CONFIG4L~3~2=0x30,0x20,512 W (512 W) CONFIG4L~3~3=0x30,0x10,512 W (512 W) CONFIG4L~3~4=0x30,0x00,256 W (256 W) CONFIG4L~4~1=0x40,0x40,Enabled CONFIG4L~4~2=0x40,0x00,Disabled CONFIG4L~5~1=0x80,0x80,Disabled CONFIG4L~5~2=0x80,0x00,Enabled CONFIG4H_unused=0x00 CONFIG5L_unused=0x00 CONFIG5L~1=CP_0,0x01,Code Protect Block 0 CONFIG5L~2=CP_1,0x02,Code Protect Block 1 CONFIG5L~1~1=0x01,0x01,Disabled CONFIG5L~1~2=0x01,0x00,Enabled CONFIG5L~2~1=0x02,0x02,Disabled CONFIG5L~2~2=0x02,0x00,Enabled CONFIG5H_unused=0x00 CONFIG5H~1=CPB,0x40,Code Protect Boot CONFIG5H~2=CPD,0x80,Code Protect Data EEPROM CONFIG5H~1~1=0x40,0x40,Disabled CONFIG5H~1~2=0x40,0x00,Enabled CONFIG5H~2~1=0x80,0x80,Disabled CONFIG5H~2~2=0x80,0x00,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F2321] pgmmem=0x0 ~pgmmem=0x1FFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0xff devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x2120 configslots=14 0x300000=CONFIG1L 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004=CONFIG3L 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007=CONFIG4H 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A= 0x30000B= 0x30000C= 0x30000D= CONFIG1L_unused=0x00 CONFIG1H_unused=0x00 CONFIG1H~1=FOSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail Safe Monitor Clock Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Enable CONFIG1H~1~1=0xC,0xC,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xF,0xA,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xF,0x5,EC-Port on RA6 CONFIG1H~1~8=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xF,0x3,0011 EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xF,0x2,HS CONFIG1H~1~11=0xF,0x1,XT CONFIG1H~1~12=0xF,0x0,LP CONFIG1H~2~1=0x40,0x40,Enabled CONFIG1H~2~2=0x40,0x00,Disabled CONFIG1H~3~1=0x80,0x80,Enabled CONFIG1H~3~2=0x80,0x00,Disabled CONFIG2L_unused=0x00 CONFIG2L~1=PWRTEN,0x01,Power-up Timer Enable CONFIG2L~2=BOREN,0x06,Brown-out Reset Enable CONFIG2L~3=BORV,0x18,Brown-out Reset Voltage CONFIG2L~1~1=0x01,0x01,Disabled CONFIG2L~1~2=0x01,0x00,Enabled CONFIG2L~2~1=0x06,0x06,Enabled In Hardware, SBOREN Ignored CONFIG2L~2~2=0x06,0x04,Enabled When Not In SLEEP, SBOREN Ignored CONFIG2L~2~3=0x06,0x02,Controlled By SBOREN CONFIG2L~2~4=0x06,0x00,Disabled, SBOREN Ignored CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x08,4.2V CONFIG2L~3~4=0x18,0x00,4.5V CONFIG2H_unused=0x00 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Timer Postscale CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x001e,0x001e,1:32,768 CONFIG2H~2~2=0x001e,0x001c,1:16,384 CONFIG2H~2~3=0x001e,0x001a,1:8,192 CONFIG2H~2~4=0x001e,0x0018,1:4,096 CONFIG2H~2~5=0x001e,0x0016,1:2,048 CONFIG2H~2~6=0x001e,0x0014,1:1,024 CONFIG2H~2~7=0x001e,0x0012,1:512 CONFIG2H~2~8=0x001e,0x0010,1:256 CONFIG2H~2~9=0x001e,0x000e,1:128 CONFIG2H~2~10=0x001e,0x000c,1:64 CONFIG2H~2~11=0x001e,0x000a,1:32 CONFIG2H~2~12=0x001e,0x0008,1:16 CONFIG2H~2~13=0x001e,0x0006,1:8 CONFIG2H~2~14=0x001e,0x0004,1:4 CONFIG2H~2~15=0x001e,0x0002,1:2 CONFIG2H~2~16=0x001e,0x0000,1:1 CONFIG3L_unused=0x00 CONFIG3H_unused=0x00 CONFIG3H~1=CCP2MX,0x01,CCP2 Mux CONFIG3H~2=PBADEN,0x02,Port B A/D Enable CONFIG3H~3=LPT1OSC,0x04,Low Power Timer1 Osc Enable CONFIG3H~4=MCLRE,0x80,MCLR Pin Enable CONFIG3H~1~1=0x01,0x01,CCP2 I/O Muxed With RC1 CONFIG3H~1~2=0x01,0x00,CCP2 I/O Muxed With RB3 CONFIG3H~2~1=0x02,0x02,Port B[4:0] Are Analog Inputs on Reset CONFIG3H~2~2=0x02,0x00,Port B[4:0] Are Digital I/O on Reset CONFIG3H~3~1=0x04,0x04,Low Power Consumption, Low Noise Immunity CONFIG3H~3~2=0x04,0x00,High Power Consumption, High Noise Immunity CONFIG3H~4~1=0x80,0x80,MCLR Enabled, RE3 Input Pin Disabled CONFIG3H~4~2=0x80,0x00,MCLR Disabled, RE3 Input Pin Enabled CONFIG4L_unused=0x00 CONFIG4L~1=STVREN,0x01,Stack Overflow Reset Enable CONFIG4L~2=LVP,0x04,Low Voltage Programming Enable CONFIG4L~3=BBSIZ,0x30,Boot Block Size Select CONFIG4L~4=ENHCPU,0x40,Enhanced CPU Enable CONFIG4L~5=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x01,0x01,Enabled CONFIG4L~1~2=0x01,0x00,Disabled CONFIG4L~2~1=0x04,0x04,Enabled CONFIG4L~2~2=0x04,0x00,Disabled CONFIG4L~3~1=0x30,0x30,1 KW (1K W) CONFIG4L~3~2=0x30,0x20,1 KW (1K W) CONFIG4L~3~3=0x30,0x10,512 W (512 W) CONFIG4L~3~4=0x30,0x00,256 W (256 W) CONFIG4L~4~1=0x40,0x40,Enabled CONFIG4L~4~2=0x40,0x00,Disabled CONFIG4L~5~1=0x80,0x80,Disabled CONFIG4L~5~2=0x80,0x00,Enabled CONFIG4H_unused=0x00 CONFIG5L_unused=0x00 CONFIG5L~1=CP_0,0x01,Code Protect Block 0 CONFIG5L~2=CP_1,0x02,Code Protect Block 1 CONFIG5L~1~1=0x01,0x01,Disabled CONFIG5L~1~2=0x01,0x00,Enabled CONFIG5L~2~1=0x02,0x02,Disabled CONFIG5L~2~2=0x02,0x00,Enabled CONFIG5H_unused=0x00 CONFIG5H~1=CPB,0x40,Code Protect Boot CONFIG5H~2=CPD,0x80,Code Protect Data EEPROM CONFIG5H~1~1=0x40,0x40,Disabled CONFIG5H~1~2=0x40,0x00,Enabled CONFIG5H~2~1=0x80,0x80,Disabled CONFIG5H~2~2=0x80,0x00,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F2423] pgmmem=0x0 ~pgmmem=0x3FFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x0 ~eedata=0xff devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFF0 id=0x1150 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xC,0xC,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xE,0xA,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xF,0x5,EC-Port on RA6 CONFIG1H~1~8=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xF,0x3,0011 EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xF,0x2,HS CONFIG1H~1~11=0xF,0x1,XT CONFIG1H~1~12=0xF,0x0,LP CONFIG1H~2~1=0x40,0x40,Enabled CONFIG1H~2~2=0x40,0x0,Disabled CONFIG1H~3~1=0x80,0x80,Enabled CONFIG1H~3~2=0x80,0x0,Disabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x08,4.2V CONFIG2L~3~4=0x18,0x00,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=PBADEN,0x2,PortB A/D Enable CONFIG3H~3=LPT1OSC,0x04,Low Power Timer1 Osc enable CONFIG3H~4=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RB3 CONFIG3H~2~1=0x2,0x2,PORTB<4:0> configured as analog inputs on RESET CONFIG3H~2~2=0x2,0x0,PORTB<4:0> configured as digital I/O on RESET CONFIG3H~3~1=0x04,0x04,Enabled CONFIG3H~3~2=0x04,0x00,Disabled CONFIG3H~4~1=0x80,0x80,MCLR Enabled,RE3 Disabled CONFIG3H~4~2=0x80,0x00,MCLR Disabled,RE3 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=ENHCPU,0x40,Extended CPU Enable CONFIG4L~4=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x40,0x40,Enabled CONFIG4L~3~2=0x40,0x00,Disabled CONFIG4L~4~1=0x80,0x80,Disabled CONFIG4L~4~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-01FFF CONFIG5L~2=CP_1,0x2,Code Protect 02000-03FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EEPROM Code Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-01FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 02000-03FFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTC,0x20,Config. Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTD,0x80,Data EEPROM Write Protect CONFIG6H~1~1=0x20,0x20,Disabled CONFIG6H~1~2=0x20,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x80,0x80,Disabled CONFIG6H~3~2=0x80,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-01FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 02000-03FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F2450] pgmmem=0x0 ~pgmmem=0x3FFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata= ~eedata= devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x2420 configslots=14 0x300000=CONFIG1L 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1L_unused=0x0 CONFIG1L~1=USBPLL,0x20,Full-Speed USB Clock Source Selection CONFIG1L~2=CPUDIV,0x18,CPU System Clock Postscaler CONFIG1L~3=PLLDIV,0x07,96MHz PLL Prescaler CONFIG1L~1~1=0x20,0x20,Clock src from 96MHz PLL/2 CONFIG1L~1~2=0x20,0x00,Clock src from OSC1/OSC2 CONFIG1L~2~1=0x18,0x18,[OSC1/OSC2 Src: /4][96MHz PLL Src: /6] CONFIG1L~2~2=0x18,0x10,[OSC1/OSC2 Src: /3][96MHz PLL Src: /4] CONFIG1L~2~3=0x18,0x08,[OSC1/OSC2 Src: /2][96MHz PLL Src: /3] CONFIG1L~2~4=0x18,0x00,[OSC1/OSC2 Src: /1][96MHz PLL Src: /2] CONFIG1L~3~1=0x07,0x07,Divide by 12 (48MHz input) CONFIG1L~3~2=0x07,0x06,Divide by 10 (40MHz input) CONFIG1L~3~3=0x07,0x05,Divide by 6 (24MHz input) CONFIG1L~3~4=0x07,0x04,Divide by 5 (20MHz input) CONFIG1L~3~5=0x07,0x03,Divide by 4 (16MHz input) CONFIG1L~3~6=0x07,0x02,Divide by 3 (12MHz input) CONFIG1L~3~7=0x07,0x01,Divide by 2 (8MHz input) CONFIG1L~3~8=0x07,0x00,No Divide (4MHz input) CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xE,0xE,HS: HS+PLL, USB-HS CONFIG1H~1~2=0xE,0xC,HS: USB-HS CONFIG1H~1~3=0xF,0xB,INTOSC: USB-HS CONFIG1H~1~4=0xF,0xA,INTOSC: USB-XT CONFIG1H~1~5=0xF,0x9,INTOSC: INTOSC+CLK0{RA6}, USB-EC CONFIG1H~1~6=0xF,0x8,INTOSC: INTOSC+RA6, USB-EC CONFIG1H~1~7=0xF,0x7,EC: EC+PLL, EC+PLL+CLKO{RA6}, USB-EC CONFIG1H~1~8=0xF,0x6,EC: EC+PLL, EC+PLL+RA6, USB-EC CONFIG1H~1~9=0xF,0x5,EC: EC+CLKO{RA6}, USB-EC CONFIG1H~1~10=0xF,0x4,EC: EC+RA6, USB-EC CONFIG1H~1~11=0xE,0x2,XT: XT+PLL, USB-XT CONFIG1H~1~12=0xE,0x0,XT: USB-XT CONFIG1H~2~1=0x40,0x40,Enabled CONFIG1H~2~2=0x40,0x0,Disabled CONFIG1H~3~1=0x80,0x80,Enabled CONFIG1H~3~2=0x80,0x0,Disabled CONFIG2L_unused=0x0 CONFIG2L~1=VREGEN,0x20,USB Voltage Regulator CONFIG2L~2=PUT,0x1,Power Up Timer CONFIG2L~3=BODEN,0x6,Brown Out Detect CONFIG2L~4=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x20,0x20,Enabled CONFIG2L~1~2=0x20,0x00,Disabled CONFIG2L~2~1=0x1,0x1,Disabled CONFIG2L~2~2=0x1,0x0,Enabled CONFIG2L~3~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~3~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~3~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~3~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~4~1=0x18,0x18,2.0V CONFIG2L~4~2=0x18,0x10,2.7V CONFIG2L~4~3=0x18,0x08,4.2V CONFIG2L~4~4=0x18,0x00,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=PBADEN,0x2,PortB A/D Enable CONFIG3H~2=LPT1OSC,0x04,Low Power Timer1 Osc enable CONFIG3H~3=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x2,0x2,PORTB<4:0> configured as analog inputs on RESET CONFIG3H~1~2=0x2,0x0,PORTB<4:0> configured as digital I/O on RESET CONFIG3H~2~1=0x04,0x04,Enabled CONFIG3H~2~2=0x04,0x00,Disabled CONFIG3H~3~1=0x80,0x80,MCLR Enabled,RE3 Disabled CONFIG3H~3~2=0x80,0x00,MCLR Disabled,RE3 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=BBSIZ,0x8,Boot Block Size Select CONFIG4L~4=ENICPORT,0x20,Dedicated In-Circuit Port {ICD/ICSP} CONFIG4L~5=ENHCPU,0x40,Extended CPU Enable CONFIG4L~6=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x8,0x8,2 KW CONFIG4L~3~2=0x8,0x0,1 KW CONFIG4L~4~1=0x20,0x20,Enabled CONFIG4L~4~2=0x20,0x00,Disabled CONFIG4L~5~1=0x40,0x40,Enabled CONFIG4L~5~2=0x40,0x00,Disabled CONFIG4L~6~1=0x80,0x80,Disabled CONFIG4L~6~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-01FFF CONFIG5L~2=CP_1,0x2,Code Protect 02000-03FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x40,0x40,Disabled CONFIG5H~1~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-01FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 02000-03FFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTC,0x20,Config. Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~1~1=0x20,0x20,Disabled CONFIG6H~1~2=0x20,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-01FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 02000-03FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE_24xx05 prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F2480] pgmmem=0x0 ~pgmmem=0x3FFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0xff devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x1AE0 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xC,0xC,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xE,0xA,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xF,0x5,EC-Port on RA6 CONFIG1H~1~8=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xF,0x3,0011 EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xF,0x2,HS CONFIG1H~1~11=0xF,0x1,XT CONFIG1H~1~12=0xF,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x08,4.2V CONFIG2L~3~4=0x18,0x00,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=PBADEN,0x2,PortB A/D Enable CONFIG3H~2=LPT1OSC,0x04,Low Power Timer1 Osc enable CONFIG3H~3=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x2,0x2,PORTB<4:0> configured as analog inputs on RESET CONFIG3H~1~2=0x2,0x0,PORTB<4:0> configured as digital I/O on RESET CONFIG3H~2~1=0x04,0x04,Enabled CONFIG3H~2~2=0x04,0x00,Disabled CONFIG3H~3~1=0x80,0x80,MCLR Enabled,RE3 Disabled CONFIG3H~3~2=0x80,0x00,MCLR Disabled, RE3 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=BBSIZ,0x10,Boot Block Size Select CONFIG4L~4=ENHCPU,0x40,Extended CPU Enable CONFIG4L~5=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x10,0x10,2 KW CONFIG4L~3~2=0x10,0x00,1 KW CONFIG4L~4~1=0x40,0x40,Enabled CONFIG4L~4~2=0x40,0x00,Disabled CONFIG4L~5~1=0x80,0x80,Disabled CONFIG4L~5~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-01FFF CONFIG5L~2=CP_1,0x2,Code Protect 02000-03FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EE Read Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-01FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 02000-03FFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EE Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-01FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 02000-03FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F2523] pgmmem=0x0 ~pgmmem=0x7FFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0xff devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFF0 id=0x1110 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xC,0xC,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xE,0xA,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xF,0x5,EC-Port on RA6 CONFIG1H~1~8=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xF,0x3,0011 EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xF,0x2,HS CONFIG1H~1~11=0xF,0x1,XT CONFIG1H~1~12=0xF,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x08,4.2V CONFIG2L~3~4=0x18,0x00,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=PBADEN,0x2,PortB A/D Enable CONFIG3H~3=LPT1OSC,0x04,Low Power Timer1 Osc enable CONFIG3H~4=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RB3 CONFIG3H~2~1=0x2,0x2,PORTB<4:0> configured as analog inputs on RESET CONFIG3H~2~2=0x2,0x0,PORTB<4:0> configured as digital I/O on RESET CONFIG3H~3~1=0x04,0x04,Enabled CONFIG3H~3~2=0x04,0x00,Disabled CONFIG3H~4~1=0x80,0x80,MCLR Enabled,RE3 Disabled CONFIG3H~4~2=0x80,0x00,MCLR Disabled,RE3 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=ENHCPU,0x40,Extended CPU Enable CONFIG4L~4=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x40,0x40,Enabled CONFIG4L~3~2=0x40,0x00,Disabled CONFIG4L~4~1=0x80,0x80,Disabled CONFIG4L~4~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-01FFF CONFIG5L~2=CP_1,0x2,Code Protect 02000-03FFF CONFIG5L~3=CP_2,0x4,Code Protect 04000-05FFF CONFIG5L~4=CP_3,0x8,Code Protect 06000-07FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EEPROM Code Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-01FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 02000-03FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 04000-05FFF CONFIG6L~4=WRT_3,0x8,Table Write Protect 06000-07FFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x00,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EEPROM Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-01FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 02000-03FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 04000-05FFF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 06000-07FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x00,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F2580] pgmmem=0x0 ~pgmmem=0x7FFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0xff devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x1AC0 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xC,0xC,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xE,0xA,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xF,0x5,EC-Port on RA6 CONFIG1H~1~8=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xF,0x3,0011 EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xF,0x2,HS CONFIG1H~1~11=0xF,0x1,XT CONFIG1H~1~12=0xF,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x08,4.2V CONFIG2L~3~4=0x18,0x00,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=PBADEN,0x2,PortB A/D Enable CONFIG3H~2=LPT1OSC,0x04,Low Power Timer1 Osc enable CONFIG3H~3=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x2,0x2,PORTB<4:0> configured as analog inputs on RESET CONFIG3H~1~2=0x2,0x0,PORTB<4:0> configured as digital I/O on RESET CONFIG3H~2~1=0x04,0x04,Enabled CONFIG3H~2~2=0x04,0x00,Disabled CONFIG3H~3~1=0x80,0x80,MCLR Enabled,RE3 Disabled CONFIG3H~3~2=0x80,0x00,MCLR Disabled, RE3 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=BBSIZ,0x10,Boot Block Size Select CONFIG4L~4=ENHCPU,0x40,Extended CPU Enable CONFIG4L~5=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x10,0x10,2 KW CONFIG4L~3~2=0x10,0x00,1 KW CONFIG4L~4~1=0x40,0x40,Enabled CONFIG4L~4~2=0x40,0x00,Disabled CONFIG4L~5~1=0x80,0x80,Disabled CONFIG4L~5~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-01FFF CONFIG5L~2=CP_1,0x2,Code Protect 02000-03FFF CONFIG5L~3=CP_2,0x4,Code Protect 04000-05FFF CONFIG5L~4=CP_3,0x8,Code Protect 06000-07FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EE Read Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-01FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 02000-03FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 04000-05FFF CONFIG6L~4=WRT_3,0x8,Table Write Protect 06000-07FFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x00,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EE Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-01FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 02000-03FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 04000-05FFF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 06000-07FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x00,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F2682] pgmmem=0x0 ~pgmmem=0x13FFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0x3ff devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x2700 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xC,0xC,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xE,0xA,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xF,0x5,EC-Port on RA6 CONFIG1H~1~8=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xF,0x3,0011 EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xF,0x2,HS CONFIG1H~1~11=0xF,0x1,XT CONFIG1H~1~12=0xF,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x08,4.2V CONFIG2L~3~4=0x18,0x00,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=PBADEN,0x2,PortB A/D Enable CONFIG3H~2=LPT1OSC,0x04,Low Power Timer1 Osc enable CONFIG3H~3=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x2,0x2,PORTB<4> and <1:0> configured as analog inputs on RESET CONFIG3H~1~2=0x2,0x0,PORTB<4> and <1:0> configured as digital I/O on RESET CONFIG3H~2~1=0x04,0x04,Enabled CONFIG3H~2~2=0x04,0x00,Disabled CONFIG3H~3~1=0x80,0x80,MCLR Enabled,RE3 Disabled CONFIG3H~3~2=0x80,0x00,MCLR Disabled, RE3 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=BBSIZ,0x30,Boot Block Size CONFIG4L~4=ENHCPU,0x40,Extended CPU Enable CONFIG4L~5=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x20,0x20,4K Words (8 Kbytes) CONFIG4L~3~2=0x30,0x10,2K Words (4 Kbytes) CONFIG4L~3~3=0x30,0x00,1K Words (2 Kbytes) CONFIG4L~4~1=0x40,0x40,Enabled CONFIG4L~4~2=0x40,0x00,Disabled CONFIG4L~5~1=0x80,0x80,Disabled CONFIG4L~5~2=0x80,0x0,Enabled CONFIG5L_unused=0x20 CONFIG5L~1=CP_0,0x1,Code Protect 00800-03FFF CONFIG5L~2=CP_1,0x2,Code Protect 04000-07FFF CONFIG5L~3=CP_2,0x4,Code Protect 08000-0BFFF CONFIG5L~4=CP_3,0x8,Code Protect 0C000-0FFFF CONFIG5L~5=CP_4,0x10,Code Protect 10000-13FFF CONFIG5L~6=CP_5,0x20,Code Protect 14000-17FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5L~5~1=0x10,0x10,Disabled CONFIG5L~5~2=0x10,0x00,Enabled CONFIG5L~6~1=0x20,0x20,Disabled CONFIG5L~6~2=0x20,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EE Read Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x20 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-03FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 04000-07FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 08000-0BFFF CONFIG6L~4=WRT_3,0x8,Table Write Protect 0C000-0FFFF CONFIG6L~5=WRT_4,0x10,Table Write Protect 10000-13FFF CONFIG6L~6=WRT_5,0x20,Table Write Protect 14000-17FFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x00,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x00,Enabled CONFIG6L~5~1=0x10,0x10,Disabled CONFIG6L~5~2=0x10,0x00,Enabled CONFIG6L~6~1=0x20,0x20,Disabled CONFIG6L~6~2=0x20,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EE Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x20 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-03FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 04000-07FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 08000-0BFFF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 0C000-0FFFF CONFIG7L~5=EBTR_4,0x10,Table Read Protect 10000-13FFF CONFIG7L~6=EBTR_5,0x20,Table Read Protect 14000-17FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x00,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x00,Enabled CONFIG7L~5~1=0x10,0x10,Disabled CONFIG7L~5~2=0x10,0x00,Enabled CONFIG7L~6~1=0x20,0x20,Disabled CONFIG7L~6~2=0x20,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE_24xx05 prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F2685] pgmmem=0x0 ~pgmmem=0x17FFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0x3ff devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x2720 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xC,0xC,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xE,0xA,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xF,0x5,EC-Port on RA6 CONFIG1H~1~8=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xF,0x3,0011 EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xF,0x2,HS CONFIG1H~1~11=0xF,0x1,XT CONFIG1H~1~12=0xF,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x08,4.2V CONFIG2L~3~4=0x18,0x00,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=PBADEN,0x2,PortB A/D Enable CONFIG3H~2=LPT1OSC,0x04,Low Power Timer1 Osc enable CONFIG3H~3=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x2,0x2,PORTB<4> and <1:0> configured as analog inputs on RESET CONFIG3H~1~2=0x2,0x0,PORTB<4> and <1:0> configured as digital I/O on RESET CONFIG3H~2~1=0x04,0x04,Enabled CONFIG3H~2~2=0x04,0x00,Disabled CONFIG3H~3~1=0x80,0x80,MCLR Enabled,RE3 Disabled CONFIG3H~3~2=0x80,0x00,MCLR Disabled, RE3 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=BBSIZ,0x30,Boot Block Size CONFIG4L~4=ENHCPU,0x40,Extended CPU Enable CONFIG4L~5=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x20,0x20,4K Words (8 Kbytes) CONFIG4L~3~2=0x30,0x10,2K Words (4 Kbytes) CONFIG4L~3~3=0x30,0x00,1K Words (2 Kbytes) CONFIG4L~4~1=0x40,0x40,Enabled CONFIG4L~4~2=0x40,0x00,Disabled CONFIG4L~5~1=0x80,0x80,Disabled CONFIG4L~5~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-03FFF CONFIG5L~2=CP_1,0x2,Code Protect 04000-07FFF CONFIG5L~3=CP_2,0x4,Code Protect 08000-0BFFF CONFIG5L~4=CP_3,0x8,Code Protect 0C000-0FFFF CONFIG5L~5=CP_4,0x10,Code Protect 10000-13FFF CONFIG5L~6=CP_5,0x20,Code Protect 14000-17FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5L~5~1=0x10,0x10,Disabled CONFIG5L~5~2=0x10,0x00,Enabled CONFIG5L~6~1=0x20,0x20,Disabled CONFIG5L~6~2=0x20,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EE Read Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-03FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 04000-07FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 08000-0BFFF CONFIG6L~4=WRT_3,0x8,Table Write Protect 0C000-0FFFF CONFIG6L~5=WRT_4,0x10,Table Write Protect 10000-13FFF CONFIG6L~6=WRT_5,0x20,Table Write Protect 14000-17FFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x00,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x00,Enabled CONFIG6L~5~1=0x10,0x10,Disabled CONFIG6L~5~2=0x10,0x00,Enabled CONFIG6L~6~1=0x20,0x20,Disabled CONFIG6L~6~2=0x20,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EE Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-03FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 04000-07FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 08000-0BFFF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 0C000-0FFFF CONFIG7L~5=EBTR_4,0x10,Table Read Protect 10000-13FFF CONFIG7L~6=EBTR_5,0x20,Table Read Protect 14000-17FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x00,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x00,Enabled CONFIG7L~5~1=0x10,0x10,Disabled CONFIG7L~5~2=0x10,0x00,Enabled CONFIG7L~6~1=0x20,0x20,Disabled CONFIG7L~6~2=0x20,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE_24xx05 prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F4221] pgmmem=0x0 ~pgmmem=0xFFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0xff devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x2140 configslots=14 0x300000=CONFIG1L 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004=CONFIG3L 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007=CONFIG4H 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A= 0x30000B= 0x30000C= 0x30000D= CONFIG1L_unused=0x00 CONFIG1H_unused=0x00 CONFIG1H~1=FOSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail Safe Monitor Clock Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Enable CONFIG1H~1~1=0xC,0xC,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xF,0xA,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xF,0x5,EC-Port on RA6 CONFIG1H~1~8=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xF,0x3,0011 EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xF,0x2,HS CONFIG1H~1~11=0xF,0x1,XT CONFIG1H~1~12=0xF,0x0,LP CONFIG1H~2~1=0x40,0x40,Enabled CONFIG1H~2~2=0x40,0x00,Disabled CONFIG1H~3~1=0x80,0x80,Enabled CONFIG1H~3~2=0x80,0x00,Disabled CONFIG2L_unused=0x00 CONFIG2L~1=PWRTEN,0x01,Power-up Timer Enable CONFIG2L~2=BOREN,0x06,Brown-out Reset Enable CONFIG2L~3=BORV,0x18,Brown-out Reset Voltage CONFIG2L~1~1=0x01,0x01,Disabled CONFIG2L~1~2=0x01,0x00,Enabled CONFIG2L~2~1=0x06,0x06,Enabled In Hardware, SBOREN Ignored CONFIG2L~2~2=0x06,0x04,Enabled When Not In SLEEP, SBOREN Ignored CONFIG2L~2~3=0x06,0x02,Controlled By SBOREN CONFIG2L~2~4=0x06,0x00,Disabled, SBOREN Ignored CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x08,4.2V CONFIG2L~3~4=0x18,0x00,4.5V CONFIG2H_unused=0x00 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Timer Postscale CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x001e,0x001e,1:32,768 CONFIG2H~2~2=0x001e,0x001c,1:16,384 CONFIG2H~2~3=0x001e,0x001a,1:8,192 CONFIG2H~2~4=0x001e,0x0018,1:4,096 CONFIG2H~2~5=0x001e,0x0016,1:2,048 CONFIG2H~2~6=0x001e,0x0014,1:1,024 CONFIG2H~2~7=0x001e,0x0012,1:512 CONFIG2H~2~8=0x001e,0x0010,1:256 CONFIG2H~2~9=0x001e,0x000e,1:128 CONFIG2H~2~10=0x001e,0x000c,1:64 CONFIG2H~2~11=0x001e,0x000a,1:32 CONFIG2H~2~12=0x001e,0x0008,1:16 CONFIG2H~2~13=0x001e,0x0006,1:8 CONFIG2H~2~14=0x001e,0x0004,1:4 CONFIG2H~2~15=0x001e,0x0002,1:2 CONFIG2H~2~16=0x001e,0x0000,1:1 CONFIG3L_unused=0x00 CONFIG3H_unused=0x00 CONFIG3H~1=CCP2MX,0x01,CCP2 Mux CONFIG3H~2=PBADEN,0x02,Port B A/D Enable CONFIG3H~3=LPT1OSC,0x04,Low Power Timer1 Osc Enable CONFIG3H~4=MCLRE,0x80,MCLR Pin Enable CONFIG3H~1~1=0x01,0x01,CCP2 I/O Muxed With RC1 CONFIG3H~1~2=0x01,0x00,CCP2 I/O Muxed With RB3 CONFIG3H~2~1=0x02,0x02,Port B[4:0] Are Analog Inputs on Reset CONFIG3H~2~2=0x02,0x00,Port B[4:0] Are Digital I/O on Reset CONFIG3H~3~1=0x04,0x04,Low Power Consumption, Low Noise Immunity CONFIG3H~3~2=0x04,0x00,High Power Consumption, High Noise Immunity CONFIG3H~4~1=0x80,0x80,MCLR Enabled, RE3 Input Pin Disabled CONFIG3H~4~2=0x80,0x00,MCLR Disabled, RE3 Input Pin Enabled CONFIG4L_unused=0x00 CONFIG4L~1=STVREN,0x01,Stack Overflow Reset Enable CONFIG4L~2=LVP,0x04,Low Voltage Programming Enable CONFIG4L~3=BBSIZ,0x30,Boot Block Size Select CONFIG4L~4=ENHCPU,0x40,Enhanced CPU Enable CONFIG4L~5=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x01,0x01,Enabled CONFIG4L~1~2=0x01,0x00,Disabled CONFIG4L~2~1=0x04,0x04,Enabled CONFIG4L~2~2=0x04,0x00,Disabled CONFIG4L~3~1=0x30,0x30,512 W (512 W) CONFIG4L~3~2=0x30,0x20,512 W (512 W) CONFIG4L~3~3=0x30,0x10,512 W (512 W) CONFIG4L~3~4=0x30,0x00,256 W (256 W) CONFIG4L~4~1=0x40,0x40,Enabled CONFIG4L~4~2=0x40,0x00,Disabled CONFIG4L~5~1=0x80,0x80,Disabled CONFIG4L~5~2=0x80,0x00,Enabled CONFIG4H_unused=0x00 CONFIG5L_unused=0x00 CONFIG5L~1=CP_0,0x01,Code Protect Block 0 CONFIG5L~2=CP_1,0x02,Code Protect Block 1 CONFIG5L~1~1=0x01,0x01,Disabled CONFIG5L~1~2=0x01,0x00,Enabled CONFIG5L~2~1=0x02,0x02,Disabled CONFIG5L~2~2=0x02,0x00,Enabled CONFIG5H_unused=0x00 CONFIG5H~1=CPB,0x40,Code Protect Boot CONFIG5H~2=CPD,0x80,Code Protect Data EEPROM CONFIG5H~1~1=0x40,0x40,Disabled CONFIG5H~1~2=0x40,0x00,Enabled CONFIG5H~2~1=0x80,0x80,Disabled CONFIG5H~2~2=0x80,0x00,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F4321] pgmmem=0x0 ~pgmmem=0x1FFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0xff devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x2100 configslots=14 0x300000=CONFIG1L 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004=CONFIG3L 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007=CONFIG4H 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A= 0x30000B= 0x30000C= 0x30000D= CONFIG1L_unused=0x00 CONFIG1H_unused=0x00 CONFIG1H~1=FOSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail Safe Monitor Clock Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Enable CONFIG1H~1~1=0xC,0xC,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xF,0xA,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xF,0x5,EC-Port on RA6 CONFIG1H~1~8=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xF,0x3,0011 EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xF,0x2,HS CONFIG1H~1~11=0xF,0x1,XT CONFIG1H~1~12=0xF,0x0,LP CONFIG1H~2~1=0x40,0x40,Enabled CONFIG1H~2~2=0x40,0x00,Disabled CONFIG1H~3~1=0x80,0x80,Enabled CONFIG1H~3~2=0x80,0x00,Disabled CONFIG2L_unused=0x00 CONFIG2L~1=PWRTEN,0x01,Power-up Timer Enable CONFIG2L~2=BOREN,0x06,Brown-out Reset Enable CONFIG2L~3=BORV,0x18,Brown-out Reset Voltage CONFIG2L~1~1=0x01,0x01,Disabled CONFIG2L~1~2=0x01,0x00,Enabled CONFIG2L~2~1=0x06,0x06,Enabled In Hardware, SBOREN Ignored CONFIG2L~2~2=0x06,0x04,Enabled When Not In SLEEP, SBOREN Ignored CONFIG2L~2~3=0x06,0x02,Controlled By SBOREN CONFIG2L~2~4=0x06,0x00,Disabled, SBOREN Ignored CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x08,4.2V CONFIG2L~3~4=0x18,0x00,4.5V CONFIG2H_unused=0x00 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Timer Postscale CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x001e,0x001e,1:32,768 CONFIG2H~2~2=0x001e,0x001c,1:16,384 CONFIG2H~2~3=0x001e,0x001a,1:8,192 CONFIG2H~2~4=0x001e,0x0018,1:4,096 CONFIG2H~2~5=0x001e,0x0016,1:2,048 CONFIG2H~2~6=0x001e,0x0014,1:1,024 CONFIG2H~2~7=0x001e,0x0012,1:512 CONFIG2H~2~8=0x001e,0x0010,1:256 CONFIG2H~2~9=0x001e,0x000e,1:128 CONFIG2H~2~10=0x001e,0x000c,1:64 CONFIG2H~2~11=0x001e,0x000a,1:32 CONFIG2H~2~12=0x001e,0x0008,1:16 CONFIG2H~2~13=0x001e,0x0006,1:8 CONFIG2H~2~14=0x001e,0x0004,1:4 CONFIG2H~2~15=0x001e,0x0002,1:2 CONFIG2H~2~16=0x001e,0x0000,1:1 CONFIG3L_unused=0x00 CONFIG3H_unused=0x00 CONFIG3H~1=CCP2MX,0x01,CCP2 Mux CONFIG3H~2=PBADEN,0x02,Port B A/D Enable CONFIG3H~3=LPT1OSC,0x04,Low Power Timer1 Osc Enable CONFIG3H~4=MCLRE,0x80,MCLR Pin Enable CONFIG3H~1~1=0x01,0x01,CCP2 I/O Muxed With RC1 CONFIG3H~1~2=0x01,0x00,CCP2 I/O Muxed With RB3 CONFIG3H~2~1=0x02,0x02,Port B[4:0] Are Analog Inputs on Reset CONFIG3H~2~2=0x02,0x00,Port B[4:0] Are Digital I/O on Reset CONFIG3H~3~1=0x04,0x04,Low Power Consumption, Low Noise Immunity CONFIG3H~3~2=0x04,0x00,High Power Consumption, High Noise Immunity CONFIG3H~4~1=0x80,0x80,MCLR Enabled, RE3 Input Pin Disabled CONFIG3H~4~2=0x80,0x00,MCLR Disabled, RE3 Input Pin Enabled CONFIG4L_unused=0x00 CONFIG4L~1=STVREN,0x01,Stack Overflow Reset Enable CONFIG4L~2=LVP,0x04,Low Voltage Programming Enable CONFIG4L~3=BBSIZ,0x30,Boot Block Size Select CONFIG4L~4=ENHCPU,0x40,Enhanced CPU Enable CONFIG4L~5=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x01,0x01,Enabled CONFIG4L~1~2=0x01,0x00,Disabled CONFIG4L~2~1=0x04,0x04,Enabled CONFIG4L~2~2=0x04,0x00,Disabled CONFIG4L~3~1=0x30,0x30,1 KW (1K W) CONFIG4L~3~2=0x30,0x20,1 KW (1K W) CONFIG4L~3~3=0x30,0x10,512 W (512 W) CONFIG4L~3~4=0x30,0x00,256 W (256 W) CONFIG4L~4~1=0x40,0x40,Enabled CONFIG4L~4~2=0x40,0x00,Disabled CONFIG4L~5~1=0x80,0x80,Disabled CONFIG4L~5~2=0x80,0x00,Enabled CONFIG4H_unused=0x00 CONFIG5L_unused=0x00 CONFIG5L~1=CP_0,0x01,Code Protect Block 0 CONFIG5L~2=CP_1,0x02,Code Protect Block 1 CONFIG5L~1~1=0x01,0x01,Disabled CONFIG5L~1~2=0x01,0x00,Enabled CONFIG5L~2~1=0x02,0x02,Disabled CONFIG5L~2~2=0x02,0x00,Enabled CONFIG5H_unused=0x00 CONFIG5H~1=CPB,0x40,Code Protect Boot CONFIG5H~2=CPD,0x80,Code Protect Data EEPROM CONFIG5H~1~1=0x40,0x40,Disabled CONFIG5H~1~2=0x40,0x00,Enabled CONFIG5H~2~1=0x80,0x80,Disabled CONFIG5H~2~2=0x80,0x00,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F4423] pgmmem=0x0 ~pgmmem=0x3FFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x0 ~eedata=0xff devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFF0 id=0x10D0 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xC,0xC,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xE,0xA,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xF,0x5,EC-Port on RA6 CONFIG1H~1~8=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xF,0x3,0011 EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xF,0x2,HS CONFIG1H~1~11=0xF,0x1,XT CONFIG1H~1~12=0xF,0x0,LP CONFIG1H~2~1=0x40,0x40,Enabled CONFIG1H~2~2=0x40,0x0,Disabled CONFIG1H~3~1=0x80,0x80,Enabled CONFIG1H~3~2=0x80,0x0,Disabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x08,4.2V CONFIG2L~3~4=0x18,0x00,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=PBADEN,0x2,PortB A/D Enable CONFIG3H~3=LPT1OSC,0x04,Low Power Timer1 Osc enable CONFIG3H~4=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RB3 CONFIG3H~2~1=0x2,0x2,PORTB<4:0> configured as analog inputs on RESET CONFIG3H~2~2=0x2,0x0,PORTB<4:0> configured as digital I/O on RESET CONFIG3H~3~1=0x04,0x04,Enabled CONFIG3H~3~2=0x04,0x00,Disabled CONFIG3H~4~1=0x80,0x80,MCLR Enabled,RE3 Disabled CONFIG3H~4~2=0x80,0x00,MCLR Disabled,RE3 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=ENHCPU,0x40,Extended CPU Enable CONFIG4L~4=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x40,0x40,Enabled CONFIG4L~3~2=0x40,0x00,Disabled CONFIG4L~4~1=0x80,0x80,Disabled CONFIG4L~4~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-01FFF CONFIG5L~2=CP_1,0x2,Code Protect 02000-03FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EEPROM Code Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-01FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 02000-03FFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTC,0x20,Config. Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTD,0x80,Data EEPROM Write Protect CONFIG6H~1~1=0x20,0x20,Disabled CONFIG6H~1~2=0x20,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x80,0x80,Disabled CONFIG6H~3~2=0x80,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-01FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 02000-03FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F4450] pgmmem=0x0 ~pgmmem=0x3FFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata= ~eedata= devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x2400 configslots=14 0x300000=CONFIG1L 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1L_unused=0x0 CONFIG1L~1=USBPLL,0x20,Full-Speed USB Clock Source Selection CONFIG1L~2=CPUDIV,0x18,CPU System Clock Postscaler CONFIG1L~3=PLLDIV,0x07,96MHz PLL Prescaler CONFIG1L~1~1=0x20,0x20,Clock src from 96MHz PLL/2 CONFIG1L~1~2=0x20,0x00,Clock src from OSC1/OSC2 CONFIG1L~2~1=0x18,0x18,[OSC1/OSC2 Src: /4][96MHz PLL Src: /6] CONFIG1L~2~2=0x18,0x10,[OSC1/OSC2 Src: /3][96MHz PLL Src: /4] CONFIG1L~2~3=0x18,0x08,[OSC1/OSC2 Src: /2][96MHz PLL Src: /3] CONFIG1L~2~4=0x18,0x00,[OSC1/OSC2 Src: /1][96MHz PLL Src: /2] CONFIG1L~3~1=0x07,0x07,Divide by 12 (48MHz input) CONFIG1L~3~2=0x07,0x06,Divide by 10 (40MHz input) CONFIG1L~3~3=0x07,0x05,Divide by 6 (24MHz input) CONFIG1L~3~4=0x07,0x04,Divide by 5 (20MHz input) CONFIG1L~3~5=0x07,0x03,Divide by 4 (16MHz input) CONFIG1L~3~6=0x07,0x02,Divide by 3 (12MHz input) CONFIG1L~3~7=0x07,0x01,Divide by 2 (8MHz input) CONFIG1L~3~8=0x07,0x00,No Divide (4MHz input) CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xE,0xE,HS: HS+PLL, USB-HS CONFIG1H~1~2=0xE,0xC,HS: USB-HS CONFIG1H~1~3=0xF,0xB,INTOSC: USB-HS CONFIG1H~1~4=0xF,0xA,INTOSC: USB-XT CONFIG1H~1~5=0xF,0x9,INTOSC: INTOSC+CLK0{RA6}, USB-EC CONFIG1H~1~6=0xF,0x8,INTOSC: INTOSC+RA6, USB-EC CONFIG1H~1~7=0xF,0x7,EC: EC+PLL, EC+PLL+CLKO{RA6}, USB-EC CONFIG1H~1~8=0xF,0x6,EC: EC+PLL, EC+PLL+RA6, USB-EC CONFIG1H~1~9=0xF,0x5,EC: EC+CLKO{RA6}, USB-EC CONFIG1H~1~10=0xF,0x4,EC: EC+RA6, USB-EC CONFIG1H~1~11=0xE,0x2,XT: XT+PLL, USB-XT CONFIG1H~1~12=0xE,0x0,XT: USB-XT CONFIG1H~2~1=0x40,0x40,Enabled CONFIG1H~2~2=0x40,0x0,Disabled CONFIG1H~3~1=0x80,0x80,Enabled CONFIG1H~3~2=0x80,0x0,Disabled CONFIG2L_unused=0x0 CONFIG2L~1=VREGEN,0x20,USB Voltage Regulator CONFIG2L~2=PUT,0x1,Power Up Timer CONFIG2L~3=BODEN,0x6,Brown Out Detect CONFIG2L~4=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x20,0x20,Enabled CONFIG2L~1~2=0x20,0x00,Disabled CONFIG2L~2~1=0x1,0x1,Disabled CONFIG2L~2~2=0x1,0x0,Enabled CONFIG2L~3~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~3~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~3~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~3~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~4~1=0x18,0x18,2.0V CONFIG2L~4~2=0x18,0x10,2.7V CONFIG2L~4~3=0x18,0x08,4.2V CONFIG2L~4~4=0x18,0x00,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=PBADEN,0x2,PortB A/D Enable CONFIG3H~2=LPT1OSC,0x04,Low Power Timer1 Osc enable CONFIG3H~3=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x2,0x2,PORTB<4:0> configured as analog inputs on RESET CONFIG3H~1~2=0x2,0x0,PORTB<4:0> configured as digital I/O on RESET CONFIG3H~2~1=0x04,0x04,Enabled CONFIG3H~2~2=0x04,0x00,Disabled CONFIG3H~3~1=0x80,0x80,MCLR Enabled,RE3 Disabled CONFIG3H~3~2=0x80,0x00,MCLR Disabled,RE3 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=BBSIZ,0x8,Boot Block Size Select CONFIG4L~4=ENICPORT,0x20,Dedicated In-Circuit Port {ICD/ICSP} CONFIG4L~5=ENHCPU,0x40,Extended CPU Enable CONFIG4L~6=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x8,0x8,2 KW CONFIG4L~3~2=0x8,0x0,1 KW CONFIG4L~4~1=0x20,0x20,Enabled CONFIG4L~4~2=0x20,0x00,Disabled CONFIG4L~5~1=0x40,0x40,Enabled CONFIG4L~5~2=0x40,0x00,Disabled CONFIG4L~6~1=0x80,0x80,Disabled CONFIG4L~6~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-01FFF CONFIG5L~2=CP_1,0x2,Code Protect 02000-03FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x40,0x40,Disabled CONFIG5H~1~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-01FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 02000-03FFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTC,0x20,Config. Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~1~1=0x20,0x20,Disabled CONFIG6H~1~2=0x20,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-01FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 02000-03FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE_24xx05 prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F4480] pgmmem=0x0 ~pgmmem=0x3FFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0xff devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x1AA0 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xC,0xC,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xE,0xA,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xF,0x5,EC-Port on RA6 CONFIG1H~1~8=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xF,0x3,0011 EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xF,0x2,HS CONFIG1H~1~11=0xF,0x1,XT CONFIG1H~1~12=0xF,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x08,4.2V CONFIG2L~3~4=0x18,0x00,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=PBADEN,0x2,PortB A/D Enable CONFIG3H~2=LPT1OSC,0x04,Low Power Timer1 Osc enable CONFIG3H~3=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x2,0x2,PORTB<4:0> configured as analog inputs on RESET CONFIG3H~1~2=0x2,0x0,PORTB<4:0> configured as digital I/O on RESET CONFIG3H~2~1=0x04,0x04,Enabled CONFIG3H~2~2=0x04,0x00,Disabled CONFIG3H~3~1=0x80,0x80,MCLR Enabled,RE3 Disabled CONFIG3H~3~2=0x80,0x00,MCLR Disabled, RE3 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=BBSIZ,0x10,Boot Block Size Select CONFIG4L~4=ENHCPU,0x40,Extended CPU Enable CONFIG4L~5=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x10,0x10,2 KW CONFIG4L~3~2=0x10,0x00,1 KW CONFIG4L~4~1=0x40,0x40,Enabled CONFIG4L~4~2=0x40,0x00,Disabled CONFIG4L~5~1=0x80,0x80,Disabled CONFIG4L~5~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-01FFF CONFIG5L~2=CP_1,0x2,Code Protect 02000-03FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EE Read Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-01FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 02000-03FFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EE Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-01FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 02000-03FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F4523] pgmmem=0x0 ~pgmmem=0x7FFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0xff devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFF0 id=0x1090 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xC,0xC,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xE,0xA,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xF,0x5,EC-Port on RA6 CONFIG1H~1~8=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xF,0x3,0011 EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xF,0x2,HS CONFIG1H~1~11=0xF,0x1,XT CONFIG1H~1~12=0xF,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x08,4.2V CONFIG2L~3~4=0x18,0x00,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=PBADEN,0x2,PortB A/D Enable CONFIG3H~3=LPT1OSC,0x04,Low Power Timer1 Osc enable CONFIG3H~4=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RB3 CONFIG3H~2~1=0x2,0x2,PORTB<4:0> configured as analog inputs on RESET CONFIG3H~2~2=0x2,0x0,PORTB<4:0> configured as digital I/O on RESET CONFIG3H~3~1=0x04,0x04,Enabled CONFIG3H~3~2=0x04,0x00,Disabled CONFIG3H~4~1=0x80,0x80,MCLR Enabled,RE3 Disabled CONFIG3H~4~2=0x80,0x00,MCLR Disabled,RE3 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=ENHCPU,0x40,Extended CPU Enable CONFIG4L~4=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x40,0x40,Enabled CONFIG4L~3~2=0x40,0x00,Disabled CONFIG4L~4~1=0x80,0x80,Disabled CONFIG4L~4~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-01FFF CONFIG5L~2=CP_1,0x2,Code Protect 02000-03FFF CONFIG5L~3=CP_2,0x4,Code Protect 04000-05FFF CONFIG5L~4=CP_3,0x8,Code Protect 06000-07FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EEPROM Code Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-01FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 02000-03FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 04000-05FFF CONFIG6L~4=WRT_3,0x8,Table Write Protect 06000-07FFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x00,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EEPROM Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-01FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 02000-03FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 04000-05FFF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 06000-07FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x00,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F4580] pgmmem=0x0 ~pgmmem=0x7FFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0xff devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x1A80 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xC,0xC,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xE,0xA,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xF,0x5,EC-Port on RA6 CONFIG1H~1~8=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xF,0x3,0011 EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xF,0x2,HS CONFIG1H~1~11=0xF,0x1,XT CONFIG1H~1~12=0xF,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x08,4.2V CONFIG2L~3~4=0x18,0x00,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=PBADEN,0x2,PortB A/D Enable CONFIG3H~2=LPT1OSC,0x04,Low Power Timer1 Osc enable CONFIG3H~3=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x2,0x2,PORTB<4:0> configured as analog inputs on RESET CONFIG3H~1~2=0x2,0x0,PORTB<4:0> configured as digital I/O on RESET CONFIG3H~2~1=0x04,0x04,Enabled CONFIG3H~2~2=0x04,0x00,Disabled CONFIG3H~3~1=0x80,0x80,MCLR Enabled,RE3 Disabled CONFIG3H~3~2=0x80,0x00,MCLR Disabled, RE3 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=BBSIZ,0x10,Boot Block Size Select CONFIG4L~4=ENHCPU,0x40,Extended CPU Enable CONFIG4L~5=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x10,0x10,2 KW CONFIG4L~3~2=0x10,0x00,1 KW CONFIG4L~4~1=0x40,0x40,Enabled CONFIG4L~4~2=0x40,0x00,Disabled CONFIG4L~5~1=0x80,0x80,Disabled CONFIG4L~5~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-01FFF CONFIG5L~2=CP_1,0x2,Code Protect 02000-03FFF CONFIG5L~3=CP_2,0x4,Code Protect 04000-05FFF CONFIG5L~4=CP_3,0x8,Code Protect 06000-07FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EE Read Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-01FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 02000-03FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 04000-05FFF CONFIG6L~4=WRT_3,0x8,Table Write Protect 06000-07FFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x00,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EE Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-01FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 02000-03FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 04000-05FFF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 06000-07FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x00,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE_24xx05 prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F4682] pgmmem=0x0 ~pgmmem=0x13FFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0x3ff devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x2740 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xC,0xC,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xE,0xA,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xF,0x5,EC-Port on RA6 CONFIG1H~1~8=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xF,0x3,0011 EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xF,0x2,HS CONFIG1H~1~11=0xF,0x1,XT CONFIG1H~1~12=0xF,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x08,4.2V CONFIG2L~3~4=0x18,0x00,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=PBADEN,0x2,PortB A/D Enable CONFIG3H~2=LPT1OSC,0x04,Low Power Timer1 Osc enable CONFIG3H~3=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x2,0x2,PORTB<4> and <1:0> configured as analog inputs on RESET CONFIG3H~1~2=0x2,0x0,PORTB<4> and <1:0> configured as digital I/O on RESET CONFIG3H~2~1=0x04,0x04,Enabled CONFIG3H~2~2=0x04,0x00,Disabled CONFIG3H~3~1=0x80,0x80,MCLR Enabled,RE3 Disabled CONFIG3H~3~2=0x80,0x00,MCLR Disabled, RE3 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=BBSIZ,0x30,Boot Block Size CONFIG4L~4=ENHCPU,0x40,Extended CPU Enable CONFIG4L~5=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x20,0x20,4K Words (8 Kbytes) CONFIG4L~3~2=0x30,0x10,2K Words (4 Kbytes) CONFIG4L~3~3=0x30,0x00,1K Words (2 Kbytes) CONFIG4L~4~1=0x40,0x40,Enabled CONFIG4L~4~2=0x40,0x00,Disabled CONFIG4L~5~1=0x80,0x80,Disabled CONFIG4L~5~2=0x80,0x0,Enabled CONFIG5L_unused=0x20 CONFIG5L~1=CP_0,0x1,Code Protect 00800-03FFF CONFIG5L~2=CP_1,0x2,Code Protect 04000-07FFF CONFIG5L~3=CP_2,0x4,Code Protect 08000-0BFFF CONFIG5L~4=CP_3,0x8,Code Protect 0C000-0FFFF CONFIG5L~5=CP_4,0x10,Code Protect 10000-13FFF CONFIG5L~6=CP_5,0x20,Code Protect 14000-17FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5L~5~1=0x10,0x10,Disabled CONFIG5L~5~2=0x10,0x00,Enabled CONFIG5L~6~1=0x20,0x20,Disabled CONFIG5L~6~2=0x20,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EE Read Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x20 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-03FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 04000-07FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 08000-0BFFF CONFIG6L~4=WRT_3,0x8,Table Write Protect 0C000-0FFFF CONFIG6L~5=WRT_4,0x10,Table Write Protect 10000-13FFF CONFIG6L~6=WRT_5,0x20,Table Write Protect 14000-17FFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x00,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x00,Enabled CONFIG6L~5~1=0x10,0x10,Disabled CONFIG6L~5~2=0x10,0x00,Enabled CONFIG6L~6~1=0x20,0x20,Disabled CONFIG6L~6~2=0x20,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EE Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x20 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-03FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 04000-07FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 08000-0BFFF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 0C000-0FFFF CONFIG7L~5=EBTR_4,0x10,Table Read Protect 10000-13FFF CONFIG7L~6=EBTR_5,0x20,Table Read Protect 14000-17FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x00,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x00,Enabled CONFIG7L~5~1=0x10,0x10,Disabled CONFIG7L~5~2=0x10,0x00,Enabled CONFIG7L~6~1=0x20,0x20,Disabled CONFIG7L~6~2=0x20,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE_24xx05 prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F4685] pgmmem=0x0 ~pgmmem=0x17FFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0x3ff devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x2760 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xC,0xC,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xE,0xA,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xF,0x5,EC-Port on RA6 CONFIG1H~1~8=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xF,0x3,0011 EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xF,0x2,HS CONFIG1H~1~11=0xF,0x1,XT CONFIG1H~1~12=0xF,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x08,4.2V CONFIG2L~3~4=0x18,0x00,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=PBADEN,0x2,PortB A/D Enable CONFIG3H~2=LPT1OSC,0x04,Low Power Timer1 Osc enable CONFIG3H~3=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x2,0x2,PORTB<4> and <1:0> configured as analog inputs on RESET CONFIG3H~1~2=0x2,0x0,PORTB<4> and <1:0> configured as digital I/O on RESET CONFIG3H~2~1=0x04,0x04,Enabled CONFIG3H~2~2=0x04,0x00,Disabled CONFIG3H~3~1=0x80,0x80,MCLR Enabled,RE3 Disabled CONFIG3H~3~2=0x80,0x00,MCLR Disabled, RE3 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=BBSIZ,0x30,Boot Block Size CONFIG4L~4=ENHCPU,0x40,Extended CPU Enable CONFIG4L~5=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x20,0x20,4K Words (8 Kbytes) CONFIG4L~3~2=0x30,0x10,2K Words (4 Kbytes) CONFIG4L~3~3=0x30,0x00,1K Words (2 Kbytes) CONFIG4L~4~1=0x40,0x40,Enabled CONFIG4L~4~2=0x40,0x00,Disabled CONFIG4L~5~1=0x80,0x80,Disabled CONFIG4L~5~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-03FFF CONFIG5L~2=CP_1,0x2,Code Protect 04000-07FFF CONFIG5L~3=CP_2,0x4,Code Protect 08000-0BFFF CONFIG5L~4=CP_3,0x8,Code Protect 0C000-0FFFF CONFIG5L~5=CP_4,0x10,Code Protect 10000-13FFF CONFIG5L~6=CP_5,0x20,Code Protect 14000-17FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5L~5~1=0x10,0x10,Disabled CONFIG5L~5~2=0x10,0x00,Enabled CONFIG5L~6~1=0x20,0x20,Disabled CONFIG5L~6~2=0x20,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EE Read Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-03FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 04000-07FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 08000-0BFFF CONFIG6L~4=WRT_3,0x8,Table Write Protect 0C000-0FFFF CONFIG6L~5=WRT_4,0x10,Table Write Protect 10000-13FFF CONFIG6L~6=WRT_5,0x20,Table Write Protect 14000-17FFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x00,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x00,Enabled CONFIG6L~5~1=0x10,0x10,Disabled CONFIG6L~5~2=0x10,0x00,Enabled CONFIG6L~6~1=0x20,0x20,Disabled CONFIG6L~6~2=0x20,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EE Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-03FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 04000-07FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 08000-0BFFF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 0C000-0FFFF CONFIG7L~5=EBTR_4,0x10,Table Read Protect 10000-13FFF CONFIG7L~6=EBTR_5,0x20,Table Read Protect 14000-17FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x00,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x00,Enabled CONFIG7L~5~1=0x10,0x10,Disabled CONFIG7L~5~2=0x10,0x00,Enabled CONFIG7L~6~1=0x20,0x20,Disabled CONFIG7L~6~2=0x20,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE_24xx05 prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F6527] pgmmem=0x0 ~pgmmem=0xBFFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0x3ff devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x1340 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004=CONFIG3L 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xC,0xC,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xE,0xA,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xF,0x5,EC-Port on RA6 CONFIG1H~1~8=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xF,0x3,0011 EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xF,0x2,HS CONFIG1H~1~11=0xF,0x1,XT CONFIG1H~1~12=0xF,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x08,4.2V CONFIG2L~3~4=0x18,0x00,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3L_unused=0x0 CONFIG3L~1=PMODE,0x3,Processor Mode CONFIG3L~1~1=0x3,0x3,Microcontroller CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=LPT1OSC,0x04,Low Power Timer1 Osc enable CONFIG3H~3=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,CCP2 muxed with RC1 CONFIG3H~1~2=0x1,0x0,CCP2 muxed with RE7 CONFIG3H~2~1=0x04,0x04,Enabled CONFIG3H~2~2=0x04,0x00,Disabled CONFIG3H~3~1=0x80,0x80,MCLR Enabled,RG5 Disabled CONFIG3H~3~2=0x80,0x00,MCLR Disabled, RG5 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=BBSIZ,0x30,Boot Block Size CONFIG4L~4=ENHCPU,0x40,Extended CPU Enable CONFIG4L~5=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x20,0x20,4K Words (8 Kbytes) CONFIG4L~3~2=0x30,0x10,2K Words (4 Kbytes) CONFIG4L~3~3=0x30,0x00,1K Words (2 Kbytes) CONFIG4L~4~1=0x40,0x40,Enabled CONFIG4L~4~2=0x40,0x00,Disabled CONFIG4L~5~1=0x80,0x80,Disabled CONFIG4L~5~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-03FFF CONFIG5L~2=CP_1,0x2,Code Protect 04000-07FFF CONFIG5L~3=CP_2,0x4,Code Protect 08000-0BFFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EE Read Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-03FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 04000-07FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 08000-0BFFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EE Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-03FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 04000-07FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 08000-0BFFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE_24xx05 prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F6622] pgmmem=0x0 ~pgmmem=0xFFFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0x3ff devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x1380 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004=CONFIG3L 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xC,0xC,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xE,0xA,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xF,0x5,EC-Port on RA6 CONFIG1H~1~8=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xF,0x3,0011 EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xF,0x2,HS CONFIG1H~1~11=0xF,0x1,XT CONFIG1H~1~12=0xF,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x08,4.2V CONFIG2L~3~4=0x18,0x00,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3L_unused=0x0 CONFIG3L~1=PMODE,0x3,Processor Mode CONFIG3L~1~1=0x3,0x3,Microcontroller CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=LPT1OSC,0x04,Low Power Timer1 Osc enable CONFIG3H~3=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,CCP2 muxed with RC1 CONFIG3H~1~2=0x1,0x0,CCP2 muxed with RE7 CONFIG3H~2~1=0x04,0x04,Enabled CONFIG3H~2~2=0x04,0x00,Disabled CONFIG3H~3~1=0x80,0x80,MCLR Enabled,RG5 Disabled CONFIG3H~3~2=0x80,0x00,MCLR Disabled, RG5 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=BBSIZ,0x30,Boot Block Size CONFIG4L~4=ENHCPU,0x40,Extended CPU Enable CONFIG4L~5=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x20,0x20,4K Words (8 Kbytes) CONFIG4L~3~2=0x30,0x10,2K Words (4 Kbytes) CONFIG4L~3~3=0x30,0x00,1K Words (2 Kbytes) CONFIG4L~4~1=0x40,0x40,Enabled CONFIG4L~4~2=0x40,0x00,Disabled CONFIG4L~5~1=0x80,0x80,Disabled CONFIG4L~5~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-03FFF CONFIG5L~2=CP_1,0x2,Code Protect 04000-07FFF CONFIG5L~3=CP_2,0x4,Code Protect 08000-0BFFF CONFIG5L~4=CP_3,0x8,Code Protect 0C000-0FFFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EE Read Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-03FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 04000-07FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 08000-0BFFF CONFIG6L~4=WRT_3,0x8,Table Write Protect 0C000-0FFFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x00,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EE Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-03FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 04000-07FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 08000-0BFFF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 0C000-0FFFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x00,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F6627] pgmmem=0x0 ~pgmmem=0x17FFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0x3ff devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x13C0 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004=CONFIG3L 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xC,0xC,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xE,0xA,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xF,0x5,EC-Port on RA6 CONFIG1H~1~8=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xF,0x3,0011 EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xF,0x2,HS CONFIG1H~1~11=0xF,0x1,XT CONFIG1H~1~12=0xF,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x08,4.2V CONFIG2L~3~4=0x18,0x00,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3L_unused=0x0 CONFIG3L~1=PMODE,0x3,Processor Mode CONFIG3L~1~1=0x3,0x3,Microcontroller CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=LPT1OSC,0x04,Low Power Timer1 Osc enable CONFIG3H~3=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,CCP2 muxed with RC1 CONFIG3H~1~2=0x1,0x0,CCP2 muxed with RE7 CONFIG3H~2~1=0x04,0x04,Enabled CONFIG3H~2~2=0x04,0x00,Disabled CONFIG3H~3~1=0x80,0x80,MCLR Enabled,RG5 Disabled CONFIG3H~3~2=0x80,0x00,MCLR Disabled, RG5 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=BBSIZ,0x30,Boot Block Size CONFIG4L~4=ENHCPU,0x40,Extended CPU Enable CONFIG4L~5=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x20,0x20,4K Words (8 Kbytes) CONFIG4L~3~2=0x30,0x10,2K Words (4 Kbytes) CONFIG4L~3~3=0x30,0x00,1K Words (2 Kbytes) CONFIG4L~4~1=0x40,0x40,Enabled CONFIG4L~4~2=0x40,0x00,Disabled CONFIG4L~5~1=0x80,0x80,Disabled CONFIG4L~5~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-03FFF CONFIG5L~2=CP_1,0x2,Code Protect 04000-07FFF CONFIG5L~3=CP_2,0x4,Code Protect 08000-0BFFF CONFIG5L~4=CP_3,0x8,Code Protect 0C000-0FFFF CONFIG5L~5=CP_4,0x10,Code Protect 10000-13FFF CONFIG5L~6=CP_5,0x20,Code Protect 14000-17FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5L~5~1=0x10,0x10,Disabled CONFIG5L~5~2=0x10,0x00,Enabled CONFIG5L~6~1=0x20,0x20,Disabled CONFIG5L~6~2=0x20,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EE Read Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-03FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 04000-07FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 08000-0BFFF CONFIG6L~4=WRT_3,0x8,Table Write Protect 0C000-0FFFF CONFIG6L~5=WRT_4,0x10,Table Write Protect 10000-13FFF CONFIG6L~6=WRT_5,0x20,Table Write Protect 14000-17FFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x00,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x00,Enabled CONFIG6L~5~1=0x10,0x10,Disabled CONFIG6L~5~2=0x10,0x00,Enabled CONFIG6L~6~1=0x20,0x20,Disabled CONFIG6L~6~2=0x20,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EE Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-03FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 04000-07FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 08000-0BFFF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 0C000-0FFFF CONFIG7L~5=EBTR_4,0x10,Table Read Protect 10000-13FFF CONFIG7L~6=EBTR_5,0x20,Table Read Protect 14000-17FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x00,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x00,Enabled CONFIG7L~5~1=0x10,0x10,Disabled CONFIG7L~5~2=0x10,0x00,Enabled CONFIG7L~6~1=0x20,0x20,Disabled CONFIG7L~6~2=0x20,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F6722] pgmmem=0x0 ~pgmmem=0x1FFFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0x3ff devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x1400 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004=CONFIG3L 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xC,0xC,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xE,0xA,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xF,0x5,EC-Port on RA6 CONFIG1H~1~8=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xF,0x3,0011 EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xF,0x2,HS CONFIG1H~1~11=0xF,0x1,XT CONFIG1H~1~12=0xF,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x08,4.2V CONFIG2L~3~4=0x18,0x00,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3L_unused=0x0 CONFIG3L~1=PMODE,0x3,Processor Mode CONFIG3L~1~1=0x3,0x3,Microcontroller CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=LPT1OSC,0x04,Low Power Timer1 Osc enable CONFIG3H~3=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,CCP2 muxed with RC1 CONFIG3H~1~2=0x1,0x0,CCP2 muxed with RE7 CONFIG3H~2~1=0x04,0x04,Enabled CONFIG3H~2~2=0x04,0x00,Disabled CONFIG3H~3~1=0x80,0x80,MCLR Enabled,RG5 Disabled CONFIG3H~3~2=0x80,0x00,MCLR Disabled, RG5 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=BBSIZ,0x30,Boot Block Size CONFIG4L~4=ENHCPU,0x40,Extended CPU Enable CONFIG4L~5=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x20,0x20,4K Words (8 Kbytes) CONFIG4L~3~2=0x30,0x10,2K Words (4 Kbytes) CONFIG4L~3~3=0x30,0x00,1K Words (2 Kbytes) CONFIG4L~4~1=0x40,0x40,Enabled CONFIG4L~4~2=0x40,0x00,Disabled CONFIG4L~5~1=0x80,0x80,Disabled CONFIG4L~5~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-03FFF CONFIG5L~2=CP_1,0x2,Code Protect 04000-07FFF CONFIG5L~3=CP_2,0x4,Code Protect 08000-0BFFF CONFIG5L~4=CP_3,0x8,Code Protect 0C000-0FFFF CONFIG5L~5=CP_4,0x10,Code Protect 10000-13FFF CONFIG5L~6=CP_5,0x20,Code Protect 14000-17FFF CONFIG5L~7=CP_6,0x40,Code Protect 18000-1BFFF CONFIG5L~8=CP_7,0x80,Code Protect 1C000-1FFFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5L~5~1=0x10,0x10,Disabled CONFIG5L~5~2=0x10,0x00,Enabled CONFIG5L~6~1=0x20,0x20,Disabled CONFIG5L~6~2=0x20,0x00,Enabled CONFIG5L~7~1=0x40,0x40,Disabled CONFIG5L~7~2=0x40,0x00,Enabled CONFIG5L~8~1=0x80,0x80,Disabled CONFIG5L~8~2=0x80,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EE Read Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-03FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 04000-07FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 08000-0BFFF CONFIG6L~4=WRT_3,0x8,Table Write Protect 0C000-0FFFF CONFIG6L~5=WRT_4,0x10,Table Write Protect 10000-13FFF CONFIG6L~6=WRT_5,0x20,Table Write Protect 14000-17FFF CONFIG6L~7=WRT_6,0x40,Table Write Protect 18000-1BFFF CONFIG6L~8=WRT_7,0x80,Table Write Protect 1C000-1FFFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x00,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x00,Enabled CONFIG6L~5~1=0x10,0x10,Disabled CONFIG6L~5~2=0x10,0x00,Enabled CONFIG6L~6~1=0x20,0x20,Disabled CONFIG6L~6~2=0x20,0x00,Enabled CONFIG6L~7~1=0x40,0x40,Disabled CONFIG6L~7~2=0x40,0x00,Enabled CONFIG6L~8~1=0x80,0x80,Disabled CONFIG6L~8~2=0x80,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EE Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-03FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 04000-07FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 08000-0BFFF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 0C000-0FFFF CONFIG7L~5=EBTR_4,0x10,Table Read Protect 10000-13FFF CONFIG7L~6=EBTR_5,0x20,Table Read Protect 14000-17FFF CONFIG7L~7=EBTR_6,0x40,Table Read Protect 18000-1BFFF CONFIG7L~8=EBTR_7,0x80,Table Read Protect 1C000-1FFFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x00,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x00,Enabled CONFIG7L~5~1=0x10,0x10,Disabled CONFIG7L~5~2=0x10,0x00,Enabled CONFIG7L~6~1=0x20,0x20,Disabled CONFIG7L~6~2=0x20,0x00,Enabled CONFIG7L~7~1=0x40,0x40,Disabled CONFIG7L~7~2=0x40,0x00,Enabled CONFIG7L~8~1=0x80,0x80,Disabled CONFIG7L~8~2=0x80,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F8527] pgmmem=0x0 ~pgmmem=0xBFFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0x3ff devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x1360 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004=CONFIG3L 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xC,0xC,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xE,0xA,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xF,0x5,EC-Port on RA6 CONFIG1H~1~8=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xF,0x3,0011 EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xF,0x2,HS CONFIG1H~1~11=0xF,0x1,XT CONFIG1H~1~12=0xF,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x08,4.2V CONFIG2L~3~4=0x18,0x00,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3L_unused=0x0 CONFIG3L~1=PMODE,0x3,Processor Mode CONFIG3L~2=ABW,0x30,Address Bus Width CONFIG3L~3=BW,0x40,Bus Width CONFIG3L~4=WAIT,0x80,External Bus Wait CONFIG3L~1~1=0x3,0x3,Microcontroller CONFIG3L~1~2=0x3,0x2,Microprocessor CONFIG3L~1~3=0x3,0x1,Microprocessor w/Boot CONFIG3L~1~4=0x3,0x0,Ext Microcontroller CONFIG3L~2~1=0x30,0x30,20-bit CONFIG3L~2~2=0x30,0x20,16-bit CONFIG3L~2~3=0x30,0x10,12-bit CONFIG3L~2~4=0x30,0x00,8-bit CONFIG3L~3~1=0x40,0x40,16-bit external bus CONFIG3L~3~2=0x40,0x00,8-bit external bus CONFIG3L~4~1=0x80,0x80,Disabled CONFIG3L~4~2=0x80,0x0,Enabled CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=ECCPMX,0x2,ECCP Mux CONFIG3H~3=LPT1OSC,0x04,Low Power Timer1 Osc enable CONFIG3H~4=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RE7-Microcontroller Mode/RB3-All other modes CONFIG3H~2~1=0x2,0x2,ECCP1/3 [1B/1C/3B/3C] muxed with RE6-RE3 CONFIG3H~2~2=0x2,0x0,ECCP1/3 [1B/1C/3B/3C] muxed with RH7-RH4 CONFIG3H~3~1=0x04,0x04,Enabled CONFIG3H~3~2=0x04,0x00,Disabled CONFIG3H~4~1=0x80,0x80,MCLR Enabled, RG5 Disabled CONFIG3H~4~2=0x80,0x00,MCLR Disabled, RG5 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=BBSIZ,0x30,Boot Block Size CONFIG4L~4=ENHCPU,0x40,Extended CPU Enable CONFIG4L~5=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x20,0x20,4K Words (8 Kbytes) CONFIG4L~3~2=0x30,0x10,2K Words (4 Kbytes) CONFIG4L~3~3=0x30,0x00,1K Words (2 Kbytes) CONFIG4L~4~1=0x40,0x40,Enabled CONFIG4L~4~2=0x40,0x00,Disabled CONFIG4L~5~1=0x80,0x80,Disabled CONFIG4L~5~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-03FFF CONFIG5L~2=CP_1,0x2,Code Protect 04000-07FFF CONFIG5L~3=CP_2,0x4,Code Protect 08000-0BFFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EE Read Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-03FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 04000-07FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 08000-0BFFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EE Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-03FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 04000-07FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 08000-0BFFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F8622] pgmmem=0x0 ~pgmmem=0xffff cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0x3ff devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x0A80 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004=CONFIG3L 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B= 0x30000C=CONFIG7L 0x30000D= CONFIG1H_unused=0x00 CONFIG1H~1=FOSC,0x0f,Oscillator CONFIG1H~2=FCMEN,0x40,Fail Safe Monitor Clock Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Enable CONFIG1H~1~1=0x0c,0x0c,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0x0e,0x0a,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0x0f,0x09,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0x0f,0x08,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0x0f,0x07,EXT RC-Port on RA6 CONFIG1H~1~6=0x0f,0x06,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0x0f,0x05,EC-Port on RA6 CONFIG1H~1~8=0x0f,0x04,EC-CLKOUT on RA6 CONFIG1H~1~9=0x0f,0x03,0011 EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0x0f,0x02,HS CONFIG1H~1~11=0x0f,0x01,XT CONFIG1H~1~12=0x0f,0x00,LP CONFIG1H~2~1=0x40,0x40,Enabled CONFIG1H~2~2=0x40,0x00,Disabled CONFIG1H~3~1=0x80,0x80,Enabled CONFIG1H~3~2=0x80,0x00,Disabled CONFIG2L_unused=0x00 CONFIG2L~1=PWRTEN,0x01,Power-up Timer Enable CONFIG2L~2=BODEN,0x06,Brown-out Reset Enable CONFIG2L~3=BORV,0x18,Brown-out Reset Voltage CONFIG2L~1~1=0x01,0x01,Disabled CONFIG2L~1~2=0x01,0x00,Enabled CONFIG2L~2~1=0x06,0x06,Brown-out Reset Enabled, SBOREN Disabled CONFIG2L~2~2=0x06,0x04,Brown-out Reset Enabled When Not in SLEEP, SBOREN Disabled CONFIG2L~2~3=0x06,0x02,Brown-out Controlled by SBOREN CONFIG2L~2~4=0x06,0x00,Brown-out Disabled, SBOREN Disabled CONFIG2L~3~1=0x18,0x18,2.0 V CONFIG2L~3~2=0x18,0x10,2.7 V CONFIG2L~3~3=0x18,0x08,4.2 V CONFIG2L~3~4=0x18,0x00,4.5 V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3L_unused=0x00 CONFIG3L~1=PM,0x03,Processor Data Memory Mode Select CONFIG3L~2=ABW,0x30,Address Bus Width Select CONFIG3L~3=BW,0x40,Data Bus Width Select CONFIG3L~4=WAIT,0x80,External Bus Wait Enable CONFIG3L~1~1=0x03,0x03,Microcontroller Mode CONFIG3L~1~2=0x03,0x02,Microprocessor Mode CONFIG3L~1~3=0x03,0x01,Microprocessor With Boot Block Mode CONFIG3L~1~4=0x03,0x00,Extended Microcontroller Mode CONFIG3L~2~1=0x30,0x30,20-bit CONFIG3L~2~2=0x30,0x20,16-bit CONFIG3L~2~3=0x30,0x10,12-bit CONFIG3L~2~4=0x30,0x00,8-bit CONFIG3L~3~1=0x40,0x40,16-bit CONFIG3L~3~2=0x40,0x00,8-bit CONFIG3L~4~1=0x80,0x80,MEMCON.WAIT Ignored, Device Will Not Wait CONFIG3L~4~2=0x80,0x00,Wait Programmed by MEMCON.WAIT CONFIG3H_unused=0x00 CONFIG3H~1=CCP2MX,0x01,CCP2 Mux CONFIG3H~2=ECCPMX,0x02,ECCP Mux CONFIG3H~3=LPT1OSC,0x04,Low-Power Timer1 Oscillator Enable CONFIG3H~4=MCLRE,0x80,MCLR Pin Enable CONFIG3H~1~1=0x01,0x01,ECCP2 I/O Muxed With RC1 CONFIG3H~1~2=0x01,0x00,ECCP2 I/O Muxed With RB3 or RE7 CONFIG3H~2~1=0x2,0x02,ECCP1/3 [1B/1C/3B/3C] muxed with RE6-RE3 CONFIG3H~2~2=0x2,0x00,ECCP1/3 [1B/1C/3B/3C] muxed with RH7-RH4 CONFIG3H~3~1=0x04,0x04,Low Power Consumption, Low Noise Immunity CONFIG3H~3~2=0x04,0x00,High Power Consumption, High Noise Immunity CONFIG3H~4~1=0x80,0x80,MCLR Enabled, RG5 Input Pin Disabled CONFIG3H~4~2=0x80,0x00,MCLR Disabled, RG5 Input Pin Enabled CONFIG4L_unused=0x00 CONFIG4L~1=STVREN,0x01,Stack Overflow Reset Enable CONFIG4L~2=LVP,0x04,Low Voltage Programming Enable CONFIG4L~3=BBSIZ,0x30,Boot Block Size CONFIG4L~4=ENHCPU,0x40,Enhanced CPU Enable CONFIG4L~5=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x01,0x01,Enabled CONFIG4L~1~2=0x01,0x00,Disabled CONFIG4L~2~1=0x04,0x04,Enabled CONFIG4L~2~2=0x04,0x00,Disabled CONFIG4L~3~1=0x20,0x20,4K Words (8 Kbytes) CONFIG4L~3~2=0x30,0x10,2K Words (4 Kbytes) CONFIG4L~3~3=0x30,0x00,1K Words (2 Kbytes) CONFIG4L~4~1=0x40,0x40,Enabled CONFIG4L~4~2=0x40,0x00,Disabled CONFIG4L~5~1=0x80,0x80,Disabled CONFIG4L~5~2=0x80,0x00,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-03FFF CONFIG5L~2=CP_1,0x2,Code Protect 04000-07FFF CONFIG5L~3=CP_2,0x4,Code Protect 08000-0BFFF CONFIG5L~4=CP_3,0x8,Code Protect 0C000-0FFFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EE Read Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-03FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 04000-07FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 08000-0BFFF CONFIG6L~4=WRT_3,0x8,Table Write Protect 0C000-0FFFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x00,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x00,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-03FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 04000-07FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 08000-0BFFF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 0C000-0FFFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x00,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x00,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F8627] pgmmem=0x0 ~pgmmem=0x17FFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0x3ff devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x13E0 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004=CONFIG3L 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xC,0xC,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xE,0xA,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xF,0x5,EC-Port on RA6 CONFIG1H~1~8=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xF,0x3,0011 EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xF,0x2,HS CONFIG1H~1~11=0xF,0x1,XT CONFIG1H~1~12=0xF,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x08,4.2V CONFIG2L~3~4=0x18,0x00,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3L_unused=0x0 CONFIG3L~1=PMODE,0x3,Processor Mode CONFIG3L~2=ABW,0x30,Address Bus Width CONFIG3L~3=BW,0x40,Bus Width CONFIG3L~4=WAIT,0x80,External Bus Wait CONFIG3L~1~1=0x3,0x3,Microcontroller CONFIG3L~1~2=0x3,0x2,Microprocessor CONFIG3L~1~3=0x3,0x1,Microprocessor w/Boot CONFIG3L~1~4=0x3,0x0,Ext Microcontroller CONFIG3L~2~1=0x30,0x30,20-bit CONFIG3L~2~2=0x30,0x20,16-bit CONFIG3L~2~3=0x30,0x10,12-bit CONFIG3L~2~4=0x30,0x00,8-bit CONFIG3L~3~1=0x40,0x40,16-bit external bus CONFIG3L~3~2=0x40,0x00,8-bit external bus CONFIG3L~4~1=0x80,0x80,Disabled CONFIG3L~4~2=0x80,0x0,Enabled CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=ECCPMX,0x2,ECCP Mux CONFIG3H~3=LPT1OSC,0x04,Low Power Timer1 Osc enable CONFIG3H~4=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RE7-Microcontroller Mode/RB3-All other modes CONFIG3H~2~1=0x2,0x2,ECCP1/3 [1B/1C/3B/3C] muxed with RE6-RE3 CONFIG3H~2~2=0x2,0x0,ECCP1/3 [1B/1C/3B/3C] muxed with RH7-RH4 CONFIG3H~3~1=0x04,0x04,Enabled CONFIG3H~3~2=0x04,0x00,Disabled CONFIG3H~4~1=0x80,0x80,MCLR Enabled, RG5 Disabled CONFIG3H~4~2=0x80,0x00,MCLR Disabled, RG5 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=BBSIZ,0x30,Boot Block Size CONFIG4L~4=ENHCPU,0x40,Extended CPU Enable CONFIG4L~5=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x20,0x20,4K Words (8 Kbytes) CONFIG4L~3~2=0x30,0x10,2K Words (4 Kbytes) CONFIG4L~3~3=0x30,0x00,1K Words (2 Kbytes) CONFIG4L~4~1=0x40,0x40,Enabled CONFIG4L~4~2=0x40,0x00,Disabled CONFIG4L~5~1=0x80,0x80,Disabled CONFIG4L~5~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-03FFF CONFIG5L~2=CP_1,0x2,Code Protect 04000-07FFF CONFIG5L~3=CP_2,0x4,Code Protect 08000-0BFFF CONFIG5L~4=CP_3,0x8,Code Protect 0C000-0FFFF CONFIG5L~5=CP_4,0x10,Code Protect 10000-13FFF CONFIG5L~6=CP_5,0x20,Code Protect 14000-17FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5L~5~1=0x10,0x10,Disabled CONFIG5L~5~2=0x10,0x00,Enabled CONFIG5L~6~1=0x20,0x20,Disabled CONFIG5L~6~2=0x20,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EE Read Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-03FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 04000-07FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 08000-0BFFF CONFIG6L~4=WRT_3,0x8,Table Write Protect 0C000-0FFFF CONFIG6L~5=WRT_4,0x10,Table Write Protect 10000-13FFF CONFIG6L~6=WRT_5,0x20,Table Write Protect 14000-17FFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x00,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x00,Enabled CONFIG6L~5~1=0x10,0x10,Disabled CONFIG6L~5~2=0x10,0x00,Enabled CONFIG6L~6~1=0x20,0x20,Disabled CONFIG6L~6~2=0x20,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EE Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-03FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 04000-07FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 08000-0BFFF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 0C000-0FFFF CONFIG7L~5=EBTR_4,0x10,Table Read Protect 10000-13FFF CONFIG7L~6=EBTR_5,0x20,Table Read Protect 14000-17FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x00,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x00,Enabled CONFIG7L~5~1=0x10,0x10,Disabled CONFIG7L~5~2=0x10,0x00,Enabled CONFIG7L~6~1=0x20,0x20,Disabled CONFIG7L~6~2=0x20,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F8722] pgmmem=0x0 ~pgmmem=0x1FFFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0x3ff devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x1420 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004=CONFIG3L 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000A=CONFIG6L 0x30000B=CONFIG6H 0x30000C=CONFIG7L 0x30000D=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xC,0xC,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xE,0xA,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xF,0x5,EC-Port on RA6 CONFIG1H~1~8=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xF,0x3,0011 EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xF,0x2,HS CONFIG1H~1~11=0xF,0x1,XT CONFIG1H~1~12=0xF,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x08,4.2V CONFIG2L~3~4=0x18,0x00,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3L_unused=0x0 CONFIG3L~1=PMODE,0x3,Processor Mode CONFIG3L~2=ABW,0x30,Address Bus Width CONFIG3L~3=BW,0x40,Bus Width CONFIG3L~4=WAIT,0x80,External Bus Wait CONFIG3L~1~1=0x3,0x3,Microcontroller CONFIG3L~1~2=0x3,0x2,Microprocessor CONFIG3L~1~3=0x3,0x1,Microprocessor w/Boot CONFIG3L~1~4=0x3,0x0,Ext Microcontroller CONFIG3L~2~1=0x30,0x30,20-bit CONFIG3L~2~2=0x30,0x20,16-bit CONFIG3L~2~3=0x30,0x10,12-bit CONFIG3L~2~4=0x30,0x00,8-bit CONFIG3L~3~1=0x40,0x40,16-bit external bus CONFIG3L~3~2=0x40,0x00,8-bit external bus CONFIG3L~4~1=0x80,0x80,Disabled CONFIG3L~4~2=0x80,0x0,Enabled CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=ECCPMX,0x2,ECCP Mux CONFIG3H~3=LPT1OSC,0x04,Low Power Timer1 Osc enable CONFIG3H~4=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RE7-Microcontroller Mode/RB3-All other modes CONFIG3H~2~1=0x2,0x2,ECCP1/3 [1B/1C/3B/3C] muxed with RE6-RE3 CONFIG3H~2~2=0x2,0x0,ECCP1/3 [1B/1C/3B/3C] muxed with RH7-RH4 CONFIG3H~3~1=0x04,0x04,Enabled CONFIG3H~3~2=0x04,0x00,Disabled CONFIG3H~4~1=0x80,0x80,MCLR Enabled,RG5 Disabled CONFIG3H~4~2=0x80,0x00,MCLR Disabled, RG5 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=BBSIZ,0x30,Boot Block Size CONFIG4L~4=ENHCPU,0x40,Extended CPU Enable CONFIG4L~5=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x20,0x20,4K Words (8 Kbytes) CONFIG4L~3~2=0x30,0x10,2K Words (4 Kbytes) CONFIG4L~3~3=0x30,0x00,1K Words (2 Kbytes) CONFIG4L~4~1=0x40,0x40,Enabled CONFIG4L~4~2=0x40,0x00,Disabled CONFIG4L~5~1=0x80,0x80,Disabled CONFIG4L~5~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-03FFF CONFIG5L~2=CP_1,0x2,Code Protect 04000-07FFF CONFIG5L~3=CP_2,0x4,Code Protect 08000-0BFFF CONFIG5L~4=CP_3,0x8,Code Protect 0C000-0FFFF CONFIG5L~5=CP_4,0x10,Code Protect 10000-13FFF CONFIG5L~6=CP_5,0x20,Code Protect 14000-17FFF CONFIG5L~7=CP_6,0x40,Code Protect 18000-1BFFF CONFIG5L~8=CP_7,0x80,Code Protect 1C000-1FFFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5L~5~1=0x10,0x10,Disabled CONFIG5L~5~2=0x10,0x00,Enabled CONFIG5L~6~1=0x20,0x20,Disabled CONFIG5L~6~2=0x20,0x00,Enabled CONFIG5L~7~1=0x40,0x40,Disabled CONFIG5L~7~2=0x40,0x00,Enabled CONFIG5L~8~1=0x80,0x80,Disabled CONFIG5L~8~2=0x80,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EE Read Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-03FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 04000-07FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 08000-0BFFF CONFIG6L~4=WRT_3,0x8,Table Write Protect 0C000-0FFFF CONFIG6L~5=WRT_4,0x10,Table Write Protect 10000-13FFF CONFIG6L~6=WRT_5,0x20,Table Write Protect 14000-17FFF CONFIG6L~7=WRT_6,0x40,Table Write Protect 18000-1BFFF CONFIG6L~8=WRT_7,0x80,Table Write Protect 1C000-1FFFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x00,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x00,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x00,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x00,Enabled CONFIG6L~5~1=0x10,0x10,Disabled CONFIG6L~5~2=0x10,0x00,Enabled CONFIG6L~6~1=0x20,0x20,Disabled CONFIG6L~6~2=0x20,0x00,Enabled CONFIG6L~7~1=0x40,0x40,Disabled CONFIG6L~7~2=0x40,0x00,Enabled CONFIG6L~8~1=0x80,0x80,Disabled CONFIG6L~8~2=0x80,0x00,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTD,0x80,Data EE Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTC,0x20,Config. Write Protect CONFIG6H~1~1=0x80,0x80,Disabled CONFIG6H~1~2=0x80,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x20,0x20,Disabled CONFIG6H~3~2=0x20,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-03FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 04000-07FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 08000-0BFFF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 0C000-0FFFF CONFIG7L~5=EBTR_4,0x10,Table Read Protect 10000-13FFF CONFIG7L~6=EBTR_5,0x20,Table Read Protect 14000-17FFF CONFIG7L~7=EBTR_6,0x40,Table Read Protect 18000-1BFFF CONFIG7L~8=EBTR_7,0x80,Table Read Protect 1C000-1FFFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x00,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x00,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x00,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x00,Enabled CONFIG7L~5~1=0x10,0x10,Disabled CONFIG7L~5~2=0x10,0x00,Enabled CONFIG7L~6~1=0x20,0x20,Disabled CONFIG7L~6~2=0x20,0x00,Enabled CONFIG7L~7~1=0x40,0x40,Disabled CONFIG7L~7~2=0x40,0x00,Enabled CONFIG7L~8~1=0x80,0x80,Disabled CONFIG7L~8~2=0x80,0x00,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA ------------------------------------------------------------------------------------------ ---- New as of 23/04/09 ------------------------------------------------------------------------------------------ [PIC18F1331] pgmmem=0x0 ~pgmmem=0x1FFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0x7f devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x1EA0 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004=CONFIG3L 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000a= 0x30000b= 0x30000c= 0x30000d= CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xC,0xC,EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xE,0xA,EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xF,0x5,EC-Port on RA6 CONFIG1H~1~8=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xF,0x2,HS CONFIG1H~1~10=0xF,0x1,XT CONFIG1H~1~11=0xF,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,BOR Enabled - SBOREN Disabled CONFIG2L~2~2=0x6,0x4,BOR when device active - SBOREN Disabled CONFIG2L~2~3=0x6,0x2,BOR controlled with SBOREN CONFIG2L~2~4=0x6,0x0,BOR Disabled - SBOREN Disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x08,4.2V CONFIG2L~3~4=0x18,0x00,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3L_unused=0x0 CONFIG3L~1=PWMPIN,0x2,PWM Output Pin Reset CONFIG3L~2=LPOL,0x4,Low-Side Transistors Polarity CONFIG3L~3=HPOL,0x8,High-Side Transistors Polarity CONFIG3L~1~1=0x2,0x2,PWM outputs disabled upon RESET CONFIG3L~1~2=0x2,0x0,PWM outputs drive active states upon RESET CONFIG3L~2~1=0x4,0x4,PWM 0, 2, 4 and 6 are active high CONFIG3L~2~2=0x4,0x0,PWM 0, 2, 4 and 6 are active low CONFIG3L~3~1=0x8,0x8,PWM 1, 3, 5, and 7 are active high CONFIG3L~3~2=0x8,0x0,PWM 1, 3, 5, and 7 are active low CONFIG3H_unused=0x0 CONFIG3H~1=MCLRE,0x80,Master Clear Enable CONFIG3H~2=T1OSCMX,0x08,T1OSC Mux bit CONFIG3H~3=FLTAMX,0x01,FLTA Mux bit CONFIG3H~1~1=0x80,0x80,MCLR enabled, RA5 input disabled CONFIG3H~1~2=0x80,0x00,MCLR disabled, RA5 input enabled CONFIG3H~2~1=0x08,0x08,T1OSC reside on RA6 and RA7 CONFIG3H~2~2=0x08,0x00,T1OSC reside on RB2 and RB3 CONFIG3H~3~1=0x01,0x01,FLTA is muxed onto RA5 CONFIG3H~3~2=0x01,0x00,FLTA is muxed onto RA7 CONFIG4L_unused=0x0 CONFIG4L~1=STVREN,0x1,Stack Overflow Reset CONFIG4L~2=ENICPORT,0x08,ICD/ICSP Port Enable bit CONFIG4L~3=BBSIZ,0x30,Boot Block Select bits CONFIG4L~4=ENHCPU,0x40,Enhanced CPU Enable bit CONFIG4L~5=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x08,0x08,Enabled CONFIG4L~2~2=0x08,0x00,Disabled CONFIG4L~3~1=0x30,0x30,Boot Block size is 1 KW if EN8K = 1/ 512 W if EN8K = 0 CONFIG4L~3~2=0x30,0x20,Boot Block size is 1 KW if EN8K = 1/ 512 W if EN8K = 0 CONFIG4L~3~3=0x30,0x10,Boot Block size is 512 W CONFIG4L~3~4=0x30,0x00,Boot Block size is 256 W CONFIG4L~4~1=0x40,0x40,Enabled CONFIG4L~4~2=0x40,0x0,Disabled CONFIG4L~5~1=0x80,0x80,Disabled CONFIG4L~5~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 000200-000FFF CONFIG5L~2=CP_1,0x2,Code Protect 001000-001FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EEPROM Code Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F2331] pgmmem=0x0 ~pgmmem=0x1FFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0xff devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x08E0 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004=CONFIG3L 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000a= 0x30000b= 0x30000c= 0x30000d= CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xC,0xC,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xE,0xA,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xF,0x5,EC-Port on RA6 CONFIG1H~1~8=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xF,0x3,0011 EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xF,0x2,HS CONFIG1H~1~11=0xF,0x1,XT CONFIG1H~1~12=0xF,0x0,LP CONFIG1H~2~1=0x40,0x40,Enabled CONFIG1H~2~2=0x40,0x0,Disabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x2,Brown Out Detect CONFIG2L~3=BODENV,0xC,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x2,0x2,Enabled CONFIG2L~2~2=0x2,0x0,Disabled CONFIG2L~3~1=0xC,0xC,Undefined CONFIG2L~3~2=0xC,0x8,2.7V CONFIG2L~3~3=0xC,0x4,4.2V CONFIG2L~3~4=0xC,0x0,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~3=WINEN,0x20,Watchdog Timer Window CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0xE,1:128 CONFIG2H~2~10=0x1E,0xC,1:64 CONFIG2H~2~11=0x1E,0xA,1:32 CONFIG2H~2~12=0x1E,0x8,1:16 CONFIG2H~2~13=0x1E,0x6,1:8 CONFIG2H~2~14=0x1E,0x4,1:4 CONFIG2H~2~15=0x1E,0x2,1:2 CONFIG2H~2~16=0x1E,0x0,1:1 CONFIG2H~3~1=0x20,0x20,Disabled CONFIG2H~3~2=0x20,0x0,Enabled CONFIG3L_unused=0x0 CONFIG3L~1=PWMPIN,0x4,PWM Output Pin Reset CONFIG3L~2=LPOL,0x8,Low-Side Transistors Polarity CONFIG3L~3=HPOL,0x10,High-Side Transistors Polarity CONFIG3L~4=T1OSCMX,0x20,Timer1 OSC CONFIG3L~1~1=0x4,0x4,PWM outputs disabled upon RESET CONFIG3L~1~2=0x4,0x0,PWM outputs drive active states upon RESET CONFIG3L~2~1=0x8,0x8,PWM 0, 2, 4 and 6 are active high CONFIG3L~2~2=0x8,0x0,PWM 0, 2, 4 and 6 are active low CONFIG3L~3~1=0x10,0x10,PWM 1, 3, 5, and 7 are active high CONFIG3L~3~2=0x10,0x0,PWM 1, 3, 5, and 7 are active low CONFIG3L~4~1=0x20,0x20,Low Power CONFIG3L~4~2=0x20,0x0,Legacy CONFIG3H_unused=0x0 CONFIG3H~1=FLTAMX,0x1,FLTA Mux CONFIG3H~2=SSPMX,0x4,SSP I/O Mux CONFIG3H~3=PWM4MX,0x8,PWM4 Mux CONFIG3H~4=EXCLKMX,0x10,TMR0/T5CKI EXT CLK Mux CONFIG3H~5=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,FLTA input muxed with RC1 CONFIG3H~1~2=0x1,0x0,FLTA input muxed with RD4 CONFIG3H~2~1=0x4,0x0,SPI not assigned CONFIG3H~2~2=0x4,0x4,SCK/SCL, SDA/SDI and SDO are mux w/ RC5, RC4 and RC7 respectively. CONFIG3H~3~1=0x8,0x8,PWM4 output muxed w/ RB5 CONFIG3H~3~2=0x8,0x0,PWM4 output muxed w/ RD5 CONFIG3H~4~1=0x10,0x0,TMR0/T5CKI external clock input is multiplexed with RD0 CONFIG3H~4~2=0x10,0x10,TMR0/T5CKI external clock input is multiplexed with RC3 CONFIG3H~5~1=0x80,0x80,MCLR enabled, RE3 input disabled CONFIG3H~5~2=0x80,0x0,RE3 input enabled, MCLR disabled CONFIG4L_unused=0x0 CONFIG4L~1=BACKBUG,0x80,Background Debug CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=STVR,0x1,Stack Overflow Reset CONFIG4L~1~1=0x80,0x80,Disabled CONFIG4L~1~2=0x80,0x0,Enabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x1,0x1,Enabled CONFIG4L~3~2=0x1,0x0,Disabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00200-00FFF CONFIG5L~2=CP_1,0x2,Code Protect 01000-01FFF CONFIG5L~3=CP_2,0x4,Code Protect 02000-02FFF CONFIG5L~4=CP_3,0x8,Code Protect 03000-03FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EE Read Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F2423] pgmmem=0x0 ~pgmmem=0x3fff cfgmem=0x300000 ~cfgmem=0x30000d userid=0x200000 ~userid=0x200007 eedata=0x0 ~eedata=0xff devid=0x3ffffe ~devid=0x3fffff idmask=0xfff0 id=0x1150 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000a=CONFIG6L 0x30000b=CONFIG6H 0x30000c=CONFIG7L 0x30000d=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xf,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xc,0xc,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xe,0xa,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xf,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xf,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xf,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xf,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xf,0x5,EC-Port on RA6 CONFIG1H~1~8=0xf,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xf,0x3,0011 EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xf,0x2,HS CONFIG1H~1~11=0xf,0x1,XT CONFIG1H~1~12=0xf,0x0,LP CONFIG1H~2~1=0x40,0x40,Enabled CONFIG1H~2~2=0x40,0x0,Disabled CONFIG1H~3~1=0x80,0x80,Enabled CONFIG1H~3~2=0x80,0x0,Disabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x8,4.2V CONFIG2L~3~4=0x18,0x0,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1e,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1e,0x1e,1:32768 CONFIG2H~2~2=0x1e,0x1c,1:16384 CONFIG2H~2~3=0x1e,0x1a,1:8192 CONFIG2H~2~4=0x1e,0x18,1:4096 CONFIG2H~2~5=0x1e,0x16,1:2048 CONFIG2H~2~6=0x1e,0x14,1:1024 CONFIG2H~2~7=0x1e,0x12,1:512 CONFIG2H~2~8=0x1e,0x10,1:256 CONFIG2H~2~9=0x1e,0xe,1:128 CONFIG2H~2~10=0x1e,0xc,1:64 CONFIG2H~2~11=0x1e,0xa,1:32 CONFIG2H~2~12=0x1e,0x8,1:16 CONFIG2H~2~13=0x1e,0x6,1:8 CONFIG2H~2~14=0x1e,0x4,1:4 CONFIG2H~2~15=0x1e,0x2,1:2 CONFIG2H~2~16=0x1e,0x0,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=PBADEN,0x2,PortB A/D Enable CONFIG3H~3=LPT1OSC,0x4,Low Power Timer1 Osc enable CONFIG3H~4=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RB3 CONFIG3H~2~1=0x2,0x2,PORTB<4:0> configured as analog inputs on RESET CONFIG3H~2~2=0x2,0x0,PORTB<4:0> configured as digital I/O on RESET CONFIG3H~3~1=0x4,0x4,Enabled CONFIG3H~3~2=0x4,0x0,Disabled CONFIG3H~4~1=0x80,0x80,MCLR Enabled,RE3 Disabled CONFIG3H~4~2=0x80,0x0,MCLR Disabled,RE3 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=XINST,0x40,Extended Instruction Set Enable bit CONFIG4L~4=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x40,0x40,Enabled CONFIG4L~3~2=0x40,0x0,Disabled CONFIG4L~4~1=0x80,0x80,Disabled CONFIG4L~4~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-01FFF CONFIG5L~2=CP_1,0x2,Code Protect 02000-03FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x0,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x0,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPB,0x40,Code Protect Boot CONFIG5H~2=CPD,0x80,Data EEPROM Code Protect CONFIG5H~1~1=0x40,0x40,Disabled CONFIG5H~1~2=0x40,0x0,Enabled CONFIG5H~2~1=0x80,0x80,Disabled CONFIG5H~2~2=0x80,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-01FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 02000-03FFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x0,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x0,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTC,0x20,Config. Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTD,0x80,Data EEPROM Write Protect CONFIG6H~1~1=0x20,0x20,Disabled CONFIG6H~1~2=0x20,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x80,0x80,Disabled CONFIG6H~3~2=0x80,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-01FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 02000-03FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x0,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x0,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F2458] pgmmem=0x0 ~pgmmem=0x5fff cfgmem=0x300000 ~cfgmem=0x30000d userid=0x200000 ~userid=0x200007 eedata=0x0 ~eedata=0xff devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0x2a60 configslots=14 0x300000=CONFIG1L 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000a=CONFIG6L 0x30000b=CONFIG6H 0x30000c=CONFIG7L 0x30000d=CONFIG7H CONFIG1L_unused=0x0 CONFIG1L~1=PLLDIV,0x7,96MHz PLL Prescaler CONFIG1L~2=CPUDIV,0x18,CPU System Clock Postscaler CONFIG1L~3=USBPLL,0x20,Full-Speed USB Clock Source Selection CONFIG1L~1~1=0x7,0x7,Divide by 12 (48MHz input) CONFIG1L~1~2=0x7,0x6,Divide by 10 (40MHz input) CONFIG1L~1~3=0x7,0x5,Divide by 6 (24MHz input) CONFIG1L~1~4=0x7,0x4,Divide by 5 (20MHz input) CONFIG1L~1~5=0x7,0x3,Divide by 4 (16MHz input) CONFIG1L~1~6=0x7,0x2,Divide by 3 (12MHz input) CONFIG1L~1~7=0x7,0x1,Divide by 2 (8MHz input) CONFIG1L~1~8=0x7,0x0,No Divide (4MHz input) CONFIG1L~2~1=0x18,0x18,[OSC1/OSC2 Src: /4][96MHz PLL Src: /6] CONFIG1L~2~2=0x18,0x10,[OSC1/OSC2 Src: /3][96MHz PLL Src: /4] CONFIG1L~2~3=0x18,0x8,[OSC1/OSC2 Src: /2][96MHz PLL Src: /3] CONFIG1L~2~4=0x18,0x0,[OSC1/OSC2 Src: /1][96MHz PLL Src: /2] CONFIG1L~3~1=0x20,0x20,Clock src from 96MHz PLL/2 CONFIG1L~3~2=0x20,0x0,Clock src from OSC1/OSC2 CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xf,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xe,0xe,HS: HS+PLL, USB-HS CONFIG1H~1~2=0xe,0xc,HS: USB-HS CONFIG1H~1~3=0xf,0xb,INTOSC: USB-HS CONFIG1H~1~4=0xf,0xa,INTOSC: USB-XT CONFIG1H~1~5=0xf,0x9,INTOSC: INTOSC+CLK0{RA6}, USB-EC CONFIG1H~1~6=0xf,0x8,INTOSC: INTOSC+RA6, USB-EC CONFIG1H~1~7=0xf,0x7,EC: EC+PLL, EC+PLL+CLKO{RA6}, USB-EC CONFIG1H~1~8=0xf,0x6,EC: EC+PLL, EC+PLL+RA6, USB-EC CONFIG1H~1~9=0xf,0x5,EC: EC+CLKO{RA6}, USB-EC CONFIG1H~1~10=0xf,0x4,EC: EC+RA6, USB-EC CONFIG1H~1~11=0xe,0x2,XT: XT+PLL, USB-XT CONFIG1H~1~12=0xe,0x0,XT: USB-XT CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~4=VREGEN,0x20,USB Voltage Regulator CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x8,4.2V CONFIG2L~3~4=0x18,0x0,4.5V CONFIG2L~4~1=0x20,0x20,Enabled CONFIG2L~4~2=0x20,0x0,Disabled CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1e,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1e,0x1e,1:32768 CONFIG2H~2~2=0x1e,0x1c,1:16384 CONFIG2H~2~3=0x1e,0x1a,1:8192 CONFIG2H~2~4=0x1e,0x18,1:4096 CONFIG2H~2~5=0x1e,0x16,1:2048 CONFIG2H~2~6=0x1e,0x14,1:1024 CONFIG2H~2~7=0x1e,0x12,1:512 CONFIG2H~2~8=0x1e,0x10,1:256 CONFIG2H~2~9=0x1e,0xe,1:128 CONFIG2H~2~10=0x1e,0xc,1:64 CONFIG2H~2~11=0x1e,0xa,1:32 CONFIG2H~2~12=0x1e,0x8,1:16 CONFIG2H~2~13=0x1e,0x6,1:8 CONFIG2H~2~14=0x1e,0x4,1:4 CONFIG2H~2~15=0x1e,0x2,1:2 CONFIG2H~2~16=0x1e,0x0,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=PBADEN,0x2,PortB A/D Enable CONFIG3H~3=LPT1OSC,0x4,Low Power Timer1 Osc enable CONFIG3H~4=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RB3 CONFIG3H~2~1=0x2,0x2,PORTB<4:0> configured as analog inputs on RESET CONFIG3H~2~2=0x2,0x0,PORTB<4:0> configured as digital I/O on RESET CONFIG3H~3~1=0x4,0x4,Enabled CONFIG3H~3~2=0x4,0x0,Disabled CONFIG3H~4~1=0x80,0x80,MCLR Enabled,RE3 Disabled CONFIG3H~4~2=0x80,0x0,MCLR Disabled,RE3 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=ENICPORT,0x20,Dedicated In-Circuit Port {ICD/ICSP} CONFIG4L~4=XINST,0x40,Extended Instruction Set Enable bit CONFIG4L~5=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x20,0x0,Disabled CONFIG4L~4~1=0x40,0x40,Enabled CONFIG4L~4~2=0x40,0x0,Disabled CONFIG4L~5~1=0x80,0x80,Disabled CONFIG4L~5~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-01FFF CONFIG5L~2=CP_1,0x2,Code Protect 02000-03FFF CONFIG5L~3=CP_2,0x4,Code Protect 04000-05FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x0,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x0,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x0,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPB,0x40,Code Protect Boot CONFIG5H~2=CPD,0x80,Data EE Read Protect CONFIG5H~1~1=0x40,0x40,Disabled CONFIG5H~1~2=0x40,0x0,Enabled CONFIG5H~2~1=0x80,0x80,Disabled CONFIG5H~2~2=0x80,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-01FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 02000-03FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 04000-05FFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x0,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x0,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x0,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTC,0x20,Config. Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTD,0x80,Data EE Write Protect CONFIG6H~1~1=0x20,0x20,Disabled CONFIG6H~1~2=0x20,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x80,0x80,Disabled CONFIG6H~3~2=0x80,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-01FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 02000-03FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 04000-05FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x0,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x0,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x0,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F24J10] pgmmem=0x0 ~pgmmem=0x3FF7 cfgmem=0x3ff8 ~cfgmem=0x3fff userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0xf5f devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x1D00 configslots=8 0x3ff8=CONFIG1L 0x3ff9=CONFIG1H 0x3ffa=CONFIG2L 0x3ffb=CONFIG2H 0x3ffc=CONFIG3L 0x3ffd=CONFIG3H 0x3ffe= 0x3fff= CONFIG1L_unused=0x00 CONFIG1L~1=WDTEN,0x01,Watchdog Timer Enable CONFIG1L~2=STVREN,0x20,Stack Overflow Reset Enable CONFIG1L~3=ENHCPU,0x40,Enhanced CPU Enable CONFIG1L~4=BACKBUG,0x80,Background Debug CONFIG1L~1~1=0x01,0x01,Enabled CONFIG1L~1~2=0x01,0x00,Disabled CONFIG1L~2~1=0x20,0x20,Enabled CONFIG1L~2~2=0x20,0x00,Disabled CONFIG1L~3~1=0x40,0x40,Enabled CONFIG1L~3~2=0x40,0x00,Disabled CONFIG1L~4~1=0x80,0x80,Disabled CONFIG1L~4~2=0x80,0x00,Enabled CONFIG1H_unused=0x00 CONFIG1H~1=CP_0,0x4,Code Protect Enable CONFIG1H~2=SIGN,0x8,Config Word Signature Bit CONFIG1H~3=FNOP_0,0xF0,Force NOP CONFIG1H~1~1=0x4,0x4,Disabled CONFIG1H~1~2=0x4,0x00,Enabled CONFIG1H~2~1=0x8,0x8,Bulk erase of memory not conducated CONFIG1H~2~2=0x8,0x0,Bulk erase of memory area complete CONFIG1H~3~1=0xF0,0xF0,NOPd CONFIG2L_unused=0x00 CONFIG2L~1=FOSC,0x03,Oscillator CONFIG2L~2=FOSC2,0x04,Default/Reset System Clock Select CONFIG2L~3=FCMEN,0x40,Fail Safe Monitor Clock Enable CONFIG2L~4=IESO,0x80,Internal External Switch Over Enable CONFIG2L~1~1=0x03,0x03,EC OSC with software PLL and CLKOUT on OSC2 CONFIG2L~1~2=0x03,0x02,EC OSC with CLKOUT on OSC2 CONFIG2L~1~3=0x03,0x01,HS OSC with software PLL CONFIG2L~1~4=0x03,0x00,HS OSC CONFIG2L~2~1=0x04,0x04,Clock Select by FOSC CONFIG2L~2~2=0x04,0x00,INTRC enabled CONFIG2L~3~1=0x40,0x40,Enabled CONFIG2L~3~2=0x40,0x00,Disabled CONFIG2L~4~1=0x80,0x80,Enabled CONFIG2L~4~2=0x80,0x00,Disabled CONFIG2H_unused=0x00 CONFIG2H~1=WDTPS,0x0f,Watchdog Timer Postscale CONFIG2H~2=FNOP_1,0xF0,Force NOP CONFIG2H~1~1=0x000f,0x000f,1:32,768 CONFIG2H~1~2=0x000f,0x000e,1:16,384 CONFIG2H~1~3=0x000f,0x000d,1:8,192 CONFIG2H~1~4=0x000f,0x000c,1:4,096 CONFIG2H~1~5=0x000f,0x000b,1:2,048 CONFIG2H~1~6=0x000f,0x000a,1:1,024 CONFIG2H~1~7=0x000f,0x0009,1:512 CONFIG2H~1~8=0x000f,0x0008,1:256 CONFIG2H~1~9=0x000f,0x0007,1:128 CONFIG2H~1~10=0x000f,0x0006,1:64 CONFIG2H~1~11=0x000f,0x0005,1:32 CONFIG2H~1~12=0x000f,0x0004,1:16 CONFIG2H~1~13=0x000f,0x0003,1:8 CONFIG2H~1~14=0x000f,0x0002,1:4 CONFIG2H~1~15=0x000f,0x0001,1:2 CONFIG2H~1~16=0x000f,0x0000,1:1 CONFIG2H~2~1=0xF0,0xF0,NOPd CONFIG3L_unused=0x00 CONFIG3H_unused=0x00 CONFIG3H~1=CCP2MX,0x01,CCP2 Mux CONFIG3H~2=FNOP_2,0xF0,Force NOP CONFIG3H~1~1=0x01,0x01,CCP2 I/O Muxed with RC1 CONFIG3H~1~2=0x01,0x00,CCP2 I/O Muxed with RB3 CONFIG3H~2~1=0xF0,0xF0,NOPd erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F24K20] pgmmem=0x0 ~pgmmem=0x3FFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0xff devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x20A0 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000a= 0x30000b= 0x30000c= 0x30000d= CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xC,0xC,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xE,0xA,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xF,0x5,EC-Port on RA6 CONFIG1H~1~8=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xF,0x3,0011 EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xF,0x2,HS CONFIG1H~1~11=0xF,0x1,XT CONFIG1H~1~12=0xF,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x08,4.2V CONFIG2L~3~4=0x18,0x00,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=PBADEN,0x2,PortB A/D Enable CONFIG3H~3=LPT1OSC,0x04,Low Power Timer1 Osc enable CONFIG3H~4=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RB3 CONFIG3H~2~1=0x2,0x2,PORTB<4:0> configured as analog inputs on RESET CONFIG3H~2~2=0x2,0x0,PORTB<4:0> configured as digital I/O on RESET CONFIG3H~3~1=0x04,0x04,Enabled CONFIG3H~3~2=0x04,0x00,Disabled CONFIG3H~4~1=0x80,0x80,MCLR Enabled,RE3 Disabled CONFIG3H~4~2=0x80,0x00,MCLR Disabled,RE3 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=ENHCPU,0x40,Extended CPU Enable CONFIG4L~4=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x40,0x40,Enabled CONFIG4L~3~2=0x40,0x00,Disabled CONFIG4L~4~1=0x80,0x80,Disabled CONFIG4L~4~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-01FFF CONFIG5L~2=CP_1,0x2,Code Protect 02000-03FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EEPROM Code Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F2523] pgmmem=0x0 ~pgmmem=0x7fff cfgmem=0x300000 ~cfgmem=0x30000d userid=0x200000 ~userid=0x200007 eedata=0x0 ~eedata=0xff devid=0x3ffffe ~devid=0x3fffff idmask=0xfff0 id=0x1110 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000a=CONFIG6L 0x30000b=CONFIG6H 0x30000c=CONFIG7L 0x30000d=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xf,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xc,0xc,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xe,0xa,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xf,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xf,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xf,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xf,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xf,0x5,EC-Port on RA6 CONFIG1H~1~8=0xf,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xf,0x3,0011 EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xf,0x2,HS CONFIG1H~1~11=0xf,0x1,XT CONFIG1H~1~12=0xf,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x8,4.2V CONFIG2L~3~4=0x18,0x0,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1e,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1e,0x1e,1:32768 CONFIG2H~2~2=0x1e,0x1c,1:16384 CONFIG2H~2~3=0x1e,0x1a,1:8192 CONFIG2H~2~4=0x1e,0x18,1:4096 CONFIG2H~2~5=0x1e,0x16,1:2048 CONFIG2H~2~6=0x1e,0x14,1:1024 CONFIG2H~2~7=0x1e,0x12,1:512 CONFIG2H~2~8=0x1e,0x10,1:256 CONFIG2H~2~9=0x1e,0xe,1:128 CONFIG2H~2~10=0x1e,0xc,1:64 CONFIG2H~2~11=0x1e,0xa,1:32 CONFIG2H~2~12=0x1e,0x8,1:16 CONFIG2H~2~13=0x1e,0x6,1:8 CONFIG2H~2~14=0x1e,0x4,1:4 CONFIG2H~2~15=0x1e,0x2,1:2 CONFIG2H~2~16=0x1e,0x0,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=PBADEN,0x2,PortB A/D Enable CONFIG3H~3=LPT1OSC,0x4,Low Power Timer1 Osc enable CONFIG3H~4=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RB3 CONFIG3H~2~1=0x2,0x2,PORTB<4:0> configured as analog inputs on RESET CONFIG3H~2~2=0x2,0x0,PORTB<4:0> configured as digital I/O on RESET CONFIG3H~3~1=0x4,0x4,Enabled CONFIG3H~3~2=0x4,0x0,Disabled CONFIG3H~4~1=0x80,0x80,MCLR Enabled,RE3 Disabled CONFIG3H~4~2=0x80,0x0,MCLR Disabled,RE3 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=XINST,0x40,Extended Instruction Set Enable bit CONFIG4L~4=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x40,0x40,Enabled CONFIG4L~3~2=0x40,0x0,Disabled CONFIG4L~4~1=0x80,0x80,Disabled CONFIG4L~4~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-01FFF CONFIG5L~2=CP_1,0x2,Code Protect 02000-03FFF CONFIG5L~3=CP_2,0x4,Code Protect 04000-05FFF CONFIG5L~4=CP_3,0x8,Code Protect 06000-07FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x0,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x0,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x0,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x0,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPB,0x40,Code Protect Boot CONFIG5H~2=CPD,0x80,Data EEPROM Code Protect CONFIG5H~1~1=0x40,0x40,Disabled CONFIG5H~1~2=0x40,0x0,Enabled CONFIG5H~2~1=0x80,0x80,Disabled CONFIG5H~2~2=0x80,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-01FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 02000-03FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 04000-05FFF CONFIG6L~4=WRT_3,0x8,Table Write Protect 06000-07FFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x0,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x0,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x0,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x0,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTC,0x20,Config. Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTD,0x80,Data EEPROM Write Protect CONFIG6H~1~1=0x20,0x20,Disabled CONFIG6H~1~2=0x20,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x80,0x80,Disabled CONFIG6H~3~2=0x80,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-01FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 02000-03FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 04000-05FFF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 06000-07FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x0,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x0,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x0,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x0,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F2586] pgmmem=0x0 ~pgmmem=0xBFFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata= ~eedata= devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x0E60 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000a= 0x30000b= 0x30000c= 0x30000d= CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xC,0xC,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xE,0xA,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xF,0x5,EC-Port on RA6 CONFIG1H~1~8=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xF,0x3,EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xF,0x2,HS CONFIG1H~1~11=0xF,0x1,XT CONFIG1H~1~12=0xF,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x08,4.2V CONFIG2L~3~4=0x18,0x00,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=PBADEN,0x2,PortB A/D Enable CONFIG3H~2=LPT1OSC,0x04,Low Power Timer1 Osc enable CONFIG3H~3=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x2,0x2,PORTB<4> and <1:0> configured as analog inputs on RESET CONFIG3H~1~2=0x2,0x0,PORTB<4> and <1:0> configured as digital I/O on RESET CONFIG3H~2~1=0x04,0x04,Enabled CONFIG3H~2~2=0x04,0x00,Disabled CONFIG3H~3~1=0x80,0x80,MCLR Enabled,RE3 Disabled CONFIG3H~3~2=0x80,0x00,MCLR Disabled, RE3 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=ENHCPU,0x40,Extended CPU Enable CONFIG4L~4=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x40,0x40,Enabled CONFIG4L~3~2=0x40,0x00,Disabled CONFIG4L~4~1=0x80,0x80,Disabled CONFIG4L~4~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-03FFF CONFIG5L~2=CP_1,0x2,Code Protect 04000-07FFF CONFIG5L~3=CP_2,0x4,Code Protect 08000-0BFFF CONFIG5L~4=CP_3,0x8,Code Protect 0C000-0FFFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EE Read Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F25J10] pgmmem=0x0 ~pgmmem=0x7FF7 cfgmem=0x7ff8 ~cfgmem=0x7fff userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0xf5f devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x1C00 configslots=8 0x7ff8=CONFIG1L 0x7ff9=CONFIG1H 0x7ffa=CONFIG2L 0x7ffb=CONFIG2H 0x7ffc=CONFIG3L 0x7ffd=CONFIG3H 0x7ffe= 0x7fff= CONFIG1L_unused=0x00 CONFIG1L~1=WDTEN,0x01,Watchdog Timer Enable CONFIG1L~2=STVREN,0x20,Stack Overflow Reset Enable CONFIG1L~3=ENHCPU,0x40,Enhanced CPU Enable CONFIG1L~4=BACKBUG,0x80,Background Debug CONFIG1L~1~1=0x01,0x01,Enabled CONFIG1L~1~2=0x01,0x00,Disabled CONFIG1L~2~1=0x20,0x20,Enabled CONFIG1L~2~2=0x20,0x00,Disabled CONFIG1L~3~1=0x40,0x40,Enabled CONFIG1L~3~2=0x40,0x00,Disabled CONFIG1L~4~1=0x80,0x80,Disabled CONFIG1L~4~2=0x80,0x00,Enabled CONFIG1H_unused=0x00 CONFIG1H~1=CP_0,0x4,Code Protect Enable CONFIG1H~2=SIGN,0x8,Config Word Signature Bit CONFIG1H~3=FNOP_0,0xF0,Force NOP CONFIG1H~1~1=0x4,0x4,Disabled CONFIG1H~1~2=0x4,0x00,Enabled CONFIG1H~2~1=0x8,0x8,Bulk erase of memory not conducated CONFIG1H~2~2=0x8,0x0,Bulk erase of memory area complete CONFIG1H~3~1=0xF0,0xF0,NOPd CONFIG2L_unused=0x00 CONFIG2L~1=FOSC,0x03,Oscillator CONFIG2L~2=FOSC2,0x04,Default/Reset System Clock Select CONFIG2L~3=FCMEN,0x40,Fail Safe Monitor Clock Enable CONFIG2L~4=IESO,0x80,Internal External Switch Over Enable CONFIG2L~1~1=0x03,0x03,EC OSC with software PLL and CLKOUT on OSC2 CONFIG2L~1~2=0x03,0x02,EC OSC with CLKOUT on OSC2 CONFIG2L~1~3=0x03,0x01,HS OSC with software PLL CONFIG2L~1~4=0x03,0x00,HS OSC CONFIG2L~2~1=0x04,0x04,Clock Select by FOSC CONFIG2L~2~2=0x04,0x00,INTRC enabled CONFIG2L~3~1=0x40,0x40,Enabled CONFIG2L~3~2=0x40,0x00,Disabled CONFIG2L~4~1=0x80,0x80,Enabled CONFIG2L~4~2=0x80,0x00,Disabled CONFIG2H_unused=0x00 CONFIG2H~1=WDTPS,0x0f,Watchdog Timer Postscale CONFIG2H~2=FNOP_1,0xF0,Force NOP CONFIG2H~1~1=0x000f,0x000f,1:32,768 CONFIG2H~1~2=0x000f,0x000e,1:16,384 CONFIG2H~1~3=0x000f,0x000d,1:8,192 CONFIG2H~1~4=0x000f,0x000c,1:4,096 CONFIG2H~1~5=0x000f,0x000b,1:2,048 CONFIG2H~1~6=0x000f,0x000a,1:1,024 CONFIG2H~1~7=0x000f,0x0009,1:512 CONFIG2H~1~8=0x000f,0x0008,1:256 CONFIG2H~1~9=0x000f,0x0007,1:128 CONFIG2H~1~10=0x000f,0x0006,1:64 CONFIG2H~1~11=0x000f,0x0005,1:32 CONFIG2H~1~12=0x000f,0x0004,1:16 CONFIG2H~1~13=0x000f,0x0003,1:8 CONFIG2H~1~14=0x000f,0x0002,1:4 CONFIG2H~1~15=0x000f,0x0001,1:2 CONFIG2H~1~16=0x000f,0x0000,1:1 CONFIG2H~2~1=0xF0,0xF0,NOPd CONFIG3L_unused=0x00 CONFIG3H_unused=0x00 CONFIG3H~1=CCP2MX,0x01,CCP2 Mux CONFIG3H~2=FNOP_2,0xF0,Force NOP CONFIG3H~1~1=0x01,0x01,CCP2 I/O Muxed with RC1 CONFIG3H~1~2=0x01,0x00,CCP2 I/O Muxed with RB3 CONFIG3H~2~1=0xF0,0xF0,NOPd erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F25K20] pgmmem=0x0 ~pgmmem=0x7FFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0xff devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x2060 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000a= 0x30000b= 0x30000c= 0x30000d= CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xC,0xC,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xE,0xA,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xF,0x5,EC-Port on RA6 CONFIG1H~1~8=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xF,0x3,0011 EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xF,0x2,HS CONFIG1H~1~11=0xF,0x1,XT CONFIG1H~1~12=0xF,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x08,4.2V CONFIG2L~3~4=0x18,0x00,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=PBADEN,0x2,PortB A/D Enable CONFIG3H~3=LPT1OSC,0x04,Low Power Timer1 Osc enable CONFIG3H~4=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RB3 CONFIG3H~2~1=0x2,0x2,PORTB<4:0> configured as analog inputs on RESET CONFIG3H~2~2=0x2,0x0,PORTB<4:0> configured as digital I/O on RESET CONFIG3H~3~1=0x04,0x04,Enabled CONFIG3H~3~2=0x04,0x00,Disabled CONFIG3H~4~1=0x80,0x80,MCLR Enabled,RE3 Disabled CONFIG3H~4~2=0x80,0x00,MCLR Disabled,RE3 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=ENHCPU,0x40,Extended CPU Enable CONFIG4L~4=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x40,0x40,Enabled CONFIG4L~3~2=0x40,0x00,Disabled CONFIG4L~4~1=0x80,0x80,Disabled CONFIG4L~4~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-01FFF CONFIG5L~2=CP_1,0x2,Code Protect 02000-03FFF CONFIG5L~3=CP_2,0x4,Code Protect 04000-05FFF CONFIG5L~4=CP_3,0x8,Code Protect 06000-07FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EEPROM Code Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F2681] pgmmem=0x0 ~pgmmem=0xFFFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata= ~eedata= devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x0E40 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000a= 0x30000b= 0x30000c= 0x30000d= CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xC,0xC,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xA,0xA,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xF,0x5,EC-Port on RA6 CONFIG1H~1~8=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xF,0x3,EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xF,0x2,HS CONFIG1H~1~11=0xF,0x1,XT CONFIG1H~1~12=0xF,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x08,4.2V CONFIG2L~3~4=0x18,0x00,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=PBADEN,0x2,PortB A/D Enable CONFIG3H~2=LPT1OSC,0x04,Low Power Timer1 Osc enable CONFIG3H~3=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x2,0x2,PORTB<4> and <1:0> configured as analog inputs on RESET CONFIG3H~1~2=0x2,0x0,PORTB<4> and <1:0> configured as digital I/O on RESET CONFIG3H~2~1=0x04,0x04,Enabled CONFIG3H~2~2=0x04,0x00,Disabled CONFIG3H~3~1=0x80,0x80,MCLR Enabled,RE3 Disabled CONFIG3H~3~2=0x80,0x00,MCLR Disabled, RE3 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=ENHCPU,0x40,Extended CPU Enable CONFIG4L~4=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x40,0x40,Enabled CONFIG4L~3~2=0x40,0x00,Disabled CONFIG4L~4~1=0x80,0x80,Disabled CONFIG4L~4~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-03FFF CONFIG5L~2=CP_1,0x2,Code Protect 04000-07FFF CONFIG5L~3=CP_2,0x4,Code Protect 08000-0BFFF CONFIG5L~4=CP_3,0x8,Code Protect 0C000-0FFFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EE Read Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F26K20] pgmmem=0x0 ~pgmmem=0xffff cfgmem=0x300000 ~cfgmem=0x30000d userid=0x200000 ~userid=0x200007 eedata=0x0 ~eedata=0x3ff devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0x2020 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000a=CONFIG6L 0x30000b=CONFIG6H 0x30000c=CONFIG7L 0x30000d=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xf,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xc,0xc,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xe,0xa,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xf,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xf,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xf,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xf,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xf,0x5,EC-Port on RA6 CONFIG1H~1~8=0xf,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xf,0x3,0011 EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xf,0x2,HS CONFIG1H~1~11=0xf,0x1,XT CONFIG1H~1~12=0xf,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,1.8V CONFIG2L~3~2=0x18,0x10,2.3V CONFIG2L~3~3=0x18,0x8,2.8V CONFIG2L~3~4=0x18,0x0,3.1V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1e,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1e,0x1e,1:32768 CONFIG2H~2~2=0x1e,0x1c,1:16384 CONFIG2H~2~3=0x1e,0x1a,1:8192 CONFIG2H~2~4=0x1e,0x18,1:4096 CONFIG2H~2~5=0x1e,0x16,1:2048 CONFIG2H~2~6=0x1e,0x14,1:1024 CONFIG2H~2~7=0x1e,0x12,1:512 CONFIG2H~2~8=0x1e,0x10,1:256 CONFIG2H~2~9=0x1e,0xe,1:128 CONFIG2H~2~10=0x1e,0xc,1:64 CONFIG2H~2~11=0x1e,0xa,1:32 CONFIG2H~2~12=0x1e,0x8,1:16 CONFIG2H~2~13=0x1e,0x6,1:8 CONFIG2H~2~14=0x1e,0x4,1:4 CONFIG2H~2~15=0x1e,0x2,1:2 CONFIG2H~2~16=0x1e,0x0,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=PBADEN,0x2,PortB A/D Enable CONFIG3H~3=LPT1OSC,0x4,Low Power Timer1 Osc enable CONFIG3H~4=HFOFST,0x8,HFINTOSC Fast Start CONFIG3H~5=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RB3 CONFIG3H~2~1=0x2,0x2,PORTB<4:0> configured as analog inputs on RESET CONFIG3H~2~2=0x2,0x0,PORTB<4:0> configured as digital I/O on RESET CONFIG3H~3~1=0x4,0x4,Enabled CONFIG3H~3~2=0x4,0x0,Disabled CONFIG3H~4~1=0x8,0x8,HFINTOSC is not delayed CONFIG3H~4~2=0x8,0x0,HFINTOSC is delayed until oscillator is stable(IOFS=1) CONFIG3H~5~1=0x80,0x80,MCLR Enabled,RE3 Disabled CONFIG3H~5~2=0x80,0x0,MCLR Disabled,RE3 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=XINST,0x40,Extended Instruction Set Enable bit CONFIG4L~4=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x40,0x40,Enabled CONFIG4L~3~2=0x40,0x0,Disabled CONFIG4L~4~1=0x80,0x80,Disabled CONFIG4L~4~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-03FFF CONFIG5L~2=CP_1,0x2,Code Protect 04000-07FFF CONFIG5L~3=CP_2,0x4,Code Protect 08000-0BFFF CONFIG5L~4=CP_3,0x8,Code Protect 0C000-0FFFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x0,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x0,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x0,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x0,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPB,0x40,Code Protect Boot CONFIG5H~2=CPD,0x80,Data EE Read Protect CONFIG5H~1~1=0x40,0x40,Disabled CONFIG5H~1~2=0x40,0x0,Enabled CONFIG5H~2~1=0x80,0x80,Disabled CONFIG5H~2~2=0x80,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00200-007FF CONFIG6L~2=WRT_1,0x2,Table Write Protect 00800-00FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 01000-017FF CONFIG6L~4=WRT_3,0x8,Table Write Protect 01800-01FFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x0,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x0,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x0,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x0,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTC,0x20,Config. Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTD,0x80,Data EE Write Protect CONFIG6H~1~1=0x20,0x20,Disabled CONFIG6H~1~2=0x20,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x80,0x80,Disabled CONFIG6H~3~2=0x80,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-01FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 02000-03FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 04000-05FFF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 06000-07FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x0,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x0,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x0,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x0,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F4423] pgmmem=0x0 ~pgmmem=0x3fff cfgmem=0x300000 ~cfgmem=0x30000d userid=0x200000 ~userid=0x200007 eedata=0x0 ~eedata=0xff devid=0x3ffffe ~devid=0x3fffff idmask=0xfff0 id=0x10d0 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000a=CONFIG6L 0x30000b=CONFIG6H 0x30000c=CONFIG7L 0x30000d=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xf,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xc,0xc,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xe,0xa,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xf,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xf,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xf,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xf,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xf,0x5,EC-Port on RA6 CONFIG1H~1~8=0xf,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xf,0x3,0011 EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xf,0x2,HS CONFIG1H~1~11=0xf,0x1,XT CONFIG1H~1~12=0xf,0x0,LP CONFIG1H~2~1=0x40,0x40,Enabled CONFIG1H~2~2=0x40,0x0,Disabled CONFIG1H~3~1=0x80,0x80,Enabled CONFIG1H~3~2=0x80,0x0,Disabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x8,4.2V CONFIG2L~3~4=0x18,0x0,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1e,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1e,0x1e,1:32768 CONFIG2H~2~2=0x1e,0x1c,1:16384 CONFIG2H~2~3=0x1e,0x1a,1:8192 CONFIG2H~2~4=0x1e,0x18,1:4096 CONFIG2H~2~5=0x1e,0x16,1:2048 CONFIG2H~2~6=0x1e,0x14,1:1024 CONFIG2H~2~7=0x1e,0x12,1:512 CONFIG2H~2~8=0x1e,0x10,1:256 CONFIG2H~2~9=0x1e,0xe,1:128 CONFIG2H~2~10=0x1e,0xc,1:64 CONFIG2H~2~11=0x1e,0xa,1:32 CONFIG2H~2~12=0x1e,0x8,1:16 CONFIG2H~2~13=0x1e,0x6,1:8 CONFIG2H~2~14=0x1e,0x4,1:4 CONFIG2H~2~15=0x1e,0x2,1:2 CONFIG2H~2~16=0x1e,0x0,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=PBADEN,0x2,PortB A/D Enable CONFIG3H~3=LPT1OSC,0x4,Low Power Timer1 Osc enable CONFIG3H~4=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RB3 CONFIG3H~2~1=0x2,0x2,PORTB<4:0> configured as analog inputs on RESET CONFIG3H~2~2=0x2,0x0,PORTB<4:0> configured as digital I/O on RESET CONFIG3H~3~1=0x4,0x4,Enabled CONFIG3H~3~2=0x4,0x0,Disabled CONFIG3H~4~1=0x80,0x80,MCLR Enabled,RE3 Disabled CONFIG3H~4~2=0x80,0x0,MCLR Disabled,RE3 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=XINST,0x40,Extended Instruction Set Enable bit CONFIG4L~4=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x40,0x40,Enabled CONFIG4L~3~2=0x40,0x0,Disabled CONFIG4L~4~1=0x80,0x80,Disabled CONFIG4L~4~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-01FFF CONFIG5L~2=CP_1,0x2,Code Protect 02000-03FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x0,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x0,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPB,0x40,Code Protect Boot CONFIG5H~2=CPD,0x80,Data EEPROM Code Protect CONFIG5H~1~1=0x40,0x40,Disabled CONFIG5H~1~2=0x40,0x0,Enabled CONFIG5H~2~1=0x80,0x80,Disabled CONFIG5H~2~2=0x80,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-01FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 02000-03FFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x0,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x0,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTC,0x20,Config. Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTD,0x80,Data EEPROM Write Protect CONFIG6H~1~1=0x20,0x20,Disabled CONFIG6H~1~2=0x20,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x80,0x80,Disabled CONFIG6H~3~2=0x80,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-01FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 02000-03FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x0,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x0,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F4458] pgmmem=0x0 ~pgmmem=0x5fff cfgmem=0x300000 ~cfgmem=0x30000d userid=0x200000 ~userid=0x200007 eedata=0x0 ~eedata=0xff devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0x2a20 configslots=14 0x300000=CONFIG1L 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000a=CONFIG6L 0x30000b=CONFIG6H 0x30000c=CONFIG7L 0x30000d=CONFIG7H CONFIG1L_unused=0x0 CONFIG1L~1=PLLDIV,0x7,96MHz PLL Prescaler CONFIG1L~2=CPUDIV,0x18,CPU System Clock Postscaler CONFIG1L~3=USBPLL,0x20,Full-Speed USB Clock Source Selection CONFIG1L~1~1=0x7,0x7,Divide by 12 (48MHz input) CONFIG1L~1~2=0x7,0x6,Divide by 10 (40MHz input) CONFIG1L~1~3=0x7,0x5,Divide by 6 (24MHz input) CONFIG1L~1~4=0x7,0x4,Divide by 5 (20MHz input) CONFIG1L~1~5=0x7,0x3,Divide by 4 (16MHz input) CONFIG1L~1~6=0x7,0x2,Divide by 3 (12MHz input) CONFIG1L~1~7=0x7,0x1,Divide by 2 (8MHz input) CONFIG1L~1~8=0x7,0x0,No Divide (4MHz input) CONFIG1L~2~1=0x18,0x18,[OSC1/OSC2 Src: /4][96MHz PLL Src: /6] CONFIG1L~2~2=0x18,0x10,[OSC1/OSC2 Src: /3][96MHz PLL Src: /4] CONFIG1L~2~3=0x18,0x8,[OSC1/OSC2 Src: /2][96MHz PLL Src: /3] CONFIG1L~2~4=0x18,0x0,[OSC1/OSC2 Src: /1][96MHz PLL Src: /2] CONFIG1L~3~1=0x20,0x20,Clock src from 96MHz PLL/2 CONFIG1L~3~2=0x20,0x0,Clock src from OSC1/OSC2 CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xf,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xe,0xe,HS: HS+PLL, USB-HS CONFIG1H~1~2=0xe,0xc,HS: USB-HS CONFIG1H~1~3=0xf,0xb,INTOSC: USB-HS CONFIG1H~1~4=0xf,0xa,INTOSC: USB-XT CONFIG1H~1~5=0xf,0x9,INTOSC: INTOSC+CLK0{RA6}, USB-EC CONFIG1H~1~6=0xf,0x8,INTOSC: INTOSC+RA6, USB-EC CONFIG1H~1~7=0xf,0x7,EC: EC+PLL, EC+PLL+CLKO{RA6}, USB-EC CONFIG1H~1~8=0xf,0x6,EC: EC+PLL, EC+PLL+RA6, USB-EC CONFIG1H~1~9=0xf,0x5,EC: EC+CLKO{RA6}, USB-EC CONFIG1H~1~10=0xf,0x4,EC: EC+RA6, USB-EC CONFIG1H~1~11=0xe,0x2,XT: XT+PLL, USB-XT CONFIG1H~1~12=0xe,0x0,XT: USB-XT CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~4=VREGEN,0x20,USB Voltage Regulator CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x8,4.2V CONFIG2L~3~4=0x18,0x0,4.5V CONFIG2L~4~1=0x20,0x20,Enabled CONFIG2L~4~2=0x20,0x0,Disabled CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1e,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1e,0x1e,1:32768 CONFIG2H~2~2=0x1e,0x1c,1:16384 CONFIG2H~2~3=0x1e,0x1a,1:8192 CONFIG2H~2~4=0x1e,0x18,1:4096 CONFIG2H~2~5=0x1e,0x16,1:2048 CONFIG2H~2~6=0x1e,0x14,1:1024 CONFIG2H~2~7=0x1e,0x12,1:512 CONFIG2H~2~8=0x1e,0x10,1:256 CONFIG2H~2~9=0x1e,0xe,1:128 CONFIG2H~2~10=0x1e,0xc,1:64 CONFIG2H~2~11=0x1e,0xa,1:32 CONFIG2H~2~12=0x1e,0x8,1:16 CONFIG2H~2~13=0x1e,0x6,1:8 CONFIG2H~2~14=0x1e,0x4,1:4 CONFIG2H~2~15=0x1e,0x2,1:2 CONFIG2H~2~16=0x1e,0x0,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=PBADEN,0x2,PortB A/D Enable CONFIG3H~3=LPT1OSC,0x4,Low Power Timer1 Osc enable CONFIG3H~4=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RB3 CONFIG3H~2~1=0x2,0x2,PORTB<4:0> configured as analog inputs on RESET CONFIG3H~2~2=0x2,0x0,PORTB<4:0> configured as digital I/O on RESET CONFIG3H~3~1=0x4,0x4,Enabled CONFIG3H~3~2=0x4,0x0,Disabled CONFIG3H~4~1=0x80,0x80,MCLR Enabled,RE3 Disabled CONFIG3H~4~2=0x80,0x0,MCLR Disabled,RE3 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=ENICPORT,0x20,Dedicated In-Circuit Port {ICD/ICSP} CONFIG4L~4=XINST,0x40,Extended Instruction Set Enable bit CONFIG4L~5=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x20,0x20,Enabled CONFIG4L~3~2=0x20,0x0,Disabled CONFIG4L~4~1=0x40,0x40,Enabled CONFIG4L~4~2=0x40,0x0,Disabled CONFIG4L~5~1=0x80,0x80,Disabled CONFIG4L~5~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-01FFF CONFIG5L~2=CP_1,0x2,Code Protect 02000-03FFF CONFIG5L~3=CP_2,0x4,Code Protect 04000-05FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x0,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x0,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x0,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPB,0x40,Code Protect Boot CONFIG5H~2=CPD,0x80,Data EE Read Protect CONFIG5H~1~1=0x40,0x40,Disabled CONFIG5H~1~2=0x40,0x0,Enabled CONFIG5H~2~1=0x80,0x80,Disabled CONFIG5H~2~2=0x80,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-01FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 02000-03FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 04000-05FFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x0,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x0,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x0,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTC,0x20,Config. Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTD,0x80,Data EE Write Protect CONFIG6H~1~1=0x20,0x20,Disabled CONFIG6H~1~2=0x20,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x80,0x80,Disabled CONFIG6H~3~2=0x80,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-01FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 02000-03FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 04000-05FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x0,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x0,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x0,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F44J10] pgmmem=0x0 ~pgmmem=0x3FF7 cfgmem=0x3ff8 ~cfgmem=0x3fff userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0xf5f devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x1D20 configslots=8 0x3ff8=CONFIG1L 0x3ff9=CONFIG1H 0x3ffa=CONFIG2L 0x3ffb=CONFIG2H 0x3ffc=CONFIG3L 0x3ffd=CONFIG3H 0x3ffe= 0x3fff= CONFIG1L_unused=0x00 CONFIG1L~1=WDTEN,0x01,Watchdog Timer Enable CONFIG1L~2=STVREN,0x20,Stack Overflow Reset Enable CONFIG1L~3=ENHCPU,0x40,Enhanced CPU Enable CONFIG1L~4=BACKBUG,0x80,Background Debug CONFIG1L~1~1=0x01,0x01,Enabled CONFIG1L~1~2=0x01,0x00,Disabled CONFIG1L~2~1=0x20,0x20,Enabled CONFIG1L~2~2=0x20,0x00,Disabled CONFIG1L~3~1=0x40,0x40,Enabled CONFIG1L~3~2=0x40,0x00,Disabled CONFIG1L~4~1=0x80,0x80,Disabled CONFIG1L~4~2=0x80,0x00,Enabled CONFIG1H_unused=0x00 CONFIG1H~1=CP_0,0x4,Code Protect Enable CONFIG1H~2=SIGN,0x8,Config Word Signature Bit CONFIG1H~3=FNOP_0,0xF0,Force NOP CONFIG1H~1~1=0x4,0x4,Disabled CONFIG1H~1~2=0x4,0x00,Enabled CONFIG1H~2~1=0x8,0x8,Bulk erase of memory not conducated CONFIG1H~2~2=0x8,0x0,Bulk erase of memory area complete CONFIG1H~3~1=0xF0,0xF0,NOPd CONFIG2L_unused=0x00 CONFIG2L~1=FOSC,0x03,Oscillator CONFIG2L~2=FOSC2,0x04,Default/Reset System Clock Select CONFIG2L~3=FCMEN,0x40,Fail Safe Monitor Clock Enable CONFIG2L~4=IESO,0x80,Internal External Switch Over Enable CONFIG2L~1~1=0x03,0x03,EC OSC with software PLL and CLKOUT on OSC2 CONFIG2L~1~2=0x03,0x02,EC OSC with CLKOUT on OSC2 CONFIG2L~1~3=0x03,0x01,HS OSC with software PLL CONFIG2L~1~4=0x03,0x00,HS OSC CONFIG2L~2~1=0x04,0x04,Clock Select by FOSC CONFIG2L~2~2=0x04,0x00,INTRC enabled CONFIG2L~3~1=0x40,0x40,Enabled CONFIG2L~3~2=0x40,0x00,Disabled CONFIG2L~4~1=0x80,0x80,Enabled CONFIG2L~4~2=0x80,0x00,Disabled CONFIG2H_unused=0x00 CONFIG2H~1=WDTPS,0x0f,Watchdog Timer Postscale CONFIG2H~2=FNOP_1,0xF0,Force NOP CONFIG2H~1~1=0x000f,0x000f,1:32,768 CONFIG2H~1~2=0x000f,0x000e,1:16,384 CONFIG2H~1~3=0x000f,0x000d,1:8,192 CONFIG2H~1~4=0x000f,0x000c,1:4,096 CONFIG2H~1~5=0x000f,0x000b,1:2,048 CONFIG2H~1~6=0x000f,0x000a,1:1,024 CONFIG2H~1~7=0x000f,0x0009,1:512 CONFIG2H~1~8=0x000f,0x0008,1:256 CONFIG2H~1~9=0x000f,0x0007,1:128 CONFIG2H~1~10=0x000f,0x0006,1:64 CONFIG2H~1~11=0x000f,0x0005,1:32 CONFIG2H~1~12=0x000f,0x0004,1:16 CONFIG2H~1~13=0x000f,0x0003,1:8 CONFIG2H~1~14=0x000f,0x0002,1:4 CONFIG2H~1~15=0x000f,0x0001,1:2 CONFIG2H~1~16=0x000f,0x0000,1:1 CONFIG2H~2~1=0xF0,0xF0,NOPd CONFIG3L_unused=0x00 CONFIG3H_unused=0x00 CONFIG3H~1=CCP2MX,0x01,CCP2 Mux CONFIG3H~2=FNOP_2,0xF0,Force NOP CONFIG3H~1~1=0x01,0x01,CCP2 I/O Muxed with RC1 CONFIG3H~1~2=0x01,0x00,CCP2 I/O Muxed with RB3 CONFIG3H~2~1=0xF0,0xF0,NOPd erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F44K20] pgmmem=0x0 ~pgmmem=0x3FFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0xff devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x2080 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000a= 0x30000b= 0x30000c= 0x30000d= CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xC,0xC,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xE,0xA,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xF,0x5,EC-Port on RA6 CONFIG1H~1~8=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xF,0x3,0011 EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xF,0x2,HS CONFIG1H~1~11=0xF,0x1,XT CONFIG1H~1~12=0xF,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x08,4.2V CONFIG2L~3~4=0x18,0x00,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=PBADEN,0x2,PortB A/D Enable CONFIG3H~3=LPT1OSC,0x04,Low Power Timer1 Osc enable CONFIG3H~4=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RB3 CONFIG3H~2~1=0x2,0x2,PORTB<4:0> configured as analog inputs on RESET CONFIG3H~2~2=0x2,0x0,PORTB<4:0> configured as digital I/O on RESET CONFIG3H~3~1=0x04,0x04,Enabled CONFIG3H~3~2=0x04,0x00,Disabled CONFIG3H~4~1=0x80,0x80,MCLR Enabled,RE3 Disabled CONFIG3H~4~2=0x80,0x00,MCLR Disabled,RE3 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=ENHCPU,0x40,Extended CPU Enable CONFIG4L~4=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x40,0x40,Enabled CONFIG4L~3~2=0x40,0x00,Disabled CONFIG4L~4~1=0x80,0x80,Disabled CONFIG4L~4~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-01FFF CONFIG5L~2=CP_1,0x2,Code Protect 02000-03FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EEPROM Code Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F4523] pgmmem=0x0 ~pgmmem=0x7fff cfgmem=0x300000 ~cfgmem=0x30000d userid=0x200000 ~userid=0x200007 eedata=0x0 ~eedata=0xff devid=0x3ffffe ~devid=0x3fffff idmask=0xfff0 id=0x1090 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000a=CONFIG6L 0x30000b=CONFIG6H 0x30000c=CONFIG7L 0x30000d=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xf,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xc,0xc,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xe,0xa,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xf,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xf,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xf,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xf,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xf,0x5,EC-Port on RA6 CONFIG1H~1~8=0xf,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xf,0x3,0011 EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xf,0x2,HS CONFIG1H~1~11=0xf,0x1,XT CONFIG1H~1~12=0xf,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x8,4.2V CONFIG2L~3~4=0x18,0x0,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1e,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1e,0x1e,1:32768 CONFIG2H~2~2=0x1e,0x1c,1:16384 CONFIG2H~2~3=0x1e,0x1a,1:8192 CONFIG2H~2~4=0x1e,0x18,1:4096 CONFIG2H~2~5=0x1e,0x16,1:2048 CONFIG2H~2~6=0x1e,0x14,1:1024 CONFIG2H~2~7=0x1e,0x12,1:512 CONFIG2H~2~8=0x1e,0x10,1:256 CONFIG2H~2~9=0x1e,0xe,1:128 CONFIG2H~2~10=0x1e,0xc,1:64 CONFIG2H~2~11=0x1e,0xa,1:32 CONFIG2H~2~12=0x1e,0x8,1:16 CONFIG2H~2~13=0x1e,0x6,1:8 CONFIG2H~2~14=0x1e,0x4,1:4 CONFIG2H~2~15=0x1e,0x2,1:2 CONFIG2H~2~16=0x1e,0x0,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=PBADEN,0x2,PortB A/D Enable CONFIG3H~3=LPT1OSC,0x4,Low Power Timer1 Osc enable CONFIG3H~4=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RB3 CONFIG3H~2~1=0x2,0x2,PORTB<4:0> configured as analog inputs on RESET CONFIG3H~2~2=0x2,0x0,PORTB<4:0> configured as digital I/O on RESET CONFIG3H~3~1=0x4,0x4,Enabled CONFIG3H~3~2=0x4,0x0,Disabled CONFIG3H~4~1=0x80,0x80,MCLR Enabled,RE3 Disabled CONFIG3H~4~2=0x80,0x0,MCLR Disabled,RE3 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=XINST,0x40,Extended Instruction Set Enable bit CONFIG4L~4=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x40,0x40,Enabled CONFIG4L~3~2=0x40,0x0,Disabled CONFIG4L~4~1=0x80,0x80,Disabled CONFIG4L~4~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-01FFF CONFIG5L~2=CP_1,0x2,Code Protect 02000-03FFF CONFIG5L~3=CP_2,0x4,Code Protect 04000-05FFF CONFIG5L~4=CP_3,0x8,Code Protect 06000-07FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x0,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x0,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x0,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x0,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPB,0x40,Code Protect Boot CONFIG5H~2=CPD,0x80,Data EEPROM Code Protect CONFIG5H~1~1=0x40,0x40,Disabled CONFIG5H~1~2=0x40,0x0,Enabled CONFIG5H~2~1=0x80,0x80,Disabled CONFIG5H~2~2=0x80,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-01FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 02000-03FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 04000-05FFF CONFIG6L~4=WRT_3,0x8,Table Write Protect 06000-07FFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x0,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x0,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x0,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x0,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTC,0x20,Config. Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTD,0x80,Data EEPROM Write Protect CONFIG6H~1~1=0x20,0x20,Disabled CONFIG6H~1~2=0x20,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x80,0x80,Disabled CONFIG6H~3~2=0x80,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-01FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 02000-03FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 04000-05FFF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 06000-07FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x0,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x0,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x0,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x0,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F4553] pgmmem=0x0 ~pgmmem=0x7fff cfgmem=0x300000 ~cfgmem=0x30000d userid=0x200000 ~userid=0x200007 eedata=0x0 ~eedata=0xff devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0x2a00 configslots=14 0x300000=CONFIG1L 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000a=CONFIG6L 0x30000b=CONFIG6H 0x30000c=CONFIG7L 0x30000d=CONFIG7H CONFIG1L_unused=0x0 CONFIG1L~1=PLLDIV,0x7,96MHz PLL Prescaler CONFIG1L~2=CPUDIV,0x18,CPU System Clock Postscaler CONFIG1L~3=USBPLL,0x20,Full-Speed USB Clock Source Selection CONFIG1L~1~1=0x7,0x7,Divide by 12 (48MHz input) CONFIG1L~1~2=0x7,0x6,Divide by 10 (40MHz input) CONFIG1L~1~3=0x7,0x5,Divide by 6 (24MHz input) CONFIG1L~1~4=0x7,0x4,Divide by 5 (20MHz input) CONFIG1L~1~5=0x7,0x3,Divide by 4 (16MHz input) CONFIG1L~1~6=0x7,0x2,Divide by 3 (12MHz input) CONFIG1L~1~7=0x7,0x1,Divide by 2 (8MHz input) CONFIG1L~1~8=0x7,0x0,No Divide (4MHz input) CONFIG1L~2~1=0x18,0x18,[OSC1/OSC2 Src: /4][96MHz PLL Src: /6] CONFIG1L~2~2=0x18,0x10,[OSC1/OSC2 Src: /3][96MHz PLL Src: /4] CONFIG1L~2~3=0x18,0x8,[OSC1/OSC2 Src: /2][96MHz PLL Src: /3] CONFIG1L~2~4=0x18,0x0,[OSC1/OSC2 Src: /1][96MHz PLL Src: /2] CONFIG1L~3~1=0x20,0x20,Clock src from 96MHz PLL/2 CONFIG1L~3~2=0x20,0x0,Clock src from OSC1/OSC2 CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xf,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xe,0xe,HS: HS+PLL, USB-HS CONFIG1H~1~2=0xe,0xc,HS: USB-HS CONFIG1H~1~3=0xf,0xb,INTOSC: USB-HS CONFIG1H~1~4=0xf,0xa,INTOSC: USB-XT CONFIG1H~1~5=0xf,0x9,INTOSC: INTOSC+CLK0{RA6}, USB-EC CONFIG1H~1~6=0xf,0x8,INTOSC: INTOSC+RA6, USB-EC CONFIG1H~1~7=0xf,0x7,EC: EC+PLL, EC+PLL+CLKO{RA6}, USB-EC CONFIG1H~1~8=0xf,0x6,EC: EC+PLL, EC+PLL+RA6, USB-EC CONFIG1H~1~9=0xf,0x5,EC: EC+CLKO{RA6}, USB-EC CONFIG1H~1~10=0xf,0x4,EC: EC+RA6, USB-EC CONFIG1H~1~11=0xe,0x2,XT: XT+PLL, USB-XT CONFIG1H~1~12=0xe,0x0,XT: USB-XT CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~4=VREGEN,0x20,USB Voltage Regulator CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x8,4.2V CONFIG2L~3~4=0x18,0x0,4.5V CONFIG2L~4~1=0x20,0x20,Enabled CONFIG2L~4~2=0x20,0x0,Disabled CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1e,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1e,0x1e,1:32768 CONFIG2H~2~2=0x1e,0x1c,1:16384 CONFIG2H~2~3=0x1e,0x1a,1:8192 CONFIG2H~2~4=0x1e,0x18,1:4096 CONFIG2H~2~5=0x1e,0x16,1:2048 CONFIG2H~2~6=0x1e,0x14,1:1024 CONFIG2H~2~7=0x1e,0x12,1:512 CONFIG2H~2~8=0x1e,0x10,1:256 CONFIG2H~2~9=0x1e,0xe,1:128 CONFIG2H~2~10=0x1e,0xc,1:64 CONFIG2H~2~11=0x1e,0xa,1:32 CONFIG2H~2~12=0x1e,0x8,1:16 CONFIG2H~2~13=0x1e,0x6,1:8 CONFIG2H~2~14=0x1e,0x4,1:4 CONFIG2H~2~15=0x1e,0x2,1:2 CONFIG2H~2~16=0x1e,0x0,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=PBADEN,0x2,PortB A/D Enable CONFIG3H~3=LPT1OSC,0x4,Low Power Timer1 Osc enable CONFIG3H~4=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RB3 CONFIG3H~2~1=0x2,0x2,PORTB<4:0> configured as analog inputs on RESET CONFIG3H~2~2=0x2,0x0,PORTB<4:0> configured as digital I/O on RESET CONFIG3H~3~1=0x4,0x4,Enabled CONFIG3H~3~2=0x4,0x0,Disabled CONFIG3H~4~1=0x80,0x80,MCLR Enabled,RE3 Disabled CONFIG3H~4~2=0x80,0x0,MCLR Disabled,RE3 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=ENICPORT,0x20,Dedicated In-Circuit Port {ICD/ICSP} CONFIG4L~4=XINST,0x40,Extended Instruction Set Enable bit CONFIG4L~5=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x20,0x20,Enabled CONFIG4L~3~2=0x20,0x0,Disabled CONFIG4L~4~1=0x40,0x40,Enabled CONFIG4L~4~2=0x40,0x0,Disabled CONFIG4L~5~1=0x80,0x80,Disabled CONFIG4L~5~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-01FFF CONFIG5L~2=CP_1,0x2,Code Protect 02000-03FFF CONFIG5L~3=CP_2,0x4,Code Protect 04000-05FFF CONFIG5L~4=CP_3,0x8,Code Protect 06000-07FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x0,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x0,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x0,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x0,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPB,0x40,Code Protect Boot CONFIG5H~2=CPD,0x80,Data EE Read Protect CONFIG5H~1~1=0x40,0x40,Disabled CONFIG5H~1~2=0x40,0x0,Enabled CONFIG5H~2~1=0x80,0x80,Disabled CONFIG5H~2~2=0x80,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-01FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 02000-03FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 04000-05FFF CONFIG6L~4=WRT_3,0x8,Table Write Protect 06000-07FFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x0,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x0,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x0,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x0,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTC,0x20,Config. Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTD,0x80,Data EE Write Protect CONFIG6H~1~1=0x20,0x20,Disabled CONFIG6H~1~2=0x20,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x80,0x80,Disabled CONFIG6H~3~2=0x80,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-01FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 02000-03FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 04000-05FFF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 06000-07FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x0,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x0,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x0,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x0,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE_24xx05 prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F4586] pgmmem=0x0 ~pgmmem=0xBFFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata= ~eedata= devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x0E20 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000a= 0x30000b= 0x30000c= 0x30000d= CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xC,0xC,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xE,0xA,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xF,0x5,EC-Port on RA6 CONFIG1H~1~8=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xF,0x3,EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xF,0x2,HS CONFIG1H~1~11=0xF,0x1,XT CONFIG1H~1~12=0xF,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x08,4.2V CONFIG2L~3~4=0x18,0x00,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=PBADEN,0x2,PortB A/D Enable CONFIG3H~2=LPT1OSC,0x04,Low Power Timer1 Osc enable CONFIG3H~3=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x2,0x2,PORTB<4> and <1:0> configured as analog inputs on RESET CONFIG3H~1~2=0x2,0x0,PORTB<4> and <1:0> configured as digital I/O on RESET CONFIG3H~2~1=0x04,0x04,Enabled CONFIG3H~2~2=0x04,0x00,Disabled CONFIG3H~3~1=0x80,0x80,MCLR Enabled,RE3 Disabled CONFIG3H~3~2=0x80,0x00,MCLR Disabled, RE3 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=ENHCPU,0x40,Extended CPU Enable CONFIG4L~4=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x40,0x40,Enabled CONFIG4L~3~2=0x40,0x00,Disabled CONFIG4L~4~1=0x80,0x80,Disabled CONFIG4L~4~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-03FFF CONFIG5L~2=CP_1,0x2,Code Protect 04000-07FFF CONFIG5L~3=CP_2,0x4,Code Protect 08000-0BFFF CONFIG5L~4=CP_3,0x8,Code Protect 0C000-0FFFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EE Read Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F45J10] pgmmem=0x0 ~pgmmem=0x7FF7 cfgmem=0x7ff8 ~cfgmem=0x7fff userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0xf5f devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x1C20 configslots=8 0x7ff8=CONFIG1L 0x7ff9=CONFIG1H 0x7ffa=CONFIG2L 0x7ffb=CONFIG2H 0x7ffc=CONFIG3L 0x7ffd=CONFIG3H 0x7ffe= 0x7fff= CONFIG1L_unused=0x00 CONFIG1L~1=WDTEN,0x01,Watchdog Timer Enable CONFIG1L~2=STVREN,0x20,Stack Overflow Reset Enable CONFIG1L~3=ENHCPU,0x40,Enhanced CPU Enable CONFIG1L~4=BACKBUG,0x80,Background Debug CONFIG1L~1~1=0x01,0x01,Enabled CONFIG1L~1~2=0x01,0x00,Disabled CONFIG1L~2~1=0x20,0x20,Enabled CONFIG1L~2~2=0x20,0x00,Disabled CONFIG1L~3~1=0x40,0x40,Enabled CONFIG1L~3~2=0x40,0x00,Disabled CONFIG1L~4~1=0x80,0x80,Disabled CONFIG1L~4~2=0x80,0x00,Enabled CONFIG1H_unused=0x00 CONFIG1H~1=CP_0,0x4,Code Protect Enable CONFIG1H~2=FNOP_0,0xF0,Force NOP CONFIG1H~3=SIGN,0x8,Config Word Signature Bit CONFIG1H~1~1=0x4,0x4,Disabled CONFIG1H~1~2=0x4,0x00,Enabled CONFIG1H~2~1=0xF0,0xF0,NOPd CONFIG1H~3~1=0x8,0x8,Bulk erase of memory not conducated CONFIG1H~3~2=0x8,0x0,Bulk erase of memory area complete CONFIG2L_unused=0x00 CONFIG2L~1=FOSC,0x03,Oscillator CONFIG2L~2=FOSC2,0x04,Default/Reset System Clock Select CONFIG2L~3=FCMEN,0x40,Fail Safe Monitor Clock Enable CONFIG2L~4=IESO,0x80,Internal External Switch Over Enable CONFIG2L~1~1=0x03,0x03,EC OSC with software PLL and CLKOUT on OSC2 CONFIG2L~1~2=0x03,0x02,EC OSC with CLKOUT on OSC2 CONFIG2L~1~3=0x03,0x01,HS OSC with software PLL CONFIG2L~1~4=0x03,0x00,HS OSC CONFIG2L~2~1=0x04,0x04,Clock Select by FOSC CONFIG2L~2~2=0x04,0x00,INTRC enabled CONFIG2L~3~1=0x40,0x40,Enabled CONFIG2L~3~2=0x40,0x00,Disabled CONFIG2L~4~1=0x80,0x80,Enabled CONFIG2L~4~2=0x80,0x00,Disabled CONFIG2H_unused=0x00 CONFIG2H~1=WDTPS,0x0f,Watchdog Timer Postscale CONFIG2H~2=FNOP_1,0xF0,Force NOP CONFIG2H~1~1=0x000f,0x000f,1:32,768 CONFIG2H~1~2=0x000f,0x000e,1:16,384 CONFIG2H~1~3=0x000f,0x000d,1:8,192 CONFIG2H~1~4=0x000f,0x000c,1:4,096 CONFIG2H~1~5=0x000f,0x000b,1:2,048 CONFIG2H~1~6=0x000f,0x000a,1:1,024 CONFIG2H~1~7=0x000f,0x0009,1:512 CONFIG2H~1~8=0x000f,0x0008,1:256 CONFIG2H~1~9=0x000f,0x0007,1:128 CONFIG2H~1~10=0x000f,0x0006,1:64 CONFIG2H~1~11=0x000f,0x0005,1:32 CONFIG2H~1~12=0x000f,0x0004,1:16 CONFIG2H~1~13=0x000f,0x0003,1:8 CONFIG2H~1~14=0x000f,0x0002,1:4 CONFIG2H~1~15=0x000f,0x0001,1:2 CONFIG2H~1~16=0x000f,0x0000,1:1 CONFIG2H~2~1=0xF0,0xF0,NOPd CONFIG3L_unused=0x00 CONFIG3H_unused=0x00 CONFIG3H~1=CCP2MX,0x01,CCP2 Mux CONFIG3H~2=FNOP_2,0xF0,Force NOP CONFIG3H~1~1=0x01,0x01,CCP2 I/O Muxed with RC1 CONFIG3H~1~2=0x01,0x00,CCP2 I/O Muxed with RB3 CONFIG3H~2~1=0xF0,0xF0,NOPd erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F45K20] pgmmem=0x0 ~pgmmem=0x7FFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0xff devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x2040 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000a= 0x30000b= 0x30000c= 0x30000d= CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xC,0xC,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xE,0xA,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xF,0x5,EC-Port on RA6 CONFIG1H~1~8=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xF,0x3,0011 EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xF,0x2,HS CONFIG1H~1~11=0xF,0x1,XT CONFIG1H~1~12=0xF,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x08,4.2V CONFIG2L~3~4=0x18,0x00,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=PBADEN,0x2,PortB A/D Enable CONFIG3H~3=LPT1OSC,0x04,Low Power Timer1 Osc enable CONFIG3H~4=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RB3 CONFIG3H~2~1=0x2,0x2,PORTB<4:0> configured as analog inputs on RESET CONFIG3H~2~2=0x2,0x0,PORTB<4:0> configured as digital I/O on RESET CONFIG3H~3~1=0x04,0x04,Enabled CONFIG3H~3~2=0x04,0x00,Disabled CONFIG3H~4~1=0x80,0x80,MCLR Enabled,RE3 Disabled CONFIG3H~4~2=0x80,0x00,MCLR Disabled,RE3 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=ENHCPU,0x40,Extended CPU Enable CONFIG4L~4=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x40,0x40,Enabled CONFIG4L~3~2=0x40,0x00,Disabled CONFIG4L~4~1=0x80,0x80,Disabled CONFIG4L~4~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-01FFF CONFIG5L~2=CP_1,0x2,Code Protect 02000-03FFF CONFIG5L~3=CP_2,0x4,Code Protect 04000-05FFF CONFIG5L~4=CP_3,0x8,Code Protect 06000-07FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EEPROM Code Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F4681] pgmmem=0x0 ~pgmmem=0xFFFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata= ~eedata= devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x0E00 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000a= 0x30000b= 0x30000c= 0x30000d= CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xC,0xC,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xA,0xA,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xF,0x5,EC-Port on RA6 CONFIG1H~1~8=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xF,0x3,EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xF,0x2,HS CONFIG1H~1~11=0xF,0x1,XT CONFIG1H~1~12=0xF,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x08,4.2V CONFIG2L~3~4=0x18,0x00,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=PBADEN,0x2,PortB A/D Enable CONFIG3H~2=LPT1OSC,0x04,Low Power Timer1 Osc enable CONFIG3H~3=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x2,0x2,PORTB<4> and <1:0> configured as analog inputs on RESET CONFIG3H~1~2=0x2,0x0,PORTB<4> and <1:0> configured as digital I/O on RESET CONFIG3H~2~1=0x04,0x04,Enabled CONFIG3H~2~2=0x04,0x00,Disabled CONFIG3H~3~1=0x80,0x80,MCLR Enabled,RE3 Disabled CONFIG3H~3~2=0x80,0x00,MCLR Disabled, RE3 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=ENHCPU,0x40,Extended CPU Enable CONFIG4L~4=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x40,0x40,Enabled CONFIG4L~3~2=0x40,0x00,Disabled CONFIG4L~4~1=0x80,0x80,Disabled CONFIG4L~4~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-03FFF CONFIG5L~2=CP_1,0x2,Code Protect 04000-07FFF CONFIG5L~3=CP_2,0x4,Code Protect 08000-0BFFF CONFIG5L~4=CP_3,0x8,Code Protect 0C000-0FFFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EE Read Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F46K20] pgmmem=0x0 ~pgmmem=0xFFFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata=0x00 ~eedata=0x3ff devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x20C0 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000a= 0x30000b= 0x30000c= 0x30000d= CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xC,0xC,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xE,0xA,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xF,0x5,EC-Port on RA6 CONFIG1H~1~8=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xF,0x3,0011 EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xF,0x2,HS CONFIG1H~1~11=0xF,0x1,XT CONFIG1H~1~12=0xF,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,1.8V CONFIG2L~3~2=0x18,0x10,2.2V CONFIG2L~3~3=0x18,0x08,2.7V CONFIG2L~3~4=0x18,0x00,3.0V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=PBADEN,0x2,PortB A/D Enable CONFIG3H~3=LPT1OSC,0x04,Low Power Timer1 Osc enable CONFIG3H~4=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RB3 CONFIG3H~2~1=0x2,0x2,PORTB<4:0> configured as analog inputs on RESET CONFIG3H~2~2=0x2,0x0,PORTB<4:0> configured as digital I/O on RESET CONFIG3H~3~1=0x04,0x04,Enabled CONFIG3H~3~2=0x04,0x00,Disabled CONFIG3H~4~1=0x80,0x80,MCLR Enabled,RE3 Disabled CONFIG3H~4~2=0x80,0x00,MCLR Disabled, RE3 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=ENHCPU,0x40,Extended CPU Enable CONFIG4L~4=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x40,0x40,Enabled CONFIG4L~3~2=0x40,0x00,Disabled CONFIG4L~4~1=0x80,0x80,Disabled CONFIG4L~4~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-03FFF CONFIG5L~2=CP_1,0x2,Code Protect 04000-07FFF CONFIG5L~3=CP_2,0x4,Code Protect 08000-0BFFF CONFIG5L~4=CP_3,0x8,Code Protect 0C000-0FFFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EEPROM Code Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F66J60] pgmmem=0x0 ~pgmmem=0x0fff7 cfgmem=0x0fff8 ~cfgmem=0x0ffff userid= ~userid= eedata=0x00 ~eedata=0xf5f devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x1800 configslots=8 0x0fff8=CONFIG1L 0x0fff9=CONFIG1H 0x0fffa=CONFIG2L 0x0fffb=CONFIG2H 0x0fffc=CONFIG3L 0x0fffd=CONFIG3H 0x0fffe=CONFIG4L 0x0ffff=CONFIG4H CONFIG1L_unused=0x00 CONFIG1L~1=WDTEN,0x01,Watchdog Timer Enable CONFIG1L~2=STVREN,0x20,Stack Overflow Reset Enable CONFIG1L~3=ENHCPU,0x40,Enhanced CPU Enable CONFIG1L~4=BACKBUG,0x80,Background Debug CONFIG1L~1~1=0x01,0x01,Enabled CONFIG1L~1~2=0x01,0x00,Disabled CONFIG1L~2~1=0x20,0x20,Enabled CONFIG1L~2~2=0x20,0x00,Disabled CONFIG1L~3~1=0x40,0x40,Enabled CONFIG1L~3~2=0x40,0x00,Disabled CONFIG1L~4~1=0x80,0x80,Disabled CONFIG1L~4~2=0x80,0x00,Enabled CONFIG1H_unused=0x00 CONFIG1H~1=CP_0,0x4,Code Protect 000000-00FFFF CONFIG1H~1~1=0x4,0x4,Disabled CONFIG1H~1~2=0x4,0x00,Enabled CONFIG2L_unused=0x00 CONFIG2L~1=FOSC,0x07,Oscillator CONFIG2L~2=FCMEN,0x40,Fail Safe Monitor Clock Enable CONFIG2L~3=IESO,0x80,Internal External Switch Over Enable CONFIG2L~1~1=0x07,0x07,OSC1/OSC2 as Primary, EC+PLL Osc with CLKOUT Function CONFIG2L~1~2=0x07,0x06,OSC1/OSC2 as Primary, EC Osc with CLKOUT Function CONFIG2L~1~3=0x07,0x05,OSC1/OSC2 as primary, HS+PLL Osc CONFIG2L~1~4=0x07,0x04,OSC1/OSC2 as primary, HS Osc CONFIG2L~1~5=0x07,0x03,INTOSC as Primary, EC+PLL Osc with CLKOUT CONFIG2L~1~6=0x07,0x02,INTOSC as Primary, EC Osc with CLKOUT CONFIG2L~1~7=0x07,0x01,INTOSC as Primary, HS+PLL Osc CONFIG2L~1~8=0x07,0x00,INTOSC as Primary, HS Osc CONFIG2L~2~1=0x40,0x40,Enabled CONFIG2L~2~2=0x40,0x00,Disabled CONFIG2L~3~1=0x80,0x80,Enabled CONFIG2L~3~2=0x80,0x00,Disabled CONFIG2H_unused=0x00 CONFIG2H~1=WDTPS,0x0f,Watchdog Timer Postscale CONFIG2H~1~1=0x000f,0x000f,1:32,768 CONFIG2H~1~2=0x000f,0x000e,1:16,384 CONFIG2H~1~3=0x000f,0x000d,1:8,192 CONFIG2H~1~4=0x000f,0x000c,1:4,096 CONFIG2H~1~5=0x000f,0x000b,1:2,048 CONFIG2H~1~6=0x000f,0x000a,1:1,024 CONFIG2H~1~7=0x000f,0x0009,1:512 CONFIG2H~1~8=0x000f,0x0008,1:256 CONFIG2H~1~9=0x000f,0x0007,1:128 CONFIG2H~1~10=0x000f,0x0006,1:64 CONFIG2H~1~11=0x000f,0x0005,1:32 CONFIG2H~1~12=0x000f,0x0004,1:16 CONFIG2H~1~13=0x000f,0x0003,1:8 CONFIG2H~1~14=0x000f,0x0002,1:4 CONFIG2H~1~15=0x000f,0x0001,1:2 CONFIG2H~1~16=0x000f,0x0000,1:1 CONFIG3L_unused=0x00 CONFIG3H_unused=0x00 CONFIG3H~1=ETHLED,0x04,Ethernet LED Enable CONFIG3H~1~1=0x04,0x04,LEDA/LEDB On RA0/RA1 With Ethernet, RA0/AN0 Without CONFIG3H~1~2=0x04,0x00,RA0 On RA0/AN0), RA1 On RA1/AN1 CONFIG4L_unused=0x00 CONFIG4H_unused=0x00 erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F66J65] pgmmem=0x0 ~pgmmem=0x17ff7 cfgmem=0x17ff8 ~cfgmem=0x17fff userid= ~userid= eedata=0x00 ~eedata=0xf5f devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x1F00 configslots=8 0x17ff8=CONFIG1L 0x17ff9=CONFIG1H 0x17ffa=CONFIG2L 0x17ffb=CONFIG2H 0x17ffc=CONFIG3L 0x17ffd=CONFIG3H 0x17ffe=CONFIG4L 0x17fff=CONFIG4H CONFIG1L_unused=0x00 CONFIG1L~1=WDTEN,0x01,Watchdog Timer Enable CONFIG1L~2=STVREN,0x20,Stack Overflow Reset Enable CONFIG1L~3=ENHCPU,0x40,Enhanced CPU Enable CONFIG1L~4=BACKBUG,0x80,Background Debug CONFIG1L~1~1=0x01,0x01,Enabled CONFIG1L~1~2=0x01,0x00,Disabled CONFIG1L~2~1=0x20,0x20,Enabled CONFIG1L~2~2=0x20,0x00,Disabled CONFIG1L~3~1=0x40,0x40,Enabled CONFIG1L~3~2=0x40,0x00,Disabled CONFIG1L~4~1=0x80,0x80,Disabled CONFIG1L~4~2=0x80,0x00,Enabled CONFIG1H_unused=0x00 CONFIG1H~1=CP_0,0x4,Code Protect 000000-017FFF CONFIG1H~1~1=0x4,0x4,Disabled CONFIG1H~1~2=0x4,0x00,Enabled CONFIG2L_unused=0x00 CONFIG2L~1=FOSC,0x07,Oscillator CONFIG2L~2=FCMEN,0x40,Fail Safe Monitor Clock Enable CONFIG2L~3=IESO,0x80,Internal External Switch Over Enable CONFIG2L~1~1=0x07,0x07,OSC1/OSC2 as Primary, EC+PLL Osc with CLKOUT Function CONFIG2L~1~2=0x07,0x06,OSC1/OSC2 as Primary, EC Osc with CLKOUT Function CONFIG2L~1~3=0x07,0x05,OSC1/OSC2 as primary, HS+PLL Osc CONFIG2L~1~4=0x07,0x04,OSC1/OSC2 as primary, HS Osc CONFIG2L~1~5=0x07,0x03,INTOSC as Primary, EC+PLL Osc with CLKOUT CONFIG2L~1~6=0x07,0x02,INTOSC as Primary, EC Osc with CLKOUT CONFIG2L~1~7=0x07,0x01,INTOSC as Primary, HS+PLL Osc CONFIG2L~1~8=0x07,0x00,INTOSC as Primary, HS Osc CONFIG2L~2~1=0x40,0x40,Enabled CONFIG2L~2~2=0x40,0x00,Disabled CONFIG2L~3~1=0x80,0x80,Enabled CONFIG2L~3~2=0x80,0x00,Disabled CONFIG2H_unused=0x00 CONFIG2H~1=WDTPS,0x0f,Watchdog Timer Postscale CONFIG2H~1~1=0x000f,0x000f,1:32,768 CONFIG2H~1~2=0x000f,0x000e,1:16,384 CONFIG2H~1~3=0x000f,0x000d,1:8,192 CONFIG2H~1~4=0x000f,0x000c,1:4,096 CONFIG2H~1~5=0x000f,0x000b,1:2,048 CONFIG2H~1~6=0x000f,0x000a,1:1,024 CONFIG2H~1~7=0x000f,0x0009,1:512 CONFIG2H~1~8=0x000f,0x0008,1:256 CONFIG2H~1~9=0x000f,0x0007,1:128 CONFIG2H~1~10=0x000f,0x0006,1:64 CONFIG2H~1~11=0x000f,0x0005,1:32 CONFIG2H~1~12=0x000f,0x0004,1:16 CONFIG2H~1~13=0x000f,0x0003,1:8 CONFIG2H~1~14=0x000f,0x0002,1:4 CONFIG2H~1~15=0x000f,0x0001,1:2 CONFIG2H~1~16=0x000f,0x0000,1:1 CONFIG3L_unused=0x00 CONFIG3H_unused=0x00 CONFIG3H~1=ETHLED,0x04,Ethernet LED Enable CONFIG3H~1~1=0x04,0x04,LEDA/LEDB On RA0/RA1 With Ethernet, RA0/AN0 Without CONFIG3H~1~2=0x04,0x00,RA0 On RA0/AN0), RA1 On RA1/AN1 CONFIG4L_unused=0x00 CONFIG4H_unused=0x00 erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F87J60] pgmmem=0x0 ~pgmmem=0x1fff7 cfgmem=0x1fff8 ~cfgmem=0x1ffff userid= ~userid= eedata=0x00 ~eedata=0xf5f devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x1F60 configslots=8 0x1fff8=CONFIG1L 0x1fff9=CONFIG1H 0x1fffa=CONFIG2L 0x1fffb=CONFIG2H 0x1fffc=CONFIG3L 0x1fffd=CONFIG3H 0x1fffe=CONFIG4L 0x1ffff=CONFIG4H CONFIG1L_unused=0x00 CONFIG1L~1=WDTEN,0x01,Watchdog Timer Enable CONFIG1L~2=STVREN,0x20,Stack Overflow Reset Enable CONFIG1L~3=ENHCPU,0x40,Enhanced CPU Enable CONFIG1L~4=BACKBUG,0x80,Background Debug CONFIG1L~1~1=0x01,0x01,Enabled CONFIG1L~1~2=0x01,0x00,Disabled CONFIG1L~2~1=0x20,0x20,Enabled CONFIG1L~2~2=0x20,0x00,Disabled CONFIG1L~3~1=0x40,0x40,Enabled CONFIG1L~3~2=0x40,0x00,Disabled CONFIG1L~4~1=0x80,0x80,Disabled CONFIG1L~4~2=0x80,0x00,Enabled CONFIG1H_unused=0x00 CONFIG1H~1=CP_0,0x4,Code Protect 000000-01FFFF CONFIG1H~1~1=0x4,0x4,Disabled CONFIG1H~1~2=0x4,0x00,Enabled CONFIG2L_unused=0x00 CONFIG2L~1=FOSC,0x07,Oscillator CONFIG2L~2=FCMEN,0x40,Fail Safe Monitor Clock Enable CONFIG2L~3=IESO,0x80,Internal External Switch Over Enable CONFIG2L~1~1=0x07,0x07,OSC1/OSC2 as Primary, EC+PLL Osc with CLKOUT Function CONFIG2L~1~2=0x07,0x06,OSC1/OSC2 as Primary, EC Osc with CLKOUT Function CONFIG2L~1~3=0x07,0x05,OSC1/OSC2 as primary, HS+PLL Osc CONFIG2L~1~4=0x07,0x04,OSC1/OSC2 as primary, HS Osc CONFIG2L~1~5=0x07,0x03,INTOSC as Primary, EC+PLL Osc with CLKOUT CONFIG2L~1~6=0x07,0x02,INTOSC as Primary, EC Osc with CLKOUT CONFIG2L~1~7=0x07,0x01,INTOSC as Primary, HS+PLL Osc CONFIG2L~1~8=0x07,0x00,INTOSC as Primary, HS Osc CONFIG2L~2~1=0x40,0x40,Enabled CONFIG2L~2~2=0x40,0x00,Disabled CONFIG2L~3~1=0x80,0x80,Enabled CONFIG2L~3~2=0x80,0x00,Disabled CONFIG2H_unused=0x00 CONFIG2H~1=WDTPS,0x0f,Watchdog Timer Postscale CONFIG2H~1~1=0x000f,0x000f,1:32,768 CONFIG2H~1~2=0x000f,0x000e,1:16,384 CONFIG2H~1~3=0x000f,0x000d,1:8,192 CONFIG2H~1~4=0x000f,0x000c,1:4,096 CONFIG2H~1~5=0x000f,0x000b,1:2,048 CONFIG2H~1~6=0x000f,0x000a,1:1,024 CONFIG2H~1~7=0x000f,0x0009,1:512 CONFIG2H~1~8=0x000f,0x0008,1:256 CONFIG2H~1~9=0x000f,0x0007,1:128 CONFIG2H~1~10=0x000f,0x0006,1:64 CONFIG2H~1~11=0x000f,0x0005,1:32 CONFIG2H~1~12=0x000f,0x0004,1:16 CONFIG2H~1~13=0x000f,0x0003,1:8 CONFIG2H~1~14=0x000f,0x0002,1:4 CONFIG2H~1~15=0x000f,0x0001,1:2 CONFIG2H~1~16=0x000f,0x0000,1:1 CONFIG3L_unused=0x00 CONFIG3H_unused=0x00 CONFIG3H~1=CCP2MX,0x01,CCP2 Mux CONFIG3H~2=ECCPXM,0x02,ECCP Mux CONFIG3H~3=ETHLED,0x04,Ethernet LED Enable CONFIG3H~1~1=0x01,0x01,ECCP2 I/O Muxed With RC1 CONFIG3H~1~2=0x01,0x00,ECCP2 IP Muxed With RE7 CONFIG3H~2~1=0x02,0x02,P1B/P1C On RE6/RE5, P3B/P3C On RE4/RE3 CONFIG3H~2~2=0x02,0x00,P1B/P1C On RH7/RH6, P3B/P3C Onto RH5/RH4 CONFIG3H~3~1=0x04,0x04,LEDA/LEDB On RA0/RA1 With Ethernet, RA0/AN0 Without CONFIG3H~3~2=0x04,0x00,RA0 On RA0/AN0), RA1 On RA1/AN1 CONFIG4L_unused=0x00 CONFIG4H_unused=0x00 erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F96J60] pgmmem=0x0 ~pgmmem=0x0fff7 cfgmem=0x0fff8 ~cfgmem=0x0ffff userid= ~userid= eedata=0x00 ~eedata=0xf5f devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x1840 configslots=8 0x0fff8=CONFIG1L 0x0fff9=CONFIG1H 0x0fffa=CONFIG2L 0x0fffb=CONFIG2H 0x0fffc=CONFIG3L 0x0fffd=CONFIG3H 0x0fffe=CONFIG4L 0x0ffff=CONFIG4H CONFIG1L_unused=0x00 CONFIG1L~1=WDTEN,0x01,Watchdog Timer Enable CONFIG1L~2=STVREN,0x20,Stack Overflow Reset Enable CONFIG1L~3=ENHCPU,0x40,Enhanced CPU Enable CONFIG1L~4=BACKBUG,0x80,Background Debug CONFIG1L~1~1=0x01,0x01,Enabled CONFIG1L~1~2=0x01,0x00,Disabled CONFIG1L~2~1=0x20,0x20,Enabled CONFIG1L~2~2=0x20,0x00,Disabled CONFIG1L~3~1=0x40,0x40,Enabled CONFIG1L~3~2=0x40,0x00,Disabled CONFIG1L~4~1=0x80,0x80,Disabled CONFIG1L~4~2=0x80,0x00,Enabled CONFIG1H_unused=0x00 CONFIG1H~1=CP_0,0x4,Code Protect 000000-00FFFF CONFIG1H~1~1=0x4,0x4,Disabled CONFIG1H~1~2=0x4,0x00,Enabled CONFIG2L_unused=0x00 CONFIG2L~1=FOSC,0x07,Oscillator CONFIG2L~2=FCMEN,0x40,Fail Safe Monitor Clock Enable CONFIG2L~3=IESO,0x80,Internal External Switch Over Enable CONFIG2L~1~1=0x07,0x07,OSC1/OSC2 as Primary, EC+PLL Osc with CLKOUT Function CONFIG2L~1~2=0x07,0x06,OSC1/OSC2 as Primary, EC Osc with CLKOUT Function CONFIG2L~1~3=0x07,0x05,OSC1/OSC2 as primary, HS+PLL Osc CONFIG2L~1~4=0x07,0x04,OSC1/OSC2 as primary, HS Osc CONFIG2L~1~5=0x07,0x03,INTOSC as Primary, EC+PLL Osc with CLKOUT CONFIG2L~1~6=0x07,0x02,INTOSC as Primary, EC Osc with CLKOUT CONFIG2L~1~7=0x07,0x01,INTOSC as Primary, HS+PLL Osc CONFIG2L~1~8=0x07,0x00,INTOSC as Primary, HS Osc CONFIG2L~2~1=0x40,0x40,Enabled CONFIG2L~2~2=0x40,0x00,Disabled CONFIG2L~3~1=0x80,0x80,Enabled CONFIG2L~3~2=0x80,0x00,Disabled CONFIG2H_unused=0x00 CONFIG2H~1=WDTPS,0x0f,Watchdog Timer Postscale CONFIG2H~1~1=0x000f,0x000f,1:32,768 CONFIG2H~1~2=0x000f,0x000e,1:16,384 CONFIG2H~1~3=0x000f,0x000d,1:8,192 CONFIG2H~1~4=0x000f,0x000c,1:4,096 CONFIG2H~1~5=0x000f,0x000b,1:2,048 CONFIG2H~1~6=0x000f,0x000a,1:1,024 CONFIG2H~1~7=0x000f,0x0009,1:512 CONFIG2H~1~8=0x000f,0x0008,1:256 CONFIG2H~1~9=0x000f,0x0007,1:128 CONFIG2H~1~10=0x000f,0x0006,1:64 CONFIG2H~1~11=0x000f,0x0005,1:32 CONFIG2H~1~12=0x000f,0x0004,1:16 CONFIG2H~1~13=0x000f,0x0003,1:8 CONFIG2H~1~14=0x000f,0x0002,1:4 CONFIG2H~1~15=0x000f,0x0001,1:2 CONFIG2H~1~16=0x000f,0x0000,1:1 CONFIG3L_unused=0x00 CONFIG3L~1=EASHFT,0x08,External Address Bus Shift Enable CONFIG3L~2=EMB,0x30,External Memory Bus Address Mode CONFIG3L~3=BW,0x40,Data Bus Width Select CONFIG3L~4=WAIT,0x80,External Bus Wait Enable CONFIG3L~1~1=0x08,0x08,Enabled CONFIG3L~1~2=0x08,0x00,Disabled CONFIG3L~2~1=0x30,0x30,Microcontroller Mode, External Bus Disabled CONFIG3L~2~2=0x30,0x20,Extended Microcontroller Mode, 12-Bit Addr CONFIG3L~2~3=0x30,0x10,Extended Microcontroller Mode, 16-Bit Addr CONFIG3L~2~4=0x30,0x00,Extended Microcontroller Mode, 20-Bit Addr CONFIG3L~3~1=0x40,0x40,16-Bit CONFIG3L~3~2=0x40,0x00,8-Bit CONFIG3L~4~1=0x80,0x80,Ignore MEMCON.WAIT, Device Will Not Wait CONFIG3L~4~2=0x80,0x00,Observe MEMCON.WAIT CONFIG3H_unused=0x00 CONFIG3H~1=CCP2MX,0x01,CCP2 Mux CONFIG3H~2=ECCPXM,0x02,ECCP Mux CONFIG3H~3=ETHLED,0x04,Ethernet LED Enable CONFIG3H~1~1=0x01,0x01,ECCP2 I/O Muxed With RC1 CONFIG3H~1~2=0x01,0x00,ECCP2 IP Muxed With RE7 (or RB3 in Ext Micro Mode) CONFIG3H~2~1=0x02,0x02,P1B/P1C On RE6/RE5, P3B/P3C On RE4/RE3 CONFIG3H~2~2=0x02,0x00,P1B/P1C On RH7/RH6, P3B/P3C Onto RH5/RH4 CONFIG3H~3~1=0x04,0x04,LEDA/LEDB On RA0/RA1 With Ethernet, RA0/AN0 Without CONFIG3H~3~2=0x04,0x00,RA0 On RA0/AN0), RA1 On RA1/AN1 CONFIG4L_unused=0x00 CONFIG4H_unused=0x00 erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F96J65] pgmmem=0x0 ~pgmmem=0x17ff7 cfgmem=0x17ff8 ~cfgmem=0x17fff userid= ~userid= eedata=0x00 ~eedata=0xf5f devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x1F80 configslots=8 0x17ff8=CONFIG1L 0x17ff9=CONFIG1H 0x17ffa=CONFIG2L 0x17ffb=CONFIG2H 0x17ffc=CONFIG3L 0x17ffd=CONFIG3H 0x17ffe=CONFIG4L 0x17fff=CONFIG4H CONFIG1L_unused=0x00 CONFIG1L~1=WDTEN,0x01,Watchdog Timer Enable CONFIG1L~2=STVREN,0x20,Stack Overflow Reset Enable CONFIG1L~3=ENHCPU,0x40,Enhanced CPU Enable CONFIG1L~4=BACKBUG,0x80,Background Debug CONFIG1L~1~1=0x01,0x01,Enabled CONFIG1L~1~2=0x01,0x00,Disabled CONFIG1L~2~1=0x20,0x20,Enabled CONFIG1L~2~2=0x20,0x00,Disabled CONFIG1L~3~1=0x40,0x40,Enabled CONFIG1L~3~2=0x40,0x00,Disabled CONFIG1L~4~1=0x80,0x80,Disabled CONFIG1L~4~2=0x80,0x00,Enabled CONFIG1H_unused=0x00 CONFIG1H~1=CP_0,0x4,Code Protect 000000-017FFF CONFIG1H~1~1=0x4,0x4,Disabled CONFIG1H~1~2=0x4,0x00,Enabled CONFIG2L_unused=0x00 CONFIG2L~1=FOSC,0x07,Oscillator CONFIG2L~2=FCMEN,0x40,Fail Safe Monitor Clock Enable CONFIG2L~3=IESO,0x80,Internal External Switch Over Enable CONFIG2L~1~1=0x07,0x07,OSC1/OSC2 as Primary, EC+PLL Osc with CLKOUT Function CONFIG2L~1~2=0x07,0x06,OSC1/OSC2 as Primary, EC Osc with CLKOUT Function CONFIG2L~1~3=0x07,0x05,OSC1/OSC2 as primary, HS+PLL Osc CONFIG2L~1~4=0x07,0x04,OSC1/OSC2 as primary, HS Osc CONFIG2L~1~5=0x07,0x03,INTOSC as Primary, EC+PLL Osc with CLKOUT CONFIG2L~1~6=0x07,0x02,INTOSC as Primary, EC Osc with CLKOUT CONFIG2L~1~7=0x07,0x01,INTOSC as Primary, HS+PLL Osc CONFIG2L~1~8=0x07,0x00,INTOSC as Primary, HS Osc CONFIG2L~2~1=0x40,0x40,Enabled CONFIG2L~2~2=0x40,0x00,Disabled CONFIG2L~3~1=0x80,0x80,Enabled CONFIG2L~3~2=0x80,0x00,Disabled CONFIG2H_unused=0x00 CONFIG2H~1=WDTPS,0x0f,Watchdog Timer Postscale CONFIG2H~1~1=0x000f,0x000f,1:32,768 CONFIG2H~1~2=0x000f,0x000e,1:16,384 CONFIG2H~1~3=0x000f,0x000d,1:8,192 CONFIG2H~1~4=0x000f,0x000c,1:4,096 CONFIG2H~1~5=0x000f,0x000b,1:2,048 CONFIG2H~1~6=0x000f,0x000a,1:1,024 CONFIG2H~1~7=0x000f,0x0009,1:512 CONFIG2H~1~8=0x000f,0x0008,1:256 CONFIG2H~1~9=0x000f,0x0007,1:128 CONFIG2H~1~10=0x000f,0x0006,1:64 CONFIG2H~1~11=0x000f,0x0005,1:32 CONFIG2H~1~12=0x000f,0x0004,1:16 CONFIG2H~1~13=0x000f,0x0003,1:8 CONFIG2H~1~14=0x000f,0x0002,1:4 CONFIG2H~1~15=0x000f,0x0001,1:2 CONFIG2H~1~16=0x000f,0x0000,1:1 CONFIG3L_unused=0x00 CONFIG3L~1=EASHFT,0x08,External Address Bus Shift Enable CONFIG3L~2=EMB,0x30,External Memory Bus Address Mode CONFIG3L~3=BW,0x40,Data Bus Width Select CONFIG3L~4=WAIT,0x80,External Bus Wait Enable CONFIG3L~1~1=0x08,0x08,Enabled CONFIG3L~1~2=0x08,0x00,Disabled CONFIG3L~2~1=0x30,0x30,Microcontroller Mode, External Bus Disabled CONFIG3L~2~2=0x30,0x20,Extended Microcontroller Mode, 12-Bit Addr CONFIG3L~2~3=0x30,0x10,Extended Microcontroller Mode, 16-Bit Addr CONFIG3L~2~4=0x30,0x00,Extended Microcontroller Mode, 20-Bit Addr CONFIG3L~3~1=0x40,0x40,16-Bit CONFIG3L~3~2=0x40,0x00,8-Bit CONFIG3L~4~1=0x80,0x80,Ignore MEMCON.WAIT, Device Will Not Wait CONFIG3L~4~2=0x80,0x00,Observe MEMCON.WAIT CONFIG3H_unused=0x00 CONFIG3H~1=CCP2MX,0x01,CCP2 Mux CONFIG3H~2=ECCPXM,0x02,ECCP Mux CONFIG3H~3=ETHLED,0x04,Ethernet LED Enable CONFIG3H~1~1=0x01,0x01,ECCP2 I/O Muxed With RC1 CONFIG3H~1~2=0x01,0x00,ECCP2 IP Muxed With RE7 (or RB3 in Ext Micro Mode) CONFIG3H~2~1=0x02,0x02,P1B/P1C On RE6/RE5, P3B/P3C On RE4/RE3 CONFIG3H~2~2=0x02,0x00,P1B/P1C On RH7/RH6, P3B/P3C Onto RH5/RH4 CONFIG3H~3~1=0x04,0x04,LEDA/LEDB On RA0/RA1 With Ethernet, RA0/AN0 Without CONFIG3H~3~2=0x04,0x00,RA0 On RA0/AN0), RA1 On RA1/AN1 CONFIG4L_unused=0x00 CONFIG4H_unused=0x00 erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F97J60] pgmmem=0x0 ~pgmmem=0x1fff7 cfgmem=0x1fff8 ~cfgmem=0x1ffff userid= ~userid= eedata=0x00 ~eedata=0xf5f devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x1FA0 configslots=8 0x1fff8=CONFIG1L 0x1fff9=CONFIG1H 0x1fffa=CONFIG2L 0x1fffb=CONFIG2H 0x1fffc=CONFIG3L 0x1fffd=CONFIG3H 0x1fffe=CONFIG4L 0x1ffff=CONFIG4H CONFIG1L_unused=0x00 CONFIG1L~1=WDTEN,0x01,Watchdog Timer Enable CONFIG1L~2=STVREN,0x20,Stack Overflow Reset Enable CONFIG1L~3=ENHCPU,0x40,Enhanced CPU Enable CONFIG1L~4=BACKBUG,0x80,Background Debug CONFIG1L~1~1=0x01,0x01,Enabled CONFIG1L~1~2=0x01,0x00,Disabled CONFIG1L~2~1=0x20,0x20,Enabled CONFIG1L~2~2=0x20,0x00,Disabled CONFIG1L~3~1=0x40,0x40,Enabled CONFIG1L~3~2=0x40,0x00,Disabled CONFIG1L~4~1=0x80,0x80,Disabled CONFIG1L~4~2=0x80,0x00,Enabled CONFIG1H_unused=0x00 CONFIG1H~1=CP_0,0x4,Code Protect 000000-01FFFF CONFIG1H~1~1=0x4,0x4,Disabled CONFIG1H~1~2=0x4,0x00,Enabled CONFIG2L_unused=0x00 CONFIG2L~1=FOSC,0x07,Oscillator CONFIG2L~2=FCMEN,0x40,Fail Safe Monitor Clock Enable CONFIG2L~3=IESO,0x80,Internal External Switch Over Enable CONFIG2L~1~1=0x07,0x07,OSC1/OSC2 as Primary, EC+PLL Osc with CLKOUT Function CONFIG2L~1~2=0x07,0x06,OSC1/OSC2 as Primary, EC Osc with CLKOUT Function CONFIG2L~1~3=0x07,0x05,OSC1/OSC2 as primary, HS+PLL Osc CONFIG2L~1~4=0x07,0x04,OSC1/OSC2 as primary, HS Osc CONFIG2L~1~5=0x07,0x03,INTOSC as Primary, EC+PLL Osc with CLKOUT CONFIG2L~1~6=0x07,0x02,INTOSC as Primary, EC Osc with CLKOUT CONFIG2L~1~7=0x07,0x01,INTOSC as Primary, HS+PLL Osc CONFIG2L~1~8=0x07,0x00,INTOSC as Primary, HS Osc CONFIG2L~2~1=0x40,0x40,Enabled CONFIG2L~2~2=0x40,0x00,Disabled CONFIG2L~3~1=0x80,0x80,Enabled CONFIG2L~3~2=0x80,0x00,Disabled CONFIG2H_unused=0x00 CONFIG2H~1=WDTPS,0x0f,Watchdog Timer Postscale CONFIG2H~1~1=0x000f,0x000f,1:32,768 CONFIG2H~1~2=0x000f,0x000e,1:16,384 CONFIG2H~1~3=0x000f,0x000d,1:8,192 CONFIG2H~1~4=0x000f,0x000c,1:4,096 CONFIG2H~1~5=0x000f,0x000b,1:2,048 CONFIG2H~1~6=0x000f,0x000a,1:1,024 CONFIG2H~1~7=0x000f,0x0009,1:512 CONFIG2H~1~8=0x000f,0x0008,1:256 CONFIG2H~1~9=0x000f,0x0007,1:128 CONFIG2H~1~10=0x000f,0x0006,1:64 CONFIG2H~1~11=0x000f,0x0005,1:32 CONFIG2H~1~12=0x000f,0x0004,1:16 CONFIG2H~1~13=0x000f,0x0003,1:8 CONFIG2H~1~14=0x000f,0x0002,1:4 CONFIG2H~1~15=0x000f,0x0001,1:2 CONFIG2H~1~16=0x000f,0x0000,1:1 CONFIG3L_unused=0x00 CONFIG3L~1=EASHFT,0x08,External Address Bus Shift Enable CONFIG3L~2=EMB,0x30,External Memory Bus Address Mode CONFIG3L~3=BW,0x40,Data Bus Width Select CONFIG3L~4=WAIT,0x80,External Bus Wait Enable CONFIG3L~1~1=0x08,0x08,Enabled CONFIG3L~1~2=0x08,0x00,Disabled CONFIG3L~2~1=0x30,0x30,Microcontroller Mode, External Bus Disabled CONFIG3L~2~2=0x30,0x20,Extended Microcontroller Mode, 12-Bit Addr CONFIG3L~2~3=0x30,0x10,Extended Microcontroller Mode, 16-Bit Addr CONFIG3L~2~4=0x30,0x00,Extended Microcontroller Mode, 20-Bit Addr CONFIG3L~3~1=0x40,0x40,16-Bit CONFIG3L~3~2=0x40,0x00,8-Bit CONFIG3L~4~1=0x80,0x80,Ignore MEMCON.WAIT, Device Will Not Wait CONFIG3L~4~2=0x80,0x00,Observe MEMCON.WAIT CONFIG3H_unused=0x00 CONFIG3H~1=CCP2MX,0x01,CCP2 Mux CONFIG3H~2=ECCPXM,0x02,ECCP Mux CONFIG3H~3=ETHLED,0x04,Ethernet LED Enable CONFIG3H~1~1=0x01,0x01,ECCP2 I/O Muxed With RC1 CONFIG3H~1~2=0x01,0x00,ECCP2 IP Muxed With RE7 (or RB3 in Ext Micro Mode) CONFIG3H~2~1=0x02,0x02,P1B/P1C On RE6/RE5, P3B/P3C On RE4/RE3 CONFIG3H~2~2=0x02,0x00,P1B/P1C On RH7/RH6, P3B/P3C Onto RH5/RH4 CONFIG3H~3~1=0x04,0x04,LEDA/LEDB On RA0/RA1 With Ethernet, RA0/AN0 Without CONFIG3H~3~2=0x04,0x00,RA0 On RA0/AN0), RA1 On RA1/AN1 CONFIG4L_unused=0x00 CONFIG4H_unused=0x00 erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F13K20] pgmmem=0x0 ~pgmmem=0xfff cfgmem=0x300000 ~cfgmem=0x30000d userid=0x200000 ~userid=0x200007 eedata=0x0 ~eedata=0xff devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0x4f40 configslots=14 0x300000=CONFIG1L 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000a=CONFIG6L 0x30000b=CONFIG6H 0x30000c=CONFIG7L 0x30000d=CONFIG7H CONFIG1L_unused=0x0 CONFIG1L~1=CPUDIV,0x18,CPU System Clock Selection bits CONFIG1L~2=USBDIV,0x20,USB Clock Selection bit CONFIG1L~1~1=0x18,0x18,CPU system clock divided by 4 CONFIG1L~1~2=0x18,0x10,CPU system clock divided by 3 CONFIG1L~1~3=0x18,0x8,CPU system clock divided by 2 CONFIG1L~1~4=0x18,0x0,No CPU system clock divide CONFIG1L~2~1=0x20,0x20,USB clock comes from the OSC1/OSC2 divided by 2 CONFIG1L~2~2=0x20,0x0,USB clock comes directly from the OSC1/OSC2 Oscillator block; no divide CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xf,Oscillator CONFIG1H~2=PLLEN,0x10,4 X PLL Enable bit CONFIG1H~3=PCLKEN,0x20,Primary Clock Enable bit CONFIG1H~4=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~5=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xc,0xc,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xe,0xa,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xf,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xf,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xf,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xf,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xf,0x5,EC-Port on RA6 CONFIG1H~1~8=0xf,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xf,0x3,0011 EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xf,0x2,HS CONFIG1H~1~11=0xf,0x1,XT CONFIG1H~1~12=0xf,0x0,LP CONFIG1H~2~1=0x10,0x10,Oscillator multiplied by 4 CONFIG1H~2~2=0x10,0x0,Oscillator used directly CONFIG1H~3~1=0x20,0x20,Primary Clock enabled CONFIG1H~3~2=0x20,0x0,Primary Clock disabled CONFIG1H~4~1=0x40,0x0,Disabled CONFIG1H~4~2=0x40,0x40,Enabled CONFIG1H~5~1=0x80,0x0,Disabled CONFIG1H~5~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=nPWRTEN,0x1,Power Up Timer CONFIG2L~2=BOREN,0x6,Brown Out Detect CONFIG2L~3=BORV,0x18,Brown Out Voltage CONFIG2L~4=VREGEN,0x20,Voltage Regulator Enable bit CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,1.9V CONFIG2L~3~2=0x18,0x10,2.2V CONFIG2L~3~3=0x18,0x8,2.7V CONFIG2L~3~4=0x18,0x0,3.0V CONFIG2L~4~1=0x20,0x0,Voltage Regulator is disabled CONFIG2L~4~2=0x20,0x20,Voltage Regulator is enabled CONFIG2H_unused=0x0 CONFIG2H~1=WDTEN,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1e,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1e,0x1e,1:32768 CONFIG2H~2~2=0x1e,0x1c,1:16384 CONFIG2H~2~3=0x1e,0x1a,1:8192 CONFIG2H~2~4=0x1e,0x18,1:4096 CONFIG2H~2~5=0x1e,0x16,1:2048 CONFIG2H~2~6=0x1e,0x14,1:1024 CONFIG2H~2~7=0x1e,0x12,1:512 CONFIG2H~2~8=0x1e,0x10,1:256 CONFIG2H~2~9=0x1e,0xe,1:128 CONFIG2H~2~10=0x1e,0xc,1:64 CONFIG2H~2~11=0x1e,0xa,1:32 CONFIG2H~2~12=0x1e,0x8,1:16 CONFIG2H~2~13=0x1e,0x6,1:8 CONFIG2H~2~14=0x1e,0x4,1:4 CONFIG2H~2~15=0x1e,0x2,1:2 CONFIG2H~2~16=0x1e,0x0,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=HFOFST,0x8,HFINTOSC Fast Start-up CONFIG3H~2=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x8,0x8,HFINTOSC starts clocking the CPU without waiting for the oscillator to stabilize CONFIG3H~1~2=0x8,0x0,The system clock is held off until the HFINTOSC is stable CONFIG3H~2~1=0x80,0x80,MCLR Enabled,RE3 Disabled CONFIG3H~2~2=0x80,0x0,MCLR Disabled,RE3 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVREN,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=BBSIZ,0x8,Boot BLock Size Select bit CONFIG4L~4=XINST,0x40,Extended Instruction Set Enable bit CONFIG4L~5=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x8,0x8,1 kW boot block size CONFIG4L~3~2=0x8,0x0,512 W boot block size CONFIG4L~4~1=0x40,0x40,Enabled CONFIG4L~4~2=0x40,0x0,Disabled CONFIG4L~5~1=0x80,0x80,Disabled CONFIG4L~5~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-01FFF CONFIG5L~2=CP_1,0x2,Code Protect 02000-03FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x0,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x0,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPB,0x40,Code Protect Boot CONFIG5H~2=CPD,0x80,Data EEPROM Code Protect CONFIG5H~1~1=0x40,0x40,Disabled CONFIG5H~1~2=0x40,0x0,Enabled CONFIG5H~2~1=0x80,0x80,Disabled CONFIG5H~2~2=0x80,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-01FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 02000-03FFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x0,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x0,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTC,0x20,Config. Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTD,0x80,Data EEPROM Write Protect CONFIG6H~1~1=0x20,0x20,Disabled CONFIG6H~1~2=0x20,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x80,0x80,Disabled CONFIG6H~3~2=0x80,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-01FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 02000-03FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x0,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x0,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F13K22] pgmmem=0x0 ~pgmmem=0x1fff cfgmem=0x300000 ~cfgmem=0x30000d userid=0x200000 ~userid=0x200007 eedata=0x0 ~eedata=0xff devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0x4f40 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000a=CONFIG6L 0x30000b=CONFIG6H 0x30000c=CONFIG7L 0x30000d=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xf,Oscillator CONFIG1H~2=PLLEN,0x10,4 X PLL Enable bit CONFIG1H~3=PCLKEN,0x20,Primary Clock Enable bit CONFIG1H~4=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~5=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xc,0xc,11XX EXT RC-CLKOUT on OSC2 CONFIG1H~1~2=0xe,0xa,101X EC-CLKOUT on OSC2 CONFIG1H~1~3=0xf,0x9,INT RC-CLKOUT on OSC2 CONFIG1H~1~4=0xf,0x8,INT RC CONFIG1H~1~5=0xf,0x7,EXT RC CONFIG1H~1~6=0xf,0x6,EXT-RC OSC-CLKOUT on OSC2 CONFIG1H~1~7=0xf,0x5,EC CONFIG1H~1~8=0xf,0x4,EC-CLKOUT on OSC2 CONFIG1H~1~9=0xf,0x3,0011 EXT RC-CLKOUT on OSC2 CONFIG1H~1~10=0xf,0x2,HS CONFIG1H~1~11=0xf,0x1,XT CONFIG1H~1~12=0xf,0x0,LP CONFIG1H~2~1=0x10,0x10,Oscillator multiplied by 4 CONFIG1H~2~2=0x10,0x0,Oscillator used directly CONFIG1H~3~1=0x20,0x20,Primary Clock enabled CONFIG1H~3~2=0x20,0x0,Primary Clock disabled CONFIG1H~4~1=0x40,0x0,Disabled CONFIG1H~4~2=0x40,0x40,Enabled CONFIG1H~5~1=0x80,0x0,Disabled CONFIG1H~5~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=nPWRTEN,0x1,Power Up Timer CONFIG2L~2=BOREN,0x6,Brown Out Detect CONFIG2L~3=BORV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,1.9V CONFIG2L~3~2=0x18,0x10,2.2V CONFIG2L~3~3=0x18,0x8,2.7V CONFIG2L~3~4=0x18,0x0,3.0V CONFIG2H_unused=0x0 CONFIG2H~1=WDTEN,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1e,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1e,0x1e,1:32768 CONFIG2H~2~2=0x1e,0x1c,1:16384 CONFIG2H~2~3=0x1e,0x1a,1:8192 CONFIG2H~2~4=0x1e,0x18,1:4096 CONFIG2H~2~5=0x1e,0x16,1:2048 CONFIG2H~2~6=0x1e,0x14,1:1024 CONFIG2H~2~7=0x1e,0x12,1:512 CONFIG2H~2~8=0x1e,0x10,1:256 CONFIG2H~2~9=0x1e,0xe,1:128 CONFIG2H~2~10=0x1e,0xc,1:64 CONFIG2H~2~11=0x1e,0xa,1:32 CONFIG2H~2~12=0x1e,0x8,1:16 CONFIG2H~2~13=0x1e,0x6,1:8 CONFIG2H~2~14=0x1e,0x4,1:4 CONFIG2H~2~15=0x1e,0x2,1:2 CONFIG2H~2~16=0x1e,0x0,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=HFOFST,0x8,HFINTOSC Fast Start-up CONFIG3H~2=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x8,0x8,HFINTOSC starts clocking the CPU without waiting for the oscillator to stabilize CONFIG3H~1~2=0x8,0x0,The system clock is held off until the HFINTOSC is stable CONFIG3H~2~1=0x80,0x80,MCLR Enabled,RA3 Disabled CONFIG3H~2~2=0x80,0x0,MCLR Disabled,RA3 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVREN,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=BBSIZ,0x8,Boot BLock Size Select bit CONFIG4L~4=XINST,0x40,Extended Instruction Set Enable bit CONFIG4L~5=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x8,0x8,1 kW boot block size CONFIG4L~3~2=0x8,0x0,512 W boot block size CONFIG4L~4~1=0x40,0x40,Enabled CONFIG4L~4~2=0x40,0x0,Disabled CONFIG4L~5~1=0x80,0x80,Disabled CONFIG4L~5~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-0FFF CONFIG5L~2=CP_1,0x2,Code Protect 01000-01FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x0,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x0,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPB,0x40,Code Protect Boot CONFIG5H~2=CPD,0x80,Data EEPROM Code Protect CONFIG5H~1~1=0x40,0x40,Disabled CONFIG5H~1~2=0x40,0x0,Enabled CONFIG5H~2~1=0x80,0x80,Disabled CONFIG5H~2~2=0x80,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-01FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 02000-03FFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x0,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x0,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTC,0x20,Config. Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTD,0x80,Data EEPROM Write Protect CONFIG6H~1~1=0x20,0x20,Disabled CONFIG6H~1~2=0x20,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x80,0x80,Disabled CONFIG6H~3~2=0x80,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-01FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 02000-03FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x0,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x0,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F13K50] pgmmem=0x0 ~pgmmem=0x1fff cfgmem=0x300000 ~cfgmem=0x30000d userid=0x200000 ~userid=0x200007 eedata=0x0 ~eedata=0x7f devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0x4740 configslots=14 0x300000=CONFIG1L 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000a=CONFIG6L 0x30000b=CONFIG6H 0x30000c=CONFIG7L 0x30000d=CONFIG7H CONFIG1L_unused=0x0 CONFIG1L~1=CPUDIV,0x18,CPU System Clock Selection bits CONFIG1L~2=USBDIV,0x20,USB Clock Selection bit CONFIG1L~1~1=0x18,0x18,CPU system clock divided by 4 CONFIG1L~1~2=0x18,0x10,CPU system clock divided by 3 CONFIG1L~1~3=0x18,0x8,CPU system clock divided by 2 CONFIG1L~1~4=0x18,0x0,No CPU system clock divide CONFIG1L~2~1=0x20,0x20,USB clock comes from the OSC1/OSC2 divided by 2 CONFIG1L~2~2=0x20,0x0,USB clock comes directly from the OSC1/OSC2 Oscillator block; no divide CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xf,Oscillator CONFIG1H~2=PLLEN,0x10,4 X PLL Enable bit CONFIG1H~3=PCLKEN,0x20,Primary Clock Enable bit CONFIG1H~4=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~5=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xe,0xe,111X EXT RC-CLKOUT on OSC2 CONFIG1H~1~2=0xf,0xd,EC - Low CONFIG1H~1~3=0xf,0xc,EC-CLKOUT on OSC2 - Low CONFIG1H~1~4=0xf,0xb,EC - Medium CONFIG1H~1~5=0xf,0xa,EC-CLKOUT on OSC2 - Medium CONFIG1H~1~6=0xf,0x9,INT RC-CLKOUT on OSC2 CONFIG1H~1~7=0xf,0x8,INT RC CONFIG1H~1~8=0xf,0x7,EXT RC CONFIG1H~1~9=0xf,0x6,0110 EXT RC-CLKOUT on OSC2 CONFIG1H~1~10=0xf,0x5,EC - High CONFIG1H~1~11=0xf,0x4,EC-CLKOUT on OSC2 - High CONFIG1H~1~12=0xf,0x3,0011 EXT RC-CLKOUT on OSC2 CONFIG1H~1~13=0xf,0x2,HS CONFIG1H~1~14=0xf,0x1,XT CONFIG1H~1~15=0xf,0x0,LP CONFIG1H~2~1=0x10,0x10,Oscillator multiplied by 4 CONFIG1H~2~2=0x10,0x0,Oscillator used directly CONFIG1H~3~1=0x20,0x20,Primary Clock enabled CONFIG1H~3~2=0x20,0x0,Primary Clock disabled CONFIG1H~4~1=0x40,0x0,Disabled CONFIG1H~4~2=0x40,0x40,Enabled CONFIG1H~5~1=0x80,0x0,Disabled CONFIG1H~5~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=nPWRTEN,0x1,Power Up Timer CONFIG2L~2=BOREN,0x6,Brown Out Detect CONFIG2L~3=BORV,0x18,Brown Out Voltage CONFIG2L~4=Reserved,0x20,Reserved CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,1.9V CONFIG2L~3~2=0x18,0x10,2.2V CONFIG2L~3~3=0x18,0x8,2.7V CONFIG2L~3~4=0x18,0x0,3.0V CONFIG2L~4~1=0x20,0x20,Reserved CONFIG2H_unused=0x0 CONFIG2H~1=WDTEN,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1e,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1e,0x1e,1:32768 CONFIG2H~2~2=0x1e,0x1c,1:16384 CONFIG2H~2~3=0x1e,0x1a,1:8192 CONFIG2H~2~4=0x1e,0x18,1:4096 CONFIG2H~2~5=0x1e,0x16,1:2048 CONFIG2H~2~6=0x1e,0x14,1:1024 CONFIG2H~2~7=0x1e,0x12,1:512 CONFIG2H~2~8=0x1e,0x10,1:256 CONFIG2H~2~9=0x1e,0xe,1:128 CONFIG2H~2~10=0x1e,0xc,1:64 CONFIG2H~2~11=0x1e,0xa,1:32 CONFIG2H~2~12=0x1e,0x8,1:16 CONFIG2H~2~13=0x1e,0x6,1:8 CONFIG2H~2~14=0x1e,0x4,1:4 CONFIG2H~2~15=0x1e,0x2,1:2 CONFIG2H~2~16=0x1e,0x0,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=HFOFST,0x8,HFINTOSC Fast Start-up CONFIG3H~2=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x8,0x8,HFINTOSC starts clocking the CPU without waiting for the oscillator to stabilize CONFIG3H~1~2=0x8,0x0,The system clock is held off until the HFINTOSC is stable CONFIG3H~2~1=0x80,0x80,MCLR Enabled,RA3 Disabled CONFIG3H~2~2=0x80,0x0,MCLR Disabled,RA3 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVREN,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=BBSIZ,0x8,Boot BLock Size Select bit CONFIG4L~4=XINST,0x40,Extended Instruction Set Enable bit CONFIG4L~5=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x8,0x8,2 kW boot block size CONFIG4L~3~2=0x8,0x0,1 kW boot block size CONFIG4L~4~1=0x40,0x40,Enabled CONFIG4L~4~2=0x40,0x0,Disabled CONFIG4L~5~1=0x80,0x80,Disabled CONFIG4L~5~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-00FFF CONFIG5L~2=CP_1,0x2,Code Protect 01000-01FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x0,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x0,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPB,0x40,Code Protect Boot CONFIG5H~2=CPD,0x80,Data EEPROM Code Protect CONFIG5H~1~1=0x40,0x40,Disabled CONFIG5H~1~2=0x40,0x0,Enabled CONFIG5H~2~1=0x80,0x80,Disabled CONFIG5H~2~2=0x80,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-01FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 02000-03FFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x0,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x0,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTC,0x20,Config. Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTD,0x80,Data EEPROM Write Protect CONFIG6H~1~1=0x20,0x20,Disabled CONFIG6H~1~2=0x20,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x80,0x80,Disabled CONFIG6H~3~2=0x80,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-01FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 02000-03FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x0,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x0,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F14K20] pgmmem=0x0 ~pgmmem=0x1fff cfgmem=0x300000 ~cfgmem=0x30000d userid=0x200000 ~userid=0x200007 eedata=0x0 ~eedata=0xff devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0x4f20 configslots=14 0x300000=CONFIG1L 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000a=CONFIG6L 0x30000b=CONFIG6H 0x30000c=CONFIG7L 0x30000d=CONFIG7H CONFIG1L_unused=0x0 CONFIG1L~1=CPUDIV,0x18,CPU System Clock Selection bits CONFIG1L~2=USBDIV,0x20,USB Clock Selection bit CONFIG1L~1~1=0x18,0x18,CPU system clock divided by 4 CONFIG1L~1~2=0x18,0x10,CPU system clock divided by 3 CONFIG1L~1~3=0x18,0x8,CPU system clock divided by 2 CONFIG1L~1~4=0x18,0x0,No CPU system clock divide CONFIG1L~2~1=0x20,0x20,USB clock comes from the OSC1/OSC2 divided by 2 CONFIG1L~2~2=0x20,0x0,USB clock comes directly from the OSC1/OSC2 Oscillator block; no divide CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xf,Oscillator CONFIG1H~2=PLLEN,0x10,4 X PLL Enable bit CONFIG1H~3=PCLKEN,0x20,Primary Clock Enable bit CONFIG1H~4=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~5=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xc,0xc,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xe,0xa,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xf,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xf,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xf,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xf,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xf,0x5,EC-Port on RA6 CONFIG1H~1~8=0xf,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xf,0x3,0011 EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xf,0x2,HS CONFIG1H~1~11=0xf,0x1,XT CONFIG1H~1~12=0xf,0x0,LP CONFIG1H~2~1=0x10,0x10,Oscillator multiplied by 4 CONFIG1H~2~2=0x10,0x0,Oscillator used directly CONFIG1H~3~1=0x20,0x20,Primary Clock enabled CONFIG1H~3~2=0x20,0x0,Primary Clock disabled CONFIG1H~4~1=0x40,0x0,Disabled CONFIG1H~4~2=0x40,0x40,Enabled CONFIG1H~5~1=0x80,0x0,Disabled CONFIG1H~5~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=nPWRTEN,0x1,Power Up Timer CONFIG2L~2=BOREN,0x6,Brown Out Detect CONFIG2L~3=BORV,0x18,Brown Out Voltage CONFIG2L~4=VREGEN,0x20,Voltage Regulator Enable bit CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,1.9V CONFIG2L~3~2=0x18,0x10,2.2V CONFIG2L~3~3=0x18,0x8,2.7V CONFIG2L~3~4=0x18,0x0,3.0V CONFIG2L~4~1=0x20,0x0,Voltage Regulator is disabled CONFIG2L~4~2=0x20,0x20,Voltage Regulator is enabled CONFIG2H_unused=0x0 CONFIG2H~1=WDTEN,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1e,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1e,0x1e,1:32768 CONFIG2H~2~2=0x1e,0x1c,1:16384 CONFIG2H~2~3=0x1e,0x1a,1:8192 CONFIG2H~2~4=0x1e,0x18,1:4096 CONFIG2H~2~5=0x1e,0x16,1:2048 CONFIG2H~2~6=0x1e,0x14,1:1024 CONFIG2H~2~7=0x1e,0x12,1:512 CONFIG2H~2~8=0x1e,0x10,1:256 CONFIG2H~2~9=0x1e,0xe,1:128 CONFIG2H~2~10=0x1e,0xc,1:64 CONFIG2H~2~11=0x1e,0xa,1:32 CONFIG2H~2~12=0x1e,0x8,1:16 CONFIG2H~2~13=0x1e,0x6,1:8 CONFIG2H~2~14=0x1e,0x4,1:4 CONFIG2H~2~15=0x1e,0x2,1:2 CONFIG2H~2~16=0x1e,0x0,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=HFOFST,0x8,HFINTOSC Fast Start-up CONFIG3H~2=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x8,0x8,HFINTOSC starts clocking the CPU without waiting for the oscillator to stabilize CONFIG3H~1~2=0x8,0x0,The system clock is held off until the HFINTOSC is stable CONFIG3H~2~1=0x80,0x80,MCLR Enabled,RE3 Disabled CONFIG3H~2~2=0x80,0x0,MCLR Disabled,RE3 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVREN,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=BBSIZ,0x8,Boot BLock Size Select bit CONFIG4L~4=XINST,0x40,Extended Instruction Set Enable bit CONFIG4L~5=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x8,0x8,1 kW boot block size CONFIG4L~3~2=0x8,0x0,512 W boot block size CONFIG4L~4~1=0x40,0x40,Enabled CONFIG4L~4~2=0x40,0x0,Disabled CONFIG4L~5~1=0x80,0x80,Disabled CONFIG4L~5~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-01FFF CONFIG5L~2=CP_1,0x2,Code Protect 02000-03FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x0,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x0,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPB,0x40,Code Protect Boot CONFIG5H~2=CPD,0x80,Data EEPROM Code Protect CONFIG5H~1~1=0x40,0x40,Disabled CONFIG5H~1~2=0x40,0x0,Enabled CONFIG5H~2~1=0x80,0x80,Disabled CONFIG5H~2~2=0x80,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-01FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 02000-03FFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x0,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x0,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTC,0x20,Config. Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTD,0x80,Data EEPROM Write Protect CONFIG6H~1~1=0x20,0x20,Disabled CONFIG6H~1~2=0x20,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x80,0x80,Disabled CONFIG6H~3~2=0x80,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-01FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 02000-03FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x0,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x0,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F14K22] pgmmem=0x0 ~pgmmem=0x3fff cfgmem=0x300000 ~cfgmem=0x30000d userid=0x200000 ~userid=0x200007 eedata=0x0 ~eedata=0xff devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0x4f20 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000a=CONFIG6L 0x30000b=CONFIG6H 0x30000c=CONFIG7L 0x30000d=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xf,Oscillator CONFIG1H~2=PLLEN,0x10,4 X PLL Enable bit CONFIG1H~3=PCLKEN,0x20,Primary Clock Enable bit CONFIG1H~4=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~5=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xc,0xc,11XX EXT RC-CLKOUT on OSC2 CONFIG1H~1~2=0xe,0xa,101X EC-CLKOUT on OSC2 CONFIG1H~1~3=0xf,0x9,INT RC-CLKOUT on OSC2 CONFIG1H~1~4=0xf,0x8,INT RC CONFIG1H~1~5=0xf,0x7,EXT RC CONFIG1H~1~6=0xf,0x6,EXT-RC OSC-CLKOUT on OSC2 CONFIG1H~1~7=0xf,0x5,EC CONFIG1H~1~8=0xf,0x4,EC-CLKOUT on OSC2 CONFIG1H~1~9=0xf,0x3,0011 EXT RC-CLKOUT on OSC2 CONFIG1H~1~10=0xf,0x2,HS CONFIG1H~1~11=0xf,0x1,XT CONFIG1H~1~12=0xf,0x0,LP CONFIG1H~2~1=0x10,0x10,Oscillator multiplied by 4 CONFIG1H~2~2=0x10,0x0,Oscillator used directly CONFIG1H~3~1=0x20,0x20,Primary Clock enabled CONFIG1H~3~2=0x20,0x0,Primary Clock disabled CONFIG1H~4~1=0x40,0x0,Disabled CONFIG1H~4~2=0x40,0x40,Enabled CONFIG1H~5~1=0x80,0x0,Disabled CONFIG1H~5~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=nPWRTEN,0x1,Power Up Timer CONFIG2L~2=BOREN,0x6,Brown Out Detect CONFIG2L~3=BORV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,1.9V CONFIG2L~3~2=0x18,0x10,2.2V CONFIG2L~3~3=0x18,0x8,2.7V CONFIG2L~3~4=0x18,0x0,3.0V CONFIG2H_unused=0x0 CONFIG2H~1=WDTEN,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1e,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1e,0x1e,1:32768 CONFIG2H~2~2=0x1e,0x1c,1:16384 CONFIG2H~2~3=0x1e,0x1a,1:8192 CONFIG2H~2~4=0x1e,0x18,1:4096 CONFIG2H~2~5=0x1e,0x16,1:2048 CONFIG2H~2~6=0x1e,0x14,1:1024 CONFIG2H~2~7=0x1e,0x12,1:512 CONFIG2H~2~8=0x1e,0x10,1:256 CONFIG2H~2~9=0x1e,0xe,1:128 CONFIG2H~2~10=0x1e,0xc,1:64 CONFIG2H~2~11=0x1e,0xa,1:32 CONFIG2H~2~12=0x1e,0x8,1:16 CONFIG2H~2~13=0x1e,0x6,1:8 CONFIG2H~2~14=0x1e,0x4,1:4 CONFIG2H~2~15=0x1e,0x2,1:2 CONFIG2H~2~16=0x1e,0x0,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=HFOFST,0x8,HFINTOSC Fast Start-up CONFIG3H~2=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x8,0x8,HFINTOSC starts clocking the CPU without waiting for the oscillator to stabilize CONFIG3H~1~2=0x8,0x0,The system clock is held off until the HFINTOSC is stable CONFIG3H~2~1=0x80,0x80,MCLR Enabled,RA3 Disabled CONFIG3H~2~2=0x80,0x0,MCLR Disabled,RA3 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVREN,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=BBSIZ,0x8,Boot BLock Size Select bit CONFIG4L~4=XINST,0x40,Extended Instruction Set Enable bit CONFIG4L~5=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x8,0x8,2 kW boot block size CONFIG4L~3~2=0x8,0x0,1 kW boot block size CONFIG4L~4~1=0x40,0x40,Enabled CONFIG4L~4~2=0x40,0x0,Disabled CONFIG4L~5~1=0x80,0x80,Disabled CONFIG4L~5~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-01FFF CONFIG5L~2=CP_1,0x2,Code Protect 02000-03FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x0,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x0,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPB,0x40,Code Protect Boot CONFIG5H~2=CPD,0x80,Data EEPROM Code Protect CONFIG5H~1~1=0x40,0x40,Disabled CONFIG5H~1~2=0x40,0x0,Enabled CONFIG5H~2~1=0x80,0x80,Disabled CONFIG5H~2~2=0x80,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-01FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 02000-03FFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x0,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x0,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTC,0x20,Config. Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTD,0x80,Data EEPROM Write Protect CONFIG6H~1~1=0x20,0x20,Disabled CONFIG6H~1~2=0x20,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x80,0x80,Disabled CONFIG6H~3~2=0x80,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-01FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 02000-03FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x0,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x0,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F14K50] pgmmem=0x0 ~pgmmem=0x3fff cfgmem=0x300000 ~cfgmem=0x30000d userid=0x200000 ~userid=0x200007 eedata=0x0 ~eedata=0xff devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0x4760 configslots=14 0x300000=CONFIG1L 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000a=CONFIG6L 0x30000b=CONFIG6H 0x30000c=CONFIG7L 0x30000d=CONFIG7H CONFIG1L_unused=0x0 CONFIG1L~1=CPUDIV,0x18,CPU System Clock Selection bits CONFIG1L~2=USBDIV,0x20,USB Clock Selection bit CONFIG1L~1~1=0x18,0x18,CPU system clock divided by 4 CONFIG1L~1~2=0x18,0x10,CPU system clock divided by 3 CONFIG1L~1~3=0x18,0x8,CPU system clock divided by 2 CONFIG1L~1~4=0x18,0x0,No CPU system clock divide CONFIG1L~2~1=0x20,0x20,USB clock comes from the OSC1/OSC2 divided by 2 CONFIG1L~2~2=0x20,0x0,USB clock comes directly from the OSC1/OSC2 Oscillator block; no divide CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xf,Oscillator CONFIG1H~2=PLLEN,0x10,4 X PLL Enable bit CONFIG1H~3=PCLKEN,0x20,Primary Clock Enable bit CONFIG1H~4=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~5=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xe,0xe,111X EXT RC-CLKOUT on OSC2 CONFIG1H~1~2=0xf,0xd,EC - Low CONFIG1H~1~3=0xf,0xc,EC-CLKOUT on OSC2 - Low CONFIG1H~1~4=0xf,0xb,EC - Medium CONFIG1H~1~5=0xf,0xa,EC-CLKOUT on OSC2 - Medium CONFIG1H~1~6=0xf,0x9,INT RC-CLKOUT on OSC2 CONFIG1H~1~7=0xf,0x8,INT RC CONFIG1H~1~8=0xf,0x7,EXT RC CONFIG1H~1~9=0xf,0x6,0110 EXT RC-CLKOUT on OSC2 CONFIG1H~1~10=0xf,0x5,EC - High CONFIG1H~1~11=0xf,0x4,EC-CLKOUT on OSC2 - High CONFIG1H~1~12=0xf,0x3,0011 EXT RC-CLKOUT on OSC2 CONFIG1H~1~13=0xf,0x2,HS CONFIG1H~1~14=0xf,0x1,XT CONFIG1H~1~15=0xf,0x0,LP CONFIG1H~2~1=0x10,0x10,Oscillator multiplied by 4 CONFIG1H~2~2=0x10,0x0,Oscillator used directly CONFIG1H~3~1=0x20,0x20,Primary Clock enabled CONFIG1H~3~2=0x20,0x0,Primary Clock disabled CONFIG1H~4~1=0x40,0x0,Disabled CONFIG1H~4~2=0x40,0x40,Enabled CONFIG1H~5~1=0x80,0x0,Disabled CONFIG1H~5~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=nPWRTEN,0x1,Power Up Timer CONFIG2L~2=BOREN,0x6,Brown Out Detect CONFIG2L~3=BORV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,1.9V CONFIG2L~3~2=0x18,0x10,2.2V CONFIG2L~3~3=0x18,0x8,2.7V CONFIG2L~3~4=0x18,0x0,3.0V CONFIG2H_unused=0x0 CONFIG2H~1=WDTEN,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1e,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1e,0x1e,1:32768 CONFIG2H~2~2=0x1e,0x1c,1:16384 CONFIG2H~2~3=0x1e,0x1a,1:8192 CONFIG2H~2~4=0x1e,0x18,1:4096 CONFIG2H~2~5=0x1e,0x16,1:2048 CONFIG2H~2~6=0x1e,0x14,1:1024 CONFIG2H~2~7=0x1e,0x12,1:512 CONFIG2H~2~8=0x1e,0x10,1:256 CONFIG2H~2~9=0x1e,0xe,1:128 CONFIG2H~2~10=0x1e,0xc,1:64 CONFIG2H~2~11=0x1e,0xa,1:32 CONFIG2H~2~12=0x1e,0x8,1:16 CONFIG2H~2~13=0x1e,0x6,1:8 CONFIG2H~2~14=0x1e,0x4,1:4 CONFIG2H~2~15=0x1e,0x2,1:2 CONFIG2H~2~16=0x1e,0x0,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=HFOFST,0x8,HFINTOSC Fast Start-up CONFIG3H~2=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x8,0x8,HFINTOSC starts clocking the CPU without waiting for the oscillator to stabilize CONFIG3H~1~2=0x8,0x0,The system clock is held off until the HFINTOSC is stable CONFIG3H~2~1=0x80,0x80,MCLR Enabled,RA3 Disabled CONFIG3H~2~2=0x80,0x0,MCLR Disabled,RA3 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVREN,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=BBSIZ,0x8,Boot BLock Size Select bit CONFIG4L~4=XINST,0x40,Extended Instruction Set Enable bit CONFIG4L~5=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x8,0x8,2 kW boot block size CONFIG4L~3~2=0x8,0x0,1 kW boot block size CONFIG4L~4~1=0x40,0x40,Enabled CONFIG4L~4~2=0x40,0x0,Disabled CONFIG4L~5~1=0x80,0x80,Disabled CONFIG4L~5~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-01FFF CONFIG5L~2=CP_1,0x2,Code Protect 02000-03FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x0,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x0,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPB,0x40,Code Protect Boot CONFIG5H~2=CPD,0x80,Data EEPROM Code Protect CONFIG5H~1~1=0x40,0x40,Disabled CONFIG5H~1~2=0x40,0x0,Enabled CONFIG5H~2~1=0x80,0x80,Disabled CONFIG5H~2~2=0x80,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-01FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 02000-03FFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x0,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x0,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTC,0x20,Config. Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTD,0x80,Data EEPROM Write Protect CONFIG6H~1~1=0x20,0x20,Disabled CONFIG6H~1~2=0x20,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x80,0x80,Disabled CONFIG6H~3~2=0x80,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-01FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 02000-03FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x0,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x0,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F23K20] pgmmem=0x0 ~pgmmem=0x1fff cfgmem=0x300000 ~cfgmem=0x30000d userid=0x200000 ~userid=0x200007 eedata=0x0 ~eedata=0xff devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0x20e0 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000a=CONFIG6L 0x30000b=CONFIG6H 0x30000c=CONFIG7L 0x30000d=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=FOSC,0xf,Oscillator Selection bits CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable bit CONFIG1H~3=IESO,0x80,Internal/External Oscillator Switchover bit CONFIG1H~1~1=0xc,0xc,11XX External RC oscillator, CLKOUT function on RA6 CONFIG1H~1~2=0xe,0xa,101X External RC oscillator, CLKOUT function on RA6 CONFIG1H~1~3=0xf,0x9,Internal oscillator block, CLKOUT function on RA6, port function on RA7 CONFIG1H~1~4=0xf,0x8,Internal oscillator block, port function on RA6 and RA7 CONFIG1H~1~5=0xf,0x7,External RC oscillator, port function on RA6 CONFIG1H~1~6=0xf,0x6,HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) CONFIG1H~1~7=0xf,0x5,EC oscillator, port function on RA6 CONFIG1H~1~8=0xf,0x4,EC oscillator, CLKOUT function on RA6 CONFIG1H~1~9=0xf,0x3,External RC oscillator, CLKOUT function on RA6 CONFIG1H~1~10=0xf,0x2,HS oscillator CONFIG1H~1~11=0xf,0x1,XT oscillator CONFIG1H~1~12=0xf,0x0,LP oscillator CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PWRT,0x1,Power-up Timer Enable bit CONFIG2L~2=BOREN,0x6,Brown-out Reset Enable bits CONFIG2L~3=BORV,0x18,Brown Out Reset Voltage bits CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Brown-out Reset enabled in hardware only (SBOREN is disabled) CONFIG2L~2~2=0x6,0x4,Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) CONFIG2L~2~3=0x6,0x2,Enabled CONFIG2L~2~4=0x6,0x0,Disabled CONFIG2L~3~1=0x18,0x18,VBOR set to 1.8 V nominal CONFIG2L~3~2=0x18,0x10,VBOR set to 2.2 V nominal CONFIG2L~3~3=0x18,0x8,VBOR set to 2.7 V nominal CONFIG2L~3~4=0x18,0x0,VBOR set to 3.0 V nominal CONFIG2H_unused=0x0 CONFIG2H~1=WDTEN,0x1,Watchdog Timer Enable bit CONFIG2H~2=WDTPS,0x1e,Watchdog Timer Postscale Select bits CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled CONFIG2H~2~1=0x1e,0x1e,1:32768 CONFIG2H~2~2=0x1e,0x1c,1:16384 CONFIG2H~2~3=0x1e,0x1a,1:8192 CONFIG2H~2~4=0x1e,0x18,1:4096 CONFIG2H~2~5=0x1e,0x16,1:2048 CONFIG2H~2~6=0x1e,0x14,1:1024 CONFIG2H~2~7=0x1e,0x12,1:512 CONFIG2H~2~8=0x1e,0x10,1:256 CONFIG2H~2~9=0x1e,0xe,1:128 CONFIG2H~2~10=0x1e,0xc,1:64 CONFIG2H~2~11=0x1e,0xa,1:32 CONFIG2H~2~12=0x1e,0x8,1:16 CONFIG2H~2~13=0x1e,0x6,1:8 CONFIG2H~2~14=0x1e,0x4,1:4 CONFIG2H~2~15=0x1e,0x2,1:2 CONFIG2H~2~16=0x1e,0x0,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 MUX bit CONFIG3H~2=PBADEN,0x2,PORTB A/D Enable bit CONFIG3H~3=LPT1OSC,0x4,Low-Power Timer1 Oscillator Enable bit CONFIG3H~4=HFOFST,0x8,HFINTOSC Fast Start-up CONFIG3H~5=MCLRE,0x80,MCLR Pin Enable bit CONFIG3H~1~1=0x1,0x1,CCP2 input/output is multiplexed with RC1 CONFIG3H~1~2=0x1,0x0,CCP2 input/output is multiplexed with RB3 CONFIG3H~2~1=0x2,0x2,Enabled CONFIG3H~2~2=0x2,0x0,Disabled CONFIG3H~3~1=0x4,0x4,Enabled CONFIG3H~3~2=0x4,0x0,Disabled CONFIG3H~4~1=0x8,0x8,Enabled CONFIG3H~4~2=0x8,0x0,Disabled CONFIG3H~5~1=0x80,0x80,Enabled CONFIG3H~5~2=0x80,0x0,Disabled CONFIG4L_unused=0x0 CONFIG4L~1=STVREN,0x1,Stack Full/Underflow Reset Enable bit CONFIG4L~2=LVP,0x4,Single-Supply ICSP Enable bit CONFIG4L~3=XINST,0x40,Extended Instruction Set Enable bit CONFIG4L~4=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x40,0x40,Enabled CONFIG4L~3~2=0x40,0x0,Disabled CONFIG4L~4~1=0x80,0x80,Disabled CONFIG4L~4~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP0,0x1,Code Protection Block 0 CONFIG5L~2=CP1,0x2,Code Protection Block 1 CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x0,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x0,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPB,0x40,Boot Block Code Protection bit CONFIG5H~2=CPD,0x80,Data EEPROM Code Protection bit CONFIG5H~1~1=0x40,0x40,Disabled CONFIG5H~1~2=0x40,0x0,Enabled CONFIG5H~2~1=0x80,0x80,Disabled CONFIG5H~2~2=0x80,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT0,0x1,Write Protection Block 0 CONFIG6L~2=WRT1,0x2,Write Protection Block 1 CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x0,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x0,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTC,0x20,Configuration Register Write Protection bit CONFIG6H~2=WRTB,0x40,Boot Block Write Protection bit CONFIG6H~3=WRTD,0x80,Data EEPROM Write Protection bit CONFIG6H~1~1=0x20,0x20,Disabled CONFIG6H~1~2=0x20,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x80,0x80,Disabled CONFIG6H~3~2=0x80,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR0,0x1,Table Read Protection Block 0 CONFIG7L~2=EBTR1,0x2,Table Read Protection Block 1 CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x0,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x0,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Boot Block Table Read Protection bit CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F2458] pgmmem=0x0 ~pgmmem=0x5fff cfgmem=0x300000 ~cfgmem=0x30000d userid=0x200000 ~userid=0x200007 eedata=0x0 ~eedata=0xff devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0x2a60 configslots=14 0x300000=CONFIG1L 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000a=CONFIG6L 0x30000b=CONFIG6H 0x30000c=CONFIG7L 0x30000d=CONFIG7H CONFIG1L_unused=0x0 CONFIG1L~1=PLLDIV,0x7,96MHz PLL Prescaler CONFIG1L~2=CPUDIV,0x18,CPU System Clock Postscaler CONFIG1L~3=USBPLL,0x20,Full-Speed USB Clock Source Selection CONFIG1L~1~1=0x7,0x7,Divide by 12 (48MHz input) CONFIG1L~1~2=0x7,0x6,Divide by 10 (40MHz input) CONFIG1L~1~3=0x7,0x5,Divide by 6 (24MHz input) CONFIG1L~1~4=0x7,0x4,Divide by 5 (20MHz input) CONFIG1L~1~5=0x7,0x3,Divide by 4 (16MHz input) CONFIG1L~1~6=0x7,0x2,Divide by 3 (12MHz input) CONFIG1L~1~7=0x7,0x1,Divide by 2 (8MHz input) CONFIG1L~1~8=0x7,0x0,No Divide (4MHz input) CONFIG1L~2~1=0x18,0x18,[OSC1/OSC2 Src: /4][96MHz PLL Src: /6] CONFIG1L~2~2=0x18,0x10,[OSC1/OSC2 Src: /3][96MHz PLL Src: /4] CONFIG1L~2~3=0x18,0x8,[OSC1/OSC2 Src: /2][96MHz PLL Src: /3] CONFIG1L~2~4=0x18,0x0,[OSC1/OSC2 Src: /1][96MHz PLL Src: /2] CONFIG1L~3~1=0x20,0x20,Clock src from 96MHz PLL/2 CONFIG1L~3~2=0x20,0x0,Clock src from OSC1/OSC2 CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xf,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xe,0xe,HS: HS+PLL, USB-HS CONFIG1H~1~2=0xe,0xc,HS: USB-HS CONFIG1H~1~3=0xf,0xb,INTOSC: USB-HS CONFIG1H~1~4=0xf,0xa,INTOSC: USB-XT CONFIG1H~1~5=0xf,0x9,INTOSC: INTOSC+CLK0{RA6}, USB-EC CONFIG1H~1~6=0xf,0x8,INTOSC: INTOSC+RA6, USB-EC CONFIG1H~1~7=0xf,0x7,EC: EC+PLL, EC+PLL+CLKO{RA6}, USB-EC CONFIG1H~1~8=0xf,0x6,EC: EC+PLL, EC+PLL+RA6, USB-EC CONFIG1H~1~9=0xf,0x5,EC: EC+CLKO{RA6}, USB-EC CONFIG1H~1~10=0xf,0x4,EC: EC+RA6, USB-EC CONFIG1H~1~11=0xe,0x2,XT: XT+PLL, USB-XT CONFIG1H~1~12=0xe,0x0,XT: USB-XT CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~4=VREGEN,0x20,USB Voltage Regulator CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x8,4.2V CONFIG2L~3~4=0x18,0x0,4.5V CONFIG2L~4~1=0x20,0x20,Enabled CONFIG2L~4~2=0x20,0x0,Disabled CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1e,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1e,0x1e,1:32768 CONFIG2H~2~2=0x1e,0x1c,1:16384 CONFIG2H~2~3=0x1e,0x1a,1:8192 CONFIG2H~2~4=0x1e,0x18,1:4096 CONFIG2H~2~5=0x1e,0x16,1:2048 CONFIG2H~2~6=0x1e,0x14,1:1024 CONFIG2H~2~7=0x1e,0x12,1:512 CONFIG2H~2~8=0x1e,0x10,1:256 CONFIG2H~2~9=0x1e,0xe,1:128 CONFIG2H~2~10=0x1e,0xc,1:64 CONFIG2H~2~11=0x1e,0xa,1:32 CONFIG2H~2~12=0x1e,0x8,1:16 CONFIG2H~2~13=0x1e,0x6,1:8 CONFIG2H~2~14=0x1e,0x4,1:4 CONFIG2H~2~15=0x1e,0x2,1:2 CONFIG2H~2~16=0x1e,0x0,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=PBADEN,0x2,PortB A/D Enable CONFIG3H~3=LPT1OSC,0x4,Low Power Timer1 Osc enable CONFIG3H~4=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RB3 CONFIG3H~2~1=0x2,0x2,PORTB<4:0> configured as analog inputs on RESET CONFIG3H~2~2=0x2,0x0,PORTB<4:0> configured as digital I/O on RESET CONFIG3H~3~1=0x4,0x4,Enabled CONFIG3H~3~2=0x4,0x0,Disabled CONFIG3H~4~1=0x80,0x80,MCLR Enabled,RE3 Disabled CONFIG3H~4~2=0x80,0x0,MCLR Disabled,RE3 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=ENICPORT,0x20,Dedicated In-Circuit Port {ICD/ICSP} CONFIG4L~4=XINST,0x40,Extended Instruction Set Enable bit CONFIG4L~5=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x20,0x0,Disabled CONFIG4L~4~1=0x40,0x40,Enabled CONFIG4L~4~2=0x40,0x0,Disabled CONFIG4L~5~1=0x80,0x80,Disabled CONFIG4L~5~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-01FFF CONFIG5L~2=CP_1,0x2,Code Protect 02000-03FFF CONFIG5L~3=CP_2,0x4,Code Protect 04000-05FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x0,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x0,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x0,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPB,0x40,Code Protect Boot CONFIG5H~2=CPD,0x80,Data EE Read Protect CONFIG5H~1~1=0x40,0x40,Disabled CONFIG5H~1~2=0x40,0x0,Enabled CONFIG5H~2~1=0x80,0x80,Disabled CONFIG5H~2~2=0x80,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-01FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 02000-03FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 04000-05FFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x0,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x0,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x0,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTC,0x20,Config. Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTD,0x80,Data EE Write Protect CONFIG6H~1~1=0x20,0x20,Disabled CONFIG6H~1~2=0x20,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x80,0x80,Disabled CONFIG6H~3~2=0x80,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-01FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 02000-03FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 04000-05FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x0,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x0,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x0,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE_24xx05 prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F24J11] pgmmem=0x0 ~pgmmem=0x3ff7 cfgmem=0x3ff8 ~cfgmem=0x3fff userid= ~userid= eedata= ~eedata= devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0x4d80 configslots=8 0x3ff8=CONFIG1L 0x3ff9=CONFIG1H 0x3ffa=CONFIG2L 0x3ffb=CONFIG2H 0x3ffc=CONFIG3L 0x3ffd=CONFIG3H 0x3ffe=CONFIG4L 0x3fff=CONFIG4H CONFIG1L_unused=0x0 CONFIG1L~1=WDTEN,0x1,Watchdog Timer CONFIG1L~2=STVREN,0x20,Stack Overflow/Underflow Reset CONFIG1L~3=XINST,0x40,Extended Instruction Set CONFIG1L~4=DEBUG,0x80,Background Debug CONFIG1L~1~1=0x1,0x1,Enabled CONFIG1L~1~2=0x1,0x0,Disabled CONFIG1L~2~1=0x20,0x20,Enabled CONFIG1L~2~2=0x20,0x0,Disabled CONFIG1L~3~1=0x40,0x40,Enabled CONFIG1L~3~2=0x40,0x0,Disabled CONFIG1L~4~1=0x80,0x80,Disabled CONFIG1L~4~2=0x80,0x0,Enabled CONFIG1H_unused=0x0 CONFIG1H~1=CP0,0x4,Code Protect CONFIG1H~2=SIGN,0x8,Config Word Signature Bit CONFIG1H~3=RESERVED,0xf0,RESERVED CONFIG1H~1~1=0x4,0x4,Disabled CONFIG1H~1~2=0x4,0x0,Enabled CONFIG1H~2~1=0x8,0x8,Bulk erase of memory not conducated CONFIG1H~2~2=0x8,0x0,Bulk erase of memory area complete CONFIG1H~3~1=0xf0,0xf0,RESERVED CONFIG2L_unused=0x0 CONFIG2L~1=OSC,0x7,Oscillator CONFIG2L~2=T1DIG,0x8,T1OSCEN Enforcement CONFIG2L~3=LPT1OSC,0x10,Low-Power Timer1 Oscillator CONFIG2L~4=FCMEN,0x40,Fail-Safe Clock Monitor CONFIG2L~5=IESO,0x80,Internal External Oscillator Switch Over Mode CONFIG2L~1~1=0x7,0x7,EC+PLL (CLKO-RA6) CONFIG2L~1~2=0x7,0x6,EC (CLKO-RA6) CONFIG2L~1~3=0x7,0x5,HS+PLL CONFIG2L~1~4=0x7,0x4,HS CONFIG2L~1~5=0x7,0x3,INTOSCPLLO (CLKO-RA6) CONFIG2L~1~6=0x7,0x2,INTOSCPLL CONFIG2L~1~7=0x7,0x1,INTOSCO (CLKO-RA6) CONFIG2L~1~8=0x7,0x0,INTOSC CONFIG2L~2~1=0x8,0x8,Enabled CONFIG2L~2~2=0x8,0x0,Disabled CONFIG2L~3~1=0x10,0x10,Disabled CONFIG2L~3~2=0x10,0x0,Enabled CONFIG2L~4~1=0x40,0x0,Disabled CONFIG2L~4~2=0x40,0x40,Enabled CONFIG2L~5~1=0x80,0x0,Disabled CONFIG2L~5~2=0x80,0x80,Enabled CONFIG2H_unused=0x0 CONFIG2H~1=WDTPS,0xf,Watchdog Postscaler CONFIG2H~2=RESERVED,0xf0,RESERVED CONFIG2H~1~1=0xf,0xf,1:32768 CONFIG2H~1~2=0xf,0xe,1:16384 CONFIG2H~1~3=0xf,0xd,1:8192 CONFIG2H~1~4=0xf,0xc,1:4096 CONFIG2H~1~5=0xf,0xb,1:2048 CONFIG2H~1~6=0xf,0xa,1:1024 CONFIG2H~1~7=0xf,0x9,1:512 CONFIG2H~1~8=0xf,0x8,1:256 CONFIG2H~1~9=0xf,0x7,1:128 CONFIG2H~1~10=0xf,0x6,1:64 CONFIG2H~1~11=0xf,0x5,1:32 CONFIG2H~1~12=0xf,0x4,1:16 CONFIG2H~1~13=0xf,0x3,1:8 CONFIG2H~1~14=0xf,0x2,1:4 CONFIG2H~1~15=0xf,0x1,1:2 CONFIG2H~1~16=0xf,0x0,1:1 CONFIG2H~2~1=0xf0,0xf0,RESERVED CONFIG3L_unused=0x0 CONFIG3L~1=DSWDTOSC,0x1,DSWDT Clock Select CONFIG3L~2=RTCOSC,0x2,RTCC Clock Select CONFIG3L~3=DSBOREN,0x4,Deep Sleep BOR CONFIG3L~4=DSWDTEN,0x8,Deep Sleep Watchdog Timer CONFIG3L~5=DSWDTPS,0xf0,Deep Sleep Watchdog Postscaler CONFIG3L~1~1=0x1,0x1,DSWDT uses INTRC CONFIG3L~1~2=0x1,0x0,DSWDT uses T1OSC/T1CKI CONFIG3L~2~1=0x2,0x2,RTCC uses T1OSC/T1CKI CONFIG3L~2~2=0x2,0x0,RTCC uses INTRC CONFIG3L~3~1=0x4,0x4,Enabled CONFIG3L~3~2=0x4,0x0,Disabled CONFIG3L~4~1=0x8,0x8,Enabled CONFIG3L~4~2=0x8,0x0,Disabled CONFIG3L~5~1=0xf0,0xf0,1:2,147,483,648 (25.7 days) CONFIG3L~5~2=0xf0,0xe0,1:536,870,912 (6.4 days) CONFIG3L~5~3=0xf0,0xd0,1:134,217,728 (38.5 hours) CONFIG3L~5~4=0xf0,0xc0,1:33,554,432 (9.6 hours) CONFIG3L~5~5=0xf0,0xb0,1:8,388,608 (2.4 hours) CONFIG3L~5~6=0xf0,0xa0,1:2,097,152 (36 minutes) CONFIG3L~5~7=0xf0,0x90,1:524,288 (9 minutes) CONFIG3L~5~8=0xf0,0x80,1:131,072 (135 seconds) CONFIG3L~5~9=0xf0,0x70,1:32,768 (34 seconds) CONFIG3L~5~10=0xf0,0x60,1:8,192 (8.5 seconds) CONFIG3L~5~11=0xf0,0x50,1:2,048 (2.1 seconds) CONFIG3L~5~12=0xf0,0x40,1:512 (528 ms) CONFIG3L~5~13=0xf0,0x30,1:128 (132 ms) CONFIG3L~5~14=0xf0,0x20,1:32 (33 ms) CONFIG3L~5~15=0xf0,0x10,1:8 (8.3 ms) CONFIG3L~5~16=0xf0,0x0,1:2 (2.1 ms) CONFIG3H_unused=0x0 CONFIG3H~1=IOL1WAY,0x1,IOLOCK One-Way Set Enable bit CONFIG3H~2=MSSP7B_EN,0x8,MSSP address masking CONFIG3H~3=RESERVED,0xf0,RESERVED CONFIG3H~1~1=0x1,0x1,Enabled CONFIG3H~1~2=0x1,0x0,Disabled CONFIG3H~2~1=0x8,0x8,7 Bit address masking mode CONFIG3H~2~2=0x8,0x0,5 Bit address masking mode CONFIG3H~3~1=0xf0,0xf0,RESERVED CONFIG4L_unused=0x0 CONFIG4L~1=WPFP,0xf,Write/Erase Protect Page Start/End Location CONFIG4L~2=WPEND,0x40,Write/Erase Protect Region Select bit (valid when WPDIS = 0) CONFIG4L~3=WPCFG,0x80,Write/Erase Protect Configuration Region CONFIG4L~1~1=0xf,0x0,Write Protect Program Flash Page 0 CONFIG4L~1~2=0xf,0x1,Write Protect Program Flash Page 1 CONFIG4L~1~3=0xf,0x2,Write Protect Program Flash Page 2 CONFIG4L~1~4=0xf,0x3,Write Protect Program Flash Page 3 CONFIG4L~1~5=0xf,0x4,Write Protect Program Flash Page 4 CONFIG4L~1~6=0xf,0x5,Write Protect Program Flash Page 5 CONFIG4L~1~7=0xf,0x6,Write Protect Program Flash Page 6 CONFIG4L~1~8=0xf,0x7,Write Protect Program Flash Page 7 CONFIG4L~1~9=0xf,0x8,Write Protect Program Flash Page 8 CONFIG4L~1~10=0xf,0x9,Write Protect Program Flash Page 9 CONFIG4L~1~11=0xf,0xa,Write Protect Program Flash Page 10 CONFIG4L~1~12=0xf,0xb,Write Protect Program Flash Page 11 CONFIG4L~1~13=0xf,0xc,Write Protect Program Flash Page 12 CONFIG4L~1~14=0xf,0xd,Write Protect Program Flash Page 13 CONFIG4L~1~15=0xf,0xe,Write Protect Program Flash Page 14 CONFIG4L~1~16=0xf,0xf,Write Protect Program Flash Page 15 CONFIG4L~2~1=0x40,0x40,Pages WPFP<5:0> to (Configuration Words page) write/erase protected CONFIG4L~2~2=0x40,0x0,Page 0 to WPFP<5:0> erase/write-protected CONFIG4L~3~1=0x80,0x80,Disabled CONFIG4L~3~2=0x80,0x0,Enabled CONFIG4H_unused=0x0 CONFIG4H~1=WPDIS,0x1,Write Protect Disable bit CONFIG4H~2=RESERVED,0xf0,RESERVED CONFIG4H~1~1=0x1,0x1,Disabled CONFIG4H~1~2=0x1,0x0,Enabled CONFIG4H~2~1=0xf0,0xf0,RESERVED erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F24J50] pgmmem=0x0 ~pgmmem=0x3ff7 cfgmem=0x3ff8 ~cfgmem=0x3fff userid= ~userid= eedata= ~eedata= devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0x4c00 configslots=8 0x3ff8=CONFIG1L 0x3ff9=CONFIG1H 0x3ffa=CONFIG2L 0x3ffb=CONFIG2H 0x3ffc=CONFIG3L 0x3ffd=CONFIG3H 0x3ffe=CONFIG4L 0x3fff=CONFIG4H CONFIG1L_unused=0x0 CONFIG1L~1=WDTEN,0x1,Watchdog Timer CONFIG1L~2=PLLDIV,0xe,PLL Prescaler Selection bits CONFIG1L~3=STVREN,0x20,Stack Overflow/Underflow Reset CONFIG1L~4=XINST,0x40,Extended Instruction Set CONFIG1L~5=DEBUG,0x80,Background Debug CONFIG1L~1~1=0x1,0x1,Enabled CONFIG1L~1~2=0x1,0x0,Disabled CONFIG1L~2~1=0xe,0xe,No prescale (4 MHz oscillator input drives PLL directly) CONFIG1L~2~2=0xe,0xc,Divide by 2 (8 MHz oscillator input) CONFIG1L~2~3=0xe,0xa,Divide by 3 (12 MHz oscillator input) CONFIG1L~2~4=0xe,0x8,Divide by 4 (16 MHz oscillator input) CONFIG1L~2~5=0xe,0x6,Divide by 5 (20 MHz oscillator input) CONFIG1L~2~6=0xe,0x4,Divide by 6 (24 MHz oscillator input) CONFIG1L~2~7=0xe,0x2,Divide by 10 (40 MHz oscillator input) CONFIG1L~2~8=0xe,0x0,Divide by 12 (48 MHz oscillator input) CONFIG1L~3~1=0x20,0x20,Enabled CONFIG1L~3~2=0x20,0x0,Disabled CONFIG1L~4~1=0x40,0x40,Enabled CONFIG1L~4~2=0x40,0x0,Disabled CONFIG1L~5~1=0x80,0x80,Disabled CONFIG1L~5~2=0x80,0x0,Enabled CONFIG1H_unused=0x0 CONFIG1H~1=CPUDIV,0x3,CPU System Clock Postscaler CONFIG1H~2=CP0,0x4,Code Protect CONFIG1H~3=SIGN,0x8,Config Word Signature Bit CONFIG1H~4=RESERVED,0xf0,RESERVED CONFIG1H~1~1=0x3,0x3,No CPU system clock divide CONFIG1H~1~2=0x3,0x2,CPU system clock divide by 2 CONFIG1H~1~3=0x3,0x1,CPU system clock divide by 3 CONFIG1H~1~4=0x3,0x0,CPU system clock divide by 6 CONFIG1H~2~1=0x4,0x4,Disabled CONFIG1H~2~2=0x4,0x0,Enabled CONFIG1H~3~1=0x8,0x8,Bulk erase of memory not conducated CONFIG1H~3~2=0x8,0x0,Bulk erase of memory area complete CONFIG1H~4~1=0xf0,0xf0,RESERVED CONFIG2L_unused=0x0 CONFIG2L~1=OSC,0x7,Oscillator CONFIG2L~2=T1DIG,0x8,T1OSCEN Enforcement CONFIG2L~3=LPT1OSC,0x10,Low-Power Timer1 Oscillator CONFIG2L~4=FCMEN,0x40,Fail-Safe Clock Monitor CONFIG2L~5=IESO,0x80,Internal External Oscillator Switch Over Mode CONFIG2L~1~1=0x7,0x7,EC+PLL (CLKO-RA6), USB-EC+PLL CONFIG2L~1~2=0x7,0x6,EC (CLKO-RA6), USB-EC CONFIG2L~1~3=0x7,0x5,HS+PLL, USB-HS+PLL CONFIG2L~1~4=0x7,0x4,HS, USB-HS CONFIG2L~1~5=0x7,0x3,INTOSCPLLO (CLKO-RA6) CONFIG2L~1~6=0x7,0x2,INTOSCPLL CONFIG2L~1~7=0x7,0x1,INTOSCO (CLKO-RA6) CONFIG2L~1~8=0x7,0x0,INTOSC CONFIG2L~2~1=0x8,0x8,Enabled CONFIG2L~2~2=0x8,0x0,Disabled CONFIG2L~3~1=0x10,0x10,Disabled CONFIG2L~3~2=0x10,0x0,Enabled CONFIG2L~4~1=0x40,0x0,Disabled CONFIG2L~4~2=0x40,0x40,Enabled CONFIG2L~5~1=0x80,0x0,Disabled CONFIG2L~5~2=0x80,0x80,Enabled CONFIG2H_unused=0x0 CONFIG2H~1=WDTPS,0xf,Watchdog Postscaler CONFIG2H~2=RESERVED,0xf0,RESERVED CONFIG2H~1~1=0xf,0xf,1:32768 CONFIG2H~1~2=0xf,0xe,1:16384 CONFIG2H~1~3=0xf,0xd,1:8192 CONFIG2H~1~4=0xf,0xc,1:4096 CONFIG2H~1~5=0xf,0xb,1:2048 CONFIG2H~1~6=0xf,0xa,1:1024 CONFIG2H~1~7=0xf,0x9,1:512 CONFIG2H~1~8=0xf,0x8,1:256 CONFIG2H~1~9=0xf,0x7,1:128 CONFIG2H~1~10=0xf,0x6,1:64 CONFIG2H~1~11=0xf,0x5,1:32 CONFIG2H~1~12=0xf,0x4,1:16 CONFIG2H~1~13=0xf,0x3,1:8 CONFIG2H~1~14=0xf,0x2,1:4 CONFIG2H~1~15=0xf,0x1,1:2 CONFIG2H~1~16=0xf,0x0,1:1 CONFIG2H~2~1=0xf0,0xf0,RESERVED CONFIG3L_unused=0x0 CONFIG3L~1=DSWDTOSC,0x1,DSWDT Clock Select CONFIG3L~2=RTCOSC,0x2,RTCC Clock Select CONFIG3L~3=DSBOREN,0x4,Deep Sleep BOR CONFIG3L~4=DSWDTEN,0x8,Deep Sleep Watchdog Timer CONFIG3L~5=DSWDTPS,0xf0,Deep Sleep Watchdog Postscaler CONFIG3L~1~1=0x1,0x1,DSWDT uses INTRC CONFIG3L~1~2=0x1,0x0,DSWDT uses T1OSC/T1CKI CONFIG3L~2~1=0x2,0x2,RTCC uses T1OSC/T1CKI CONFIG3L~2~2=0x2,0x0,RTCC uses INTRC CONFIG3L~3~1=0x4,0x4,Enabled CONFIG3L~3~2=0x4,0x0,Disabled CONFIG3L~4~1=0x8,0x8,Enabled CONFIG3L~4~2=0x8,0x0,Disabled CONFIG3L~5~1=0xf0,0xf0,1:2,147,483,648 (25.7 days) CONFIG3L~5~2=0xf0,0xe0,1:536,870,912 (6.4 days) CONFIG3L~5~3=0xf0,0xd0,1:134,217,728 (38.5 hours) CONFIG3L~5~4=0xf0,0xc0,1:33,554,432 (9.6 hours) CONFIG3L~5~5=0xf0,0xb0,1:8,388,608 (2.4 hours) CONFIG3L~5~6=0xf0,0xa0,1:2,097,152 (36 minutes) CONFIG3L~5~7=0xf0,0x90,1:524,288 (9 minutes) CONFIG3L~5~8=0xf0,0x80,1:131,072 (135 seconds) CONFIG3L~5~9=0xf0,0x70,1:32,768 (34 seconds) CONFIG3L~5~10=0xf0,0x60,1:8,192 (8.5 seconds) CONFIG3L~5~11=0xf0,0x50,1:2,048 (2.1 seconds) CONFIG3L~5~12=0xf0,0x40,1:512 (528 ms) CONFIG3L~5~13=0xf0,0x30,1:128 (132 ms) CONFIG3L~5~14=0xf0,0x20,1:32 (33 ms) CONFIG3L~5~15=0xf0,0x10,1:8 (8.3 ms) CONFIG3L~5~16=0xf0,0x0,1:2 (2.1 ms) CONFIG3H_unused=0x0 CONFIG3H~1=IOL1WAY,0x1,IOLOCK One-Way Set Enable bit CONFIG3H~2=MSSP7B_EN,0x8,MSSP address masking CONFIG3H~3=RESERVED,0xf0,RESERVED CONFIG3H~1~1=0x1,0x1,Enabled CONFIG3H~1~2=0x1,0x0,Disabled CONFIG3H~2~1=0x8,0x8,7 Bit address masking mode CONFIG3H~2~2=0x8,0x0,5 Bit address masking mode CONFIG3H~3~1=0xf0,0xf0,RESERVED CONFIG4L_unused=0x0 CONFIG4L~1=WPFP,0xf,Write/Erase Protect Page Start/End Location CONFIG4L~2=WPEND,0x40,Write/Erase Protect Region Select bit (valid when WPDIS = 0) CONFIG4L~3=WPCFG,0x80,Write/Erase Protect Configuration Region CONFIG4L~1~1=0xf,0x0,Write Protect Program Flash Page 0 CONFIG4L~1~2=0xf,0x1,Write Protect Program Flash Page 1 CONFIG4L~1~3=0xf,0x2,Write Protect Program Flash Page 2 CONFIG4L~1~4=0xf,0x3,Write Protect Program Flash Page 3 CONFIG4L~1~5=0xf,0x4,Write Protect Program Flash Page 4 CONFIG4L~1~6=0xf,0x5,Write Protect Program Flash Page 5 CONFIG4L~1~7=0xf,0x6,Write Protect Program Flash Page 6 CONFIG4L~1~8=0xf,0x7,Write Protect Program Flash Page 7 CONFIG4L~1~9=0xf,0x8,Write Protect Program Flash Page 8 CONFIG4L~1~10=0xf,0x9,Write Protect Program Flash Page 9 CONFIG4L~1~11=0xf,0xa,Write Protect Program Flash Page 10 CONFIG4L~1~12=0xf,0xb,Write Protect Program Flash Page 11 CONFIG4L~1~13=0xf,0xc,Write Protect Program Flash Page 12 CONFIG4L~1~14=0xf,0xd,Write Protect Program Flash Page 13 CONFIG4L~1~15=0xf,0xe,Write Protect Program Flash Page 14 CONFIG4L~1~16=0xf,0xf,Write Protect Program Flash Page 15 CONFIG4L~2~1=0x40,0x40,Pages WPFP<5:0> to (Configuration Words page) write/erase protected CONFIG4L~2~2=0x40,0x0,Page 0 to WPFP<5:0> erase/write-protected CONFIG4L~3~1=0x80,0x80,Disabled CONFIG4L~3~2=0x80,0x0,Enabled CONFIG4H_unused=0x0 CONFIG4H~1=WPDIS,0x1,Write Protect Disable bit CONFIG4H~2=RESERVED,0xf0,RESERVED CONFIG4H~1~1=0x1,0x1,Disabled CONFIG4H~1~2=0x1,0x0,Enabled CONFIG4H~2~1=0xf0,0xf0,RESERVED erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F2553] pgmmem=0x0 ~pgmmem=0x7fff cfgmem=0x300000 ~cfgmem=0x30000d userid=0x200000 ~userid=0x200007 eedata=0x0 ~eedata=0xff devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0x2a40 configslots=14 0x300000=CONFIG1L 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000a=CONFIG6L 0x30000b=CONFIG6H 0x30000c=CONFIG7L 0x30000d=CONFIG7H CONFIG1L_unused=0x0 CONFIG1L~1=PLLDIV,0x7,96MHz PLL Prescaler CONFIG1L~2=CPUDIV,0x18,CPU System Clock Postscaler CONFIG1L~3=USBPLL,0x20,Full-Speed USB Clock Source Selection CONFIG1L~1~1=0x7,0x7,Divide by 12 (48MHz input) CONFIG1L~1~2=0x7,0x6,Divide by 10 (40MHz input) CONFIG1L~1~3=0x7,0x5,Divide by 6 (24MHz input) CONFIG1L~1~4=0x7,0x4,Divide by 5 (20MHz input) CONFIG1L~1~5=0x7,0x3,Divide by 4 (16MHz input) CONFIG1L~1~6=0x7,0x2,Divide by 3 (12MHz input) CONFIG1L~1~7=0x7,0x1,Divide by 2 (8MHz input) CONFIG1L~1~8=0x7,0x0,No Divide (4MHz input) CONFIG1L~2~1=0x18,0x18,[OSC1/OSC2 Src: /4][96MHz PLL Src: /6] CONFIG1L~2~2=0x18,0x10,[OSC1/OSC2 Src: /3][96MHz PLL Src: /4] CONFIG1L~2~3=0x18,0x8,[OSC1/OSC2 Src: /2][96MHz PLL Src: /3] CONFIG1L~2~4=0x18,0x0,[OSC1/OSC2 Src: /1][96MHz PLL Src: /2] CONFIG1L~3~1=0x20,0x20,Clock src from 96MHz PLL/2 CONFIG1L~3~2=0x20,0x0,Clock src from OSC1/OSC2 CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xf,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xe,0xe,HS: HS+PLL, USB-HS CONFIG1H~1~2=0xe,0xc,HS: USB-HS CONFIG1H~1~3=0xf,0xb,INTOSC: USB-HS CONFIG1H~1~4=0xf,0xa,INTOSC: USB-XT CONFIG1H~1~5=0xf,0x9,INTOSC: INTOSC+CLK0{RA6}, USB-EC CONFIG1H~1~6=0xf,0x8,INTOSC: INTOSC+RA6, USB-EC CONFIG1H~1~7=0xf,0x7,EC: EC+PLL, EC+PLL+CLKO{RA6}, USB-EC CONFIG1H~1~8=0xf,0x6,EC: EC+PLL, EC+PLL+RA6, USB-EC CONFIG1H~1~9=0xf,0x5,EC: EC+CLKO{RA6}, USB-EC CONFIG1H~1~10=0xf,0x4,EC: EC+RA6, USB-EC CONFIG1H~1~11=0xe,0x2,XT: XT+PLL, USB-XT CONFIG1H~1~12=0xe,0x0,XT: USB-XT CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~4=VREGEN,0x20,USB Voltage Regulator CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x8,4.2V CONFIG2L~3~4=0x18,0x0,4.5V CONFIG2L~4~1=0x20,0x20,Enabled CONFIG2L~4~2=0x20,0x0,Disabled CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1e,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1e,0x1e,1:32768 CONFIG2H~2~2=0x1e,0x1c,1:16384 CONFIG2H~2~3=0x1e,0x1a,1:8192 CONFIG2H~2~4=0x1e,0x18,1:4096 CONFIG2H~2~5=0x1e,0x16,1:2048 CONFIG2H~2~6=0x1e,0x14,1:1024 CONFIG2H~2~7=0x1e,0x12,1:512 CONFIG2H~2~8=0x1e,0x10,1:256 CONFIG2H~2~9=0x1e,0xe,1:128 CONFIG2H~2~10=0x1e,0xc,1:64 CONFIG2H~2~11=0x1e,0xa,1:32 CONFIG2H~2~12=0x1e,0x8,1:16 CONFIG2H~2~13=0x1e,0x6,1:8 CONFIG2H~2~14=0x1e,0x4,1:4 CONFIG2H~2~15=0x1e,0x2,1:2 CONFIG2H~2~16=0x1e,0x0,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=PBADEN,0x2,PortB A/D Enable CONFIG3H~3=LPT1OSC,0x4,Low Power Timer1 Osc enable CONFIG3H~4=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RB3 CONFIG3H~2~1=0x2,0x2,PORTB<4:0> configured as analog inputs on RESET CONFIG3H~2~2=0x2,0x0,PORTB<4:0> configured as digital I/O on RESET CONFIG3H~3~1=0x4,0x4,Enabled CONFIG3H~3~2=0x4,0x0,Disabled CONFIG3H~4~1=0x80,0x80,MCLR Enabled,RE3 Disabled CONFIG3H~4~2=0x80,0x0,MCLR Disabled,RE3 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=ENICPORT,0x20,Dedicated In-Circuit Port {ICD/ICSP} CONFIG4L~4=XINST,0x40,Extended Instruction Set Enable bit CONFIG4L~5=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x20,0x0,Disabled CONFIG4L~4~1=0x40,0x40,Enabled CONFIG4L~4~2=0x40,0x0,Disabled CONFIG4L~5~1=0x80,0x80,Disabled CONFIG4L~5~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-01FFF CONFIG5L~2=CP_1,0x2,Code Protect 02000-03FFF CONFIG5L~3=CP_2,0x4,Code Protect 04000-05FFF CONFIG5L~4=CP_3,0x8,Code Protect 06000-07FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x0,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x0,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x0,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x0,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPB,0x40,Code Protect Boot CONFIG5H~2=CPD,0x80,Data EE Read Protect CONFIG5H~1~1=0x40,0x40,Disabled CONFIG5H~1~2=0x40,0x0,Enabled CONFIG5H~2~1=0x80,0x80,Disabled CONFIG5H~2~2=0x80,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-01FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 02000-03FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 04000-05FFF CONFIG6L~4=WRT_3,0x8,Table Write Protect 06000-07FFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x0,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x0,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x0,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x0,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTC,0x20,Config. Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTD,0x80,Data EE Write Protect CONFIG6H~1~1=0x20,0x20,Disabled CONFIG6H~1~2=0x20,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x80,0x80,Disabled CONFIG6H~3~2=0x80,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-01FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 02000-03FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 04000-05FFF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 06000-07FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x0,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x0,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x0,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x0,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE_24xx05 prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F25J11] pgmmem=0x0 ~pgmmem=0x7ff7 cfgmem=0x7ff8 ~cfgmem=0x7fff userid= ~userid= eedata= ~eedata= devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0x4da0 configslots=8 0x7ff8=CONFIG1L 0x7ff9=CONFIG1H 0x7ffa=CONFIG2L 0x7ffb=CONFIG2H 0x7ffc=CONFIG3L 0x7ffd=CONFIG3H 0x7ffe=CONFIG4L 0x7fff=CONFIG4H CONFIG1L_unused=0x0 CONFIG1L~1=WDTEN,0x1,Watchdog Timer CONFIG1L~2=STVREN,0x20,Stack Overflow/Underflow Reset CONFIG1L~3=XINST,0x40,Extended Instruction Set CONFIG1L~4=DEBUG,0x80,Background Debug CONFIG1L~1~1=0x1,0x1,Enabled CONFIG1L~1~2=0x1,0x0,Disabled CONFIG1L~2~1=0x20,0x20,Enabled CONFIG1L~2~2=0x20,0x0,Disabled CONFIG1L~3~1=0x40,0x40,Enabled CONFIG1L~3~2=0x40,0x0,Disabled CONFIG1L~4~1=0x80,0x80,Disabled CONFIG1L~4~2=0x80,0x0,Enabled CONFIG1H_unused=0x0 CONFIG1H~1=CP0,0x4,Code Protect CONFIG1H~2=SIGN,0x8,Config Word Signature Bit CONFIG1H~3=RESERVED,0xf0,RESERVED CONFIG1H~1~1=0x4,0x4,Disabled CONFIG1H~1~2=0x4,0x0,Enabled CONFIG1H~2~1=0x8,0x8,Bulk erase of memory not conducated CONFIG1H~2~2=0x8,0x0,Bulk erase of memory area complete CONFIG1H~3~1=0xf0,0xf0,RESERVED CONFIG2L_unused=0x0 CONFIG2L~1=OSC,0x7,Oscillator CONFIG2L~2=T1DIG,0x8,T1OSCEN Enforcement CONFIG2L~3=LPT1OSC,0x10,Low-Power Timer1 Oscillator CONFIG2L~4=FCMEN,0x40,Fail-Safe Clock Monitor CONFIG2L~5=IESO,0x80,Internal External Oscillator Switch Over Mode CONFIG2L~1~1=0x7,0x7,EC+PLL (CLKO-RA6) CONFIG2L~1~2=0x7,0x6,EC (CLKO-RA6) CONFIG2L~1~3=0x7,0x5,HS+PLL CONFIG2L~1~4=0x7,0x4,HS CONFIG2L~1~5=0x7,0x3,INTOSCPLLO (CLKO-RA6) CONFIG2L~1~6=0x7,0x2,INTOSCPLL CONFIG2L~1~7=0x7,0x1,INTOSCO (CLKO-RA6) CONFIG2L~1~8=0x7,0x0,INTOSC CONFIG2L~2~1=0x8,0x8,Enabled CONFIG2L~2~2=0x8,0x0,Disabled CONFIG2L~3~1=0x10,0x10,Disabled CONFIG2L~3~2=0x10,0x0,Enabled CONFIG2L~4~1=0x40,0x0,Disabled CONFIG2L~4~2=0x40,0x40,Enabled CONFIG2L~5~1=0x80,0x0,Disabled CONFIG2L~5~2=0x80,0x80,Enabled CONFIG2H_unused=0x0 CONFIG2H~1=WDTPS,0xf,Watchdog Postscaler CONFIG2H~2=RESERVED,0xf0,RESERVED CONFIG2H~1~1=0xf,0xf,1:32768 CONFIG2H~1~2=0xf,0xe,1:16384 CONFIG2H~1~3=0xf,0xd,1:8192 CONFIG2H~1~4=0xf,0xc,1:4096 CONFIG2H~1~5=0xf,0xb,1:2048 CONFIG2H~1~6=0xf,0xa,1:1024 CONFIG2H~1~7=0xf,0x9,1:512 CONFIG2H~1~8=0xf,0x8,1:256 CONFIG2H~1~9=0xf,0x7,1:128 CONFIG2H~1~10=0xf,0x6,1:64 CONFIG2H~1~11=0xf,0x5,1:32 CONFIG2H~1~12=0xf,0x4,1:16 CONFIG2H~1~13=0xf,0x3,1:8 CONFIG2H~1~14=0xf,0x2,1:4 CONFIG2H~1~15=0xf,0x1,1:2 CONFIG2H~1~16=0xf,0x0,1:1 CONFIG2H~2~1=0xf0,0xf0,RESERVED CONFIG3L_unused=0x0 CONFIG3L~1=DSWDTOSC,0x1,DSWDT Clock Select CONFIG3L~2=RTCOSC,0x2,RTCC Clock Select CONFIG3L~3=DSBOREN,0x4,Deep Sleep BOR CONFIG3L~4=DSWDTEN,0x8,Deep Sleep Watchdog Timer CONFIG3L~5=DSWDTPS,0xf0,Deep Sleep Watchdog Postscaler CONFIG3L~1~1=0x1,0x1,DSWDT uses INTRC CONFIG3L~1~2=0x1,0x0,DSWDT uses T1OSC/T1CKI CONFIG3L~2~1=0x2,0x2,RTCC uses T1OSC/T1CKI CONFIG3L~2~2=0x2,0x0,RTCC uses INTRC CONFIG3L~3~1=0x4,0x4,Enabled CONFIG3L~3~2=0x4,0x0,Disabled CONFIG3L~4~1=0x8,0x8,Enabled CONFIG3L~4~2=0x8,0x0,Disabled CONFIG3L~5~1=0xf0,0xf0,1:2,147,483,648 (25.7 days) CONFIG3L~5~2=0xf0,0xe0,1:536,870,912 (6.4 days) CONFIG3L~5~3=0xf0,0xd0,1:134,217,728 (38.5 hours) CONFIG3L~5~4=0xf0,0xc0,1:33,554,432 (9.6 hours) CONFIG3L~5~5=0xf0,0xb0,1:8,388,608 (2.4 hours) CONFIG3L~5~6=0xf0,0xa0,1:2,097,152 (36 minutes) CONFIG3L~5~7=0xf0,0x90,1:524,288 (9 minutes) CONFIG3L~5~8=0xf0,0x80,1:131,072 (135 seconds) CONFIG3L~5~9=0xf0,0x70,1:32,768 (34 seconds) CONFIG3L~5~10=0xf0,0x60,1:8,192 (8.5 seconds) CONFIG3L~5~11=0xf0,0x50,1:2,048 (2.1 seconds) CONFIG3L~5~12=0xf0,0x40,1:512 (528 ms) CONFIG3L~5~13=0xf0,0x30,1:128 (132 ms) CONFIG3L~5~14=0xf0,0x20,1:32 (33 ms) CONFIG3L~5~15=0xf0,0x10,1:8 (8.3 ms) CONFIG3L~5~16=0xf0,0x0,1:2 (2.1 ms) CONFIG3H_unused=0x0 CONFIG3H~1=IOL1WAY,0x1,IOLOCK One-Way Set Enable bit CONFIG3H~2=MSSP7B_EN,0x8,MSSP address masking CONFIG3H~3=RESERVED,0xf0,RESERVED CONFIG3H~1~1=0x1,0x1,Enabled CONFIG3H~1~2=0x1,0x0,Disabled CONFIG3H~2~1=0x8,0x8,7 Bit address masking mode CONFIG3H~2~2=0x8,0x0,5 Bit address masking mode CONFIG3H~3~1=0xf0,0xf0,RESERVED CONFIG4L_unused=0x0 CONFIG4L~1=WPFP,0x1f,Write/Erase Protect Page Start/End Location CONFIG4L~2=WPEND,0x40,Write/Erase Protect Region Select bit (valid when WPDIS = 0) CONFIG4L~3=WPCFG,0x80,Write/Erase Protect Configuration Region CONFIG4L~1~1=0x1f,0x0,Write Protect Program Flash Page 0 CONFIG4L~1~2=0x1f,0x1,Write Protect Program Flash Page 1 CONFIG4L~1~3=0x1f,0x2,Write Protect Program Flash Page 2 CONFIG4L~1~4=0x1f,0x3,Write Protect Program Flash Page 3 CONFIG4L~1~5=0x1f,0x4,Write Protect Program Flash Page 4 CONFIG4L~1~6=0x1f,0x5,Write Protect Program Flash Page 5 CONFIG4L~1~7=0x1f,0x6,Write Protect Program Flash Page 6 CONFIG4L~1~8=0x1f,0x7,Write Protect Program Flash Page 7 CONFIG4L~1~9=0x1f,0x8,Write Protect Program Flash Page 8 CONFIG4L~1~10=0x1f,0x9,Write Protect Program Flash Page 9 CONFIG4L~1~11=0x1f,0xa,Write Protect Program Flash Page 10 CONFIG4L~1~12=0x1f,0xb,Write Protect Program Flash Page 11 CONFIG4L~1~13=0x1f,0xc,Write Protect Program Flash Page 12 CONFIG4L~1~14=0x1f,0xd,Write Protect Program Flash Page 13 CONFIG4L~1~15=0x1f,0xe,Write Protect Program Flash Page 14 CONFIG4L~1~16=0x1f,0xf,Write Protect Program Flash Page 15 CONFIG4L~1~17=0x1f,0x10,Write Protect Program Flash Page 16 CONFIG4L~1~18=0x1f,0x11,Write Protect Program Flash Page 17 CONFIG4L~1~19=0x1f,0x12,Write Protect Program Flash Page 18 CONFIG4L~1~20=0x1f,0x13,Write Protect Program Flash Page 19 CONFIG4L~1~21=0x1f,0x14,Write Protect Program Flash Page 20 CONFIG4L~1~22=0x1f,0x15,Write Protect Program Flash Page 21 CONFIG4L~1~23=0x1f,0x16,Write Protect Program Flash Page 22 CONFIG4L~1~24=0x1f,0x17,Write Protect Program Flash Page 23 CONFIG4L~1~25=0x1f,0x18,Write Protect Program Flash Page 24 CONFIG4L~1~26=0x1f,0x19,Write Protect Program Flash Page 25 CONFIG4L~1~27=0x1f,0x1a,Write Protect Program Flash Page 26 CONFIG4L~1~28=0x1f,0x1b,Write Protect Program Flash Page 27 CONFIG4L~1~29=0x1f,0x1c,Write Protect Program Flash Page 28 CONFIG4L~1~30=0x1f,0x1d,Write Protect Program Flash Page 29 CONFIG4L~1~31=0x1f,0x1e,Write Protect Program Flash Page 30 CONFIG4L~1~32=0x1f,0x1f,Write Protect Program Flash Page 31 CONFIG4L~2~1=0x40,0x40,Pages WPFP<5:0> to (Configuration Words page) write/erase protected CONFIG4L~2~2=0x40,0x0,Page 0 to WPFP<5:0> erase/write-protected CONFIG4L~3~1=0x80,0x80,Disabled CONFIG4L~3~2=0x80,0x0,Enabled CONFIG4H_unused=0x0 CONFIG4H~1=WPDIS,0x1,Write Protect Disable bit CONFIG4H~2=RESERVED,0xf0,RESERVED CONFIG4H~1~1=0x1,0x1,Disabled CONFIG4H~1~2=0x1,0x0,Enabled CONFIG4H~2~1=0xf0,0xf0,RESERVED erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F25J50] pgmmem=0x0 ~pgmmem=0x7ff7 cfgmem=0x7ff8 ~cfgmem=0x7fff userid= ~userid= eedata= ~eedata= devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0x4c20 configslots=8 0x7ff8=CONFIG1L 0x7ff9=CONFIG1H 0x7ffa=CONFIG2L 0x7ffb=CONFIG2H 0x7ffc=CONFIG3L 0x7ffd=CONFIG3H 0x7ffe=CONFIG4L 0x7fff=CONFIG4H CONFIG1L_unused=0x0 CONFIG1L~1=WDTEN,0x1,Watchdog Timer CONFIG1L~2=PLLDIV,0xe,PLL Prescaler Selection bits CONFIG1L~3=STVREN,0x20,Stack Overflow/Underflow Reset CONFIG1L~4=XINST,0x40,Extended Instruction Set CONFIG1L~5=DEBUG,0x80,Background Debug CONFIG1L~1~1=0x1,0x1,Enabled CONFIG1L~1~2=0x1,0x0,Disabled CONFIG1L~2~1=0xe,0xe,No prescale (4 MHz oscillator input drives PLL directly) CONFIG1L~2~2=0xe,0xc,Divide by 2 (8 MHz oscillator input) CONFIG1L~2~3=0xe,0xa,Divide by 3 (12 MHz oscillator input) CONFIG1L~2~4=0xe,0x8,Divide by 4 (16 MHz oscillator input) CONFIG1L~2~5=0xe,0x6,Divide by 5 (20 MHz oscillator input) CONFIG1L~2~6=0xe,0x4,Divide by 6 (24 MHz oscillator input) CONFIG1L~2~7=0xe,0x2,Divide by 10 (40 MHz oscillator input) CONFIG1L~2~8=0xe,0x0,Divide by 12 (48 MHz oscillator input) CONFIG1L~3~1=0x20,0x20,Enabled CONFIG1L~3~2=0x20,0x0,Disabled CONFIG1L~4~1=0x40,0x40,Enabled CONFIG1L~4~2=0x40,0x0,Disabled CONFIG1L~5~1=0x80,0x80,Disabled CONFIG1L~5~2=0x80,0x0,Enabled CONFIG1H_unused=0x0 CONFIG1H~1=CPUDIV,0x3,CPU System Clock Postscaler CONFIG1H~2=CP0,0x4,Code Protect CONFIG1H~3=SIGN,0x8,Config Word Signature Bit CONFIG1H~4=RESERVED,0xf0,RESERVED CONFIG1H~1~1=0x3,0x3,No CPU system clock divide CONFIG1H~1~2=0x3,0x2,CPU system clock divide by 2 CONFIG1H~1~3=0x3,0x1,CPU system clock divide by 3 CONFIG1H~1~4=0x3,0x0,CPU system clock divide by 6 CONFIG1H~2~1=0x4,0x4,Disabled CONFIG1H~2~2=0x4,0x0,Enabled CONFIG1H~3~1=0x8,0x8,Bulk erase of memory not conducated CONFIG1H~3~2=0x8,0x0,Bulk erase of memory area complete CONFIG1H~4~1=0xf0,0xf0,RESERVED CONFIG2L_unused=0x0 CONFIG2L~1=OSC,0x7,Oscillator CONFIG2L~2=T1DIG,0x8,T1OSCEN Enforcement CONFIG2L~3=LPT1OSC,0x10,Low-Power Timer1 Oscillator CONFIG2L~4=FCMEN,0x40,Fail-Safe Clock Monitor CONFIG2L~5=IESO,0x80,Internal External Oscillator Switch Over Mode CONFIG2L~1~1=0x7,0x7,EC+PLL (CLKO-RA6), USB-EC+PLL CONFIG2L~1~2=0x7,0x6,EC (CLKO-RA6), USB-EC CONFIG2L~1~3=0x7,0x5,HS+PLL, USB-HS+PLL CONFIG2L~1~4=0x7,0x4,HS, USB-HS CONFIG2L~1~5=0x7,0x3,INTOSCPLLO (CLKO-RA6) CONFIG2L~1~6=0x7,0x2,INTOSCPLL CONFIG2L~1~7=0x7,0x1,INTOSCO (CLKO-RA6) CONFIG2L~1~8=0x7,0x0,INTOSC CONFIG2L~2~1=0x8,0x8,Enabled CONFIG2L~2~2=0x8,0x0,Disabled CONFIG2L~3~1=0x10,0x10,Disabled CONFIG2L~3~2=0x10,0x0,Enabled CONFIG2L~4~1=0x40,0x0,Disabled CONFIG2L~4~2=0x40,0x40,Enabled CONFIG2L~5~1=0x80,0x0,Disabled CONFIG2L~5~2=0x80,0x80,Enabled CONFIG2H_unused=0x0 CONFIG2H~1=WDTPS,0xf,Watchdog Postscaler CONFIG2H~2=RESERVED,0xf0,RESERVED CONFIG2H~1~1=0xf,0xf,1:32768 CONFIG2H~1~2=0xf,0xe,1:16384 CONFIG2H~1~3=0xf,0xd,1:8192 CONFIG2H~1~4=0xf,0xc,1:4096 CONFIG2H~1~5=0xf,0xb,1:2048 CONFIG2H~1~6=0xf,0xa,1:1024 CONFIG2H~1~7=0xf,0x9,1:512 CONFIG2H~1~8=0xf,0x8,1:256 CONFIG2H~1~9=0xf,0x7,1:128 CONFIG2H~1~10=0xf,0x6,1:64 CONFIG2H~1~11=0xf,0x5,1:32 CONFIG2H~1~12=0xf,0x4,1:16 CONFIG2H~1~13=0xf,0x3,1:8 CONFIG2H~1~14=0xf,0x2,1:4 CONFIG2H~1~15=0xf,0x1,1:2 CONFIG2H~1~16=0xf,0x0,1:1 CONFIG2H~2~1=0xf0,0xf0,RESERVED CONFIG3L_unused=0x0 CONFIG3L~1=DSWDTOSC,0x1,DSWDT Clock Select CONFIG3L~2=RTCOSC,0x2,RTCC Clock Select CONFIG3L~3=DSBOREN,0x4,Deep Sleep BOR CONFIG3L~4=DSWDTEN,0x8,Deep Sleep Watchdog Timer CONFIG3L~5=DSWDTPS,0xf0,Deep Sleep Watchdog Postscaler CONFIG3L~1~1=0x1,0x1,DSWDT uses INTRC CONFIG3L~1~2=0x1,0x0,DSWDT uses T1OSC/T1CKI CONFIG3L~2~1=0x2,0x2,RTCC uses T1OSC/T1CKI CONFIG3L~2~2=0x2,0x0,RTCC uses INTRC CONFIG3L~3~1=0x4,0x4,Enabled CONFIG3L~3~2=0x4,0x0,Disabled CONFIG3L~4~1=0x8,0x8,Enabled CONFIG3L~4~2=0x8,0x0,Disabled CONFIG3L~5~1=0xf0,0xf0,1:2,147,483,648 (25.7 days) CONFIG3L~5~2=0xf0,0xe0,1:536,870,912 (6.4 days) CONFIG3L~5~3=0xf0,0xd0,1:134,217,728 (38.5 hours) CONFIG3L~5~4=0xf0,0xc0,1:33,554,432 (9.6 hours) CONFIG3L~5~5=0xf0,0xb0,1:8,388,608 (2.4 hours) CONFIG3L~5~6=0xf0,0xa0,1:2,097,152 (36 minutes) CONFIG3L~5~7=0xf0,0x90,1:524,288 (9 minutes) CONFIG3L~5~8=0xf0,0x80,1:131,072 (135 seconds) CONFIG3L~5~9=0xf0,0x70,1:32,768 (34 seconds) CONFIG3L~5~10=0xf0,0x60,1:8,192 (8.5 seconds) CONFIG3L~5~11=0xf0,0x50,1:2,048 (2.1 seconds) CONFIG3L~5~12=0xf0,0x40,1:512 (528 ms) CONFIG3L~5~13=0xf0,0x30,1:128 (132 ms) CONFIG3L~5~14=0xf0,0x20,1:32 (33 ms) CONFIG3L~5~15=0xf0,0x10,1:8 (8.3 ms) CONFIG3L~5~16=0xf0,0x0,1:2 (2.1 ms) CONFIG3H_unused=0x0 CONFIG3H~1=IOL1WAY,0x1,IOLOCK One-Way Set Enable bit CONFIG3H~2=MSSP7B_EN,0x8,MSSP address masking CONFIG3H~3=RESERVED,0xf0,RESERVED CONFIG3H~1~1=0x1,0x1,Enabled CONFIG3H~1~2=0x1,0x0,Disabled CONFIG3H~2~1=0x8,0x8,7 Bit address masking mode CONFIG3H~2~2=0x8,0x0,5 Bit address masking mode CONFIG3H~3~1=0xf0,0xf0,RESERVED CONFIG4L_unused=0x0 CONFIG4L~1=WPFP,0x0f,Write/Erase Protect Page Start/End Location CONFIG4L~2=WPFP,0x10,Write/Erase Protect Page Start/End Location CONFIG4L~3=WPEND,0x40,Write/Erase Protect Region Select bit (valid when WPDIS = 0) CONFIG4L~4=WPCFG,0x80,Write/Erase Protect Configuration Region CONFIG4L~1~1=0x0f,0x0,Write Protect Program Flash Page 0 CONFIG4L~1~2=0x0f,0x1,Write Protect Program Flash Page 1 CONFIG4L~1~3=0x0f,0x2,Write Protect Program Flash Page 2 CONFIG4L~1~4=0x0f,0x3,Write Protect Program Flash Page 3 CONFIG4L~1~5=0x0f,0x4,Write Protect Program Flash Page 4 CONFIG4L~1~6=0x0f,0x5,Write Protect Program Flash Page 5 CONFIG4L~1~7=0x0f,0x6,Write Protect Program Flash Page 6 CONFIG4L~1~8=0x0f,0x7,Write Protect Program Flash Page 7 CONFIG4L~1~9=0x0f,0x8,Write Protect Program Flash Page 8 CONFIG4L~1~10=0x0f,0x9,Write Protect Program Flash Page 9 CONFIG4L~1~11=0x0f,0xa,Write Protect Program Flash Page 10 CONFIG4L~1~12=0x0f,0xb,Write Protect Program Flash Page 11 CONFIG4L~1~13=0x0f,0xc,Write Protect Program Flash Page 12 CONFIG4L~1~14=0x0f,0xd,Write Protect Program Flash Page 13 CONFIG4L~1~15=0x0f,0xe,Write Protect Program Flash Page 14 CONFIG4L~1~16=0x0f,0xf,Write Protect Program Flash Page 15 CONFIG4L~2~1=0x10,0x00,Flash Page 0 - 15 CONFIG4L~2~2=0x10,0x10,Flash Page 16 - 31 CONFIG4L~3~1=0x40,0x40,Pages WPFP<5:0> to (Configuration Words page) write/erase protected CONFIG4L~3~2=0x40,0x0,Page 0 to WPFP<5:0> erase/write-protected CONFIG4L~4~1=0x80,0x80,Disabled CONFIG4L~4~2=0x80,0x0,Enabled CONFIG4H_unused=0x0 CONFIG4H~1=WPDIS,0x1,Write Protect Disable bit CONFIG4H~2=RESERVED,0xf0,RESERVED CONFIG4H~1~1=0x1,0x1,Disabled CONFIG4H~1~2=0x1,0x0,Enabled CONFIG4H~2~1=0xf0,0xf0,RESERVED erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F2681] pgmmem=0x0 ~pgmmem=0xFFFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata= ~eedata= devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x0E40 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000a= 0x30000b= 0x30000c= 0x30000d= CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xC,0xC,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xA,0xA,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xF,0x5,EC-Port on RA6 CONFIG1H~1~8=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xF,0x3,EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xF,0x2,HS CONFIG1H~1~11=0xF,0x1,XT CONFIG1H~1~12=0xF,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x08,4.2V CONFIG2L~3~4=0x18,0x00,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=PBADEN,0x2,PortB A/D Enable CONFIG3H~2=LPT1OSC,0x04,Low Power Timer1 Osc enable CONFIG3H~3=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x2,0x2,PORTB<4> and <1:0> configured as analog inputs on RESET CONFIG3H~1~2=0x2,0x0,PORTB<4> and <1:0> configured as digital I/O on RESET CONFIG3H~2~1=0x04,0x04,Enabled CONFIG3H~2~2=0x04,0x00,Disabled CONFIG3H~3~1=0x80,0x80,MCLR Enabled,RE3 Disabled CONFIG3H~3~2=0x80,0x00,MCLR Disabled, RE3 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=ENHCPU,0x40,Extended CPU Enable CONFIG4L~4=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x40,0x40,Enabled CONFIG4L~3~2=0x40,0x00,Disabled CONFIG4L~4~1=0x80,0x80,Disabled CONFIG4L~4~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-03FFF CONFIG5L~2=CP_1,0x2,Code Protect 04000-07FFF CONFIG5L~3=CP_2,0x4,Code Protect 08000-0BFFF CONFIG5L~4=CP_3,0x8,Code Protect 0C000-0FFFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EE Read Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F26J11] pgmmem=0x0 ~pgmmem=0xfff7 cfgmem=0xfff8 ~cfgmem=0xffff userid= ~userid= eedata= ~eedata= devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0x4dc0 configslots=8 0xfff8=CONFIG1L 0xfff9=CONFIG1H 0xfffa=CONFIG2L 0xfffb=CONFIG2H 0xfffc=CONFIG3L 0xfffd=CONFIG3H 0xfffe=CONFIG4L 0xffff=CONFIG4H CONFIG1L_unused=0x0 CONFIG1L~1=WDTEN,0x1,Watchdog Timer CONFIG1L~2=STVREN,0x20,Stack Overflow/Underflow Reset CONFIG1L~3=XINST,0x40,Extended Instruction Set CONFIG1L~4=DEBUG,0x80,Background Debug CONFIG1L~1~1=0x1,0x1,Enabled CONFIG1L~1~2=0x1,0x0,Disabled CONFIG1L~2~1=0x20,0x20,Enabled CONFIG1L~2~2=0x20,0x0,Disabled CONFIG1L~3~1=0x40,0x40,Enabled CONFIG1L~3~2=0x40,0x0,Disabled CONFIG1L~4~1=0x80,0x80,Disabled CONFIG1L~4~2=0x80,0x0,Enabled CONFIG1H_unused=0x0 CONFIG1H~1=CP0,0x4,Code Protect CONFIG1H~2=SIGN,0x8,Config Word Signature Bit CONFIG1H~3=RESERVED,0xf0,RESERVED CONFIG1H~1~1=0x4,0x4,Disabled CONFIG1H~1~2=0x4,0x0,Enabled CONFIG1H~2~1=0x8,0x8,Bulk erase of memory not conducated CONFIG1H~2~2=0x8,0x0,Bulk erase of memory area complete CONFIG1H~3~1=0xf0,0xf0,RESERVED CONFIG2L_unused=0x0 CONFIG2L~1=OSC,0x7,Oscillator CONFIG2L~2=T1DIG,0x8,T1OSCEN Enforcement CONFIG2L~3=LPT1OSC,0x10,Low-Power Timer1 Oscillator CONFIG2L~4=FCMEN,0x40,Fail-Safe Clock Monitor CONFIG2L~5=IESO,0x80,Internal External Oscillator Switch Over Mode CONFIG2L~1~1=0x7,0x7,EC+PLL (CLKO-RA6) CONFIG2L~1~2=0x7,0x6,EC (CLKO-RA6) CONFIG2L~1~3=0x7,0x5,HS+PLL CONFIG2L~1~4=0x7,0x4,HS CONFIG2L~1~5=0x7,0x3,INTOSCPLLO (CLKO-RA6) CONFIG2L~1~6=0x7,0x2,INTOSCPLL CONFIG2L~1~7=0x7,0x1,INTOSCO (CLKO-RA6) CONFIG2L~1~8=0x7,0x0,INTOSC CONFIG2L~2~1=0x8,0x8,Enabled CONFIG2L~2~2=0x8,0x0,Disabled CONFIG2L~3~1=0x10,0x10,Disabled CONFIG2L~3~2=0x10,0x0,Enabled CONFIG2L~4~1=0x40,0x0,Disabled CONFIG2L~4~2=0x40,0x40,Enabled CONFIG2L~5~1=0x80,0x0,Disabled CONFIG2L~5~2=0x80,0x80,Enabled CONFIG2H_unused=0x0 CONFIG2H~1=WDTPS,0xf,Watchdog Postscaler CONFIG2H~2=RESERVED,0xf0,RESERVED CONFIG2H~1~1=0xf,0xf,1:32768 CONFIG2H~1~2=0xf,0xe,1:16384 CONFIG2H~1~3=0xf,0xd,1:8192 CONFIG2H~1~4=0xf,0xc,1:4096 CONFIG2H~1~5=0xf,0xb,1:2048 CONFIG2H~1~6=0xf,0xa,1:1024 CONFIG2H~1~7=0xf,0x9,1:512 CONFIG2H~1~8=0xf,0x8,1:256 CONFIG2H~1~9=0xf,0x7,1:128 CONFIG2H~1~10=0xf,0x6,1:64 CONFIG2H~1~11=0xf,0x5,1:32 CONFIG2H~1~12=0xf,0x4,1:16 CONFIG2H~1~13=0xf,0x3,1:8 CONFIG2H~1~14=0xf,0x2,1:4 CONFIG2H~1~15=0xf,0x1,1:2 CONFIG2H~1~16=0xf,0x0,1:1 CONFIG2H~2~1=0xf0,0xf0,RESERVED CONFIG3L_unused=0x0 CONFIG3L~1=DSWDTOSC,0x1,DSWDT Clock Select CONFIG3L~2=RTCOSC,0x2,RTCC Clock Select CONFIG3L~3=DSBOREN,0x4,Deep Sleep BOR CONFIG3L~4=DSWDTEN,0x8,Deep Sleep Watchdog Timer CONFIG3L~5=DSWDTPS,0xf0,Deep Sleep Watchdog Postscaler CONFIG3L~1~1=0x1,0x1,DSWDT uses INTRC CONFIG3L~1~2=0x1,0x0,DSWDT uses T1OSC/T1CKI CONFIG3L~2~1=0x2,0x2,RTCC uses T1OSC/T1CKI CONFIG3L~2~2=0x2,0x0,RTCC uses INTRC CONFIG3L~3~1=0x4,0x4,Enabled CONFIG3L~3~2=0x4,0x0,Disabled CONFIG3L~4~1=0x8,0x8,Enabled CONFIG3L~4~2=0x8,0x0,Disabled CONFIG3L~5~1=0xf0,0xf0,1:2,147,483,648 (25.7 days) CONFIG3L~5~2=0xf0,0xe0,1:536,870,912 (6.4 days) CONFIG3L~5~3=0xf0,0xd0,1:134,217,728 (38.5 hours) CONFIG3L~5~4=0xf0,0xc0,1:33,554,432 (9.6 hours) CONFIG3L~5~5=0xf0,0xb0,1:8,388,608 (2.4 hours) CONFIG3L~5~6=0xf0,0xa0,1:2,097,152 (36 minutes) CONFIG3L~5~7=0xf0,0x90,1:524,288 (9 minutes) CONFIG3L~5~8=0xf0,0x80,1:131,072 (135 seconds) CONFIG3L~5~9=0xf0,0x70,1:32,768 (34 seconds) CONFIG3L~5~10=0xf0,0x60,1:8,192 (8.5 seconds) CONFIG3L~5~11=0xf0,0x50,1:2,048 (2.1 seconds) CONFIG3L~5~12=0xf0,0x40,1:512 (528 ms) CONFIG3L~5~13=0xf0,0x30,1:128 (132 ms) CONFIG3L~5~14=0xf0,0x20,1:32 (33 ms) CONFIG3L~5~15=0xf0,0x10,1:8 (8.3 ms) CONFIG3L~5~16=0xf0,0x0,1:2 (2.1 ms) CONFIG3H_unused=0x0 CONFIG3H~1=IOL1WAY,0x1,IOLOCK One-Way Set Enable bit CONFIG3H~2=MSSP7B_EN,0x8,MSSP address masking CONFIG3H~3=RESERVED,0xf0,RESERVED CONFIG3H~1~1=0x1,0x1,Enabled CONFIG3H~1~2=0x1,0x0,Disabled CONFIG3H~2~1=0x8,0x8,7 Bit address masking mode CONFIG3H~2~2=0x8,0x0,5 Bit address masking mode CONFIG3H~3~1=0xf0,0xf0,RESERVED CONFIG4L_unused=0x0 CONFIG4L~1=WPFP,0x3f,Write/Erase Protect Page Start/End Location CONFIG4L~2=WPEND,0x40,Write/Erase Protect Region Select bit (valid when WPDIS = 0) CONFIG4L~3=WPCFG,0x80,Write/Erase Protect Configuration Region CONFIG4L~1~1=0x3f,0x0,Write Protect Program Flash Page 0 CONFIG4L~1~2=0x3f,0x1,Write Protect Program Flash Page 1 CONFIG4L~1~3=0x3f,0x2,Write Protect Program Flash Page 2 CONFIG4L~1~4=0x3f,0x3,Write Protect Program Flash Page 3 CONFIG4L~1~5=0x3f,0x4,Write Protect Program Flash Page 4 CONFIG4L~1~6=0x3f,0x5,Write Protect Program Flash Page 5 CONFIG4L~1~7=0x3f,0x6,Write Protect Program Flash Page 6 CONFIG4L~1~8=0x3f,0x7,Write Protect Program Flash Page 7 CONFIG4L~1~9=0x3f,0x8,Write Protect Program Flash Page 8 CONFIG4L~1~10=0x3f,0x9,Write Protect Program Flash Page 9 CONFIG4L~1~11=0x3f,0xa,Write Protect Program Flash Page 10 CONFIG4L~1~12=0x3f,0xb,Write Protect Program Flash Page 11 CONFIG4L~1~13=0x3f,0xc,Write Protect Program Flash Page 12 CONFIG4L~1~14=0x3f,0xd,Write Protect Program Flash Page 13 CONFIG4L~1~15=0x3f,0xe,Write Protect Program Flash Page 14 CONFIG4L~1~16=0x3f,0xf,Write Protect Program Flash Page 15 CONFIG4L~1~17=0x3f,0x10,Write Protect Program Flash Page 16 CONFIG4L~1~18=0x3f,0x11,Write Protect Program Flash Page 17 CONFIG4L~1~19=0x3f,0x12,Write Protect Program Flash Page 18 CONFIG4L~1~20=0x3f,0x13,Write Protect Program Flash Page 19 CONFIG4L~1~21=0x3f,0x14,Write Protect Program Flash Page 20 CONFIG4L~1~22=0x3f,0x15,Write Protect Program Flash Page 21 CONFIG4L~1~23=0x3f,0x16,Write Protect Program Flash Page 22 CONFIG4L~1~24=0x3f,0x17,Write Protect Program Flash Page 23 CONFIG4L~1~25=0x3f,0x18,Write Protect Program Flash Page 24 CONFIG4L~1~26=0x3f,0x19,Write Protect Program Flash Page 25 CONFIG4L~1~27=0x3f,0x1a,Write Protect Program Flash Page 26 CONFIG4L~1~28=0x3f,0x1b,Write Protect Program Flash Page 27 CONFIG4L~1~29=0x3f,0x1c,Write Protect Program Flash Page 28 CONFIG4L~1~30=0x3f,0x1d,Write Protect Program Flash Page 29 CONFIG4L~1~31=0x3f,0x1e,Write Protect Program Flash Page 30 CONFIG4L~1~32=0x3f,0x1f,Write Protect Program Flash Page 31 CONFIG4L~1~33=0x3f,0x20,Write Protect Program Flash Page 32 CONFIG4L~1~34=0x3f,0x21,Write Protect Program Flash Page 33 CONFIG4L~1~35=0x3f,0x22,Write Protect Program Flash Page 34 CONFIG4L~1~36=0x3f,0x23,Write Protect Program Flash Page 35 CONFIG4L~1~37=0x3f,0x24,Write Protect Program Flash Page 36 CONFIG4L~1~38=0x3f,0x25,Write Protect Program Flash Page 37 CONFIG4L~1~39=0x3f,0x26,Write Protect Program Flash Page 38 CONFIG4L~1~40=0x3f,0x27,Write Protect Program Flash Page 39 CONFIG4L~1~41=0x3f,0x28,Write Protect Program Flash Page 40 CONFIG4L~1~42=0x3f,0x29,Write Protect Program Flash Page 41 CONFIG4L~1~43=0x3f,0x2a,Write Protect Program Flash Page 42 CONFIG4L~1~44=0x3f,0x2b,Write Protect Program Flash Page 43 CONFIG4L~1~45=0x3f,0x2c,Write Protect Program Flash Page 44 CONFIG4L~1~46=0x3f,0x2d,Write Protect Program Flash Page 45 CONFIG4L~1~47=0x3f,0x2e,Write Protect Program Flash Page 46 CONFIG4L~1~48=0x3f,0x2f,Write Protect Program Flash Page 47 CONFIG4L~1~49=0x3f,0x30,Write Protect Program Flash Page 48 CONFIG4L~1~50=0x3f,0x31,Write Protect Program Flash Page 49 CONFIG4L~1~51=0x3f,0x32,Write Protect Program Flash Page 50 CONFIG4L~1~52=0x3f,0x33,Write Protect Program Flash Page 51 CONFIG4L~1~53=0x3f,0x34,Write Protect Program Flash Page 52 CONFIG4L~1~54=0x3f,0x35,Write Protect Program Flash Page 53 CONFIG4L~1~55=0x3f,0x36,Write Protect Program Flash Page 54 CONFIG4L~1~56=0x3f,0x37,Write Protect Program Flash Page 55 CONFIG4L~1~57=0x3f,0x38,Write Protect Program Flash Page 56 CONFIG4L~1~58=0x3f,0x39,Write Protect Program Flash Page 57 CONFIG4L~1~59=0x3f,0x3a,Write Protect Program Flash Page 58 CONFIG4L~1~60=0x3f,0x3b,Write Protect Program Flash Page 59 CONFIG4L~1~61=0x3f,0x3c,Write Protect Program Flash Page 60 CONFIG4L~1~62=0x3f,0x3d,Write Protect Program Flash Page 61 CONFIG4L~1~63=0x3f,0x3e,Write Protect Program Flash Page 62 CONFIG4L~1~64=0x3f,0x3f,Write Protect Program Flash Page 63 CONFIG4L~2~1=0x40,0x40,Pages WPFP<5:0> to (Configuration Words page) write/erase protected CONFIG4L~2~2=0x40,0x0,Page 0 to WPFP<5:0> erase/write-protected CONFIG4L~3~1=0x80,0x80,Disabled CONFIG4L~3~2=0x80,0x0,Enabled CONFIG4H_unused=0x0 CONFIG4H~1=WPDIS,0x1,Write Protect Disable bit CONFIG4H~2=RESERVED,0xf0,RESERVED CONFIG4H~1~1=0x1,0x1,Disabled CONFIG4H~1~2=0x1,0x0,Enabled CONFIG4H~2~1=0xf0,0xf0,RESERVED erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F26J13] pgmmem=0x0 ~pgmmem=0xfff7 cfgmem=0xfff8 ~cfgmem=0xffff userid= ~userid= eedata= ~eedata= devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0x5920 configslots=8 0xfff8=CONFIG1L 0xfff9=CONFIG1H 0xfffa=CONFIG2L 0xfffb=CONFIG2H 0xfffc=CONFIG3L 0xfffd=CONFIG3H 0xfffe=CONFIG4L 0xffff=CONFIG4H CONFIG1L_unused=0x0 CONFIG1L~1=WDTEN,0x1,Watchdog Timer CONFIG1L~2=PLLDIV,0xe,PLL Prescaler Selection bits (PLLSEL = 0) CONFIG1L~3=CFGPLLEN,0x10,PLL Configuration Enable Bit CONFIG1L~4=STVREN,0x20,Stack Overflow/Underflow Reset CONFIG1L~5=XINST,0x40,Extended Instruction Set CONFIG1L~6=DEBUG,0x80,Background Debug CONFIG1L~1~1=0x1,0x1,Enabled CONFIG1L~1~2=0x1,0x0,Disabled CONFIG1L~2~1=0xe,0xe,No prescale (4 MHz oscillator input drives PLL directly) CONFIG1L~2~2=0xe,0xc,Divide by 2 (8 MHz oscillator input) CONFIG1L~2~3=0xe,0xa,Divide by 3 (12 MHz oscillator input) CONFIG1L~2~4=0xe,0x8,Divide by 4 (16 MHz oscillator input) CONFIG1L~2~5=0xe,0x6,Divide by 5 (20 MHz oscillator input) CONFIG1L~2~6=0xe,0x4,Divide by 6 (24 MHz oscillator input) CONFIG1L~2~7=0xe,0x2,Divide by 10 (40 MHz oscillator input) CONFIG1L~2~8=0xe,0x0,Divide by 12 (48 MHz oscillator input) CONFIG1L~3~1=0x10,0x10,Enabled CONFIG1L~3~2=0x10,0x0,Disabled CONFIG1L~4~1=0x20,0x20,Enabled CONFIG1L~4~2=0x20,0x0,Disabled CONFIG1L~5~1=0x40,0x40,Enabled CONFIG1L~5~2=0x40,0x0,Disabled CONFIG1L~6~1=0x80,0x80,Disabled CONFIG1L~6~2=0x80,0x0,Enabled CONFIG1H_unused=0x0 CONFIG1H~1=CP0,0x4,Code Protect CONFIG1H~2=SIGN,0x8,Config Word Signature Bit CONFIG1H~3=RESERVED,0xf0,RESERVED CONFIG1H~1~1=0x4,0x4,Disabled CONFIG1H~1~2=0x4,0x0,Enabled CONFIG1H~2~1=0x8,0x8,Bulk erase of memory not conducated CONFIG1H~2~2=0x8,0x0,Bulk erase of memory area complete CONFIG1H~3~1=0xf0,0xf0,RESERVED CONFIG2L_unused=0x0 CONFIG2L~1=OSC,0x7,Oscillator CONFIG2L~2=SOSCSEL,0x18,T1OSC/SOSC Power Selection Bits CONFIG2L~3=CLKOEC,0x20,EC Clock Out Enable Bit CONFIG2L~4=FCMEN,0x40,Fail-Safe Clock Monitor CONFIG2L~5=IESO,0x80,Internal External Oscillator Switch Over Mode CONFIG2L~1~1=0x7,0x7,EC+PLL (CLKO-RA6), USB-EC+PLL CONFIG2L~1~2=0x7,0x6,EC (CLKO-RA6), USB-EC CONFIG2L~1~3=0x7,0x5,HS+PLL, USB-HS+PLL CONFIG2L~1~4=0x7,0x4,HS, USB-HS CONFIG2L~1~5=0x7,0x3,INTOSCPLLO (CLKO-RA6) CONFIG2L~1~6=0x7,0x2,INTOSCPLL CONFIG2L~1~7=0x7,0x1,INTOSCO (CLKO-RA6) CONFIG2L~1~8=0x7,0x0,INTOSC CONFIG2L~2~1=0x18,0x18,High Security Code Protection Enable CONFIG2L~2~2=0x18,0x10,Digital (SCLKI) mode selected CONFIG2L~2~3=0x18,0x8,Low Power T1OSC/SOSC circuit selected CONFIG2L~2~4=0x18,0x0,Reserved CONFIG2L~3~1=0x20,0x20,Enabled CONFIG2L~3~2=0x20,0x0,Disabled CONFIG2L~4~1=0x40,0x0,Disabled CONFIG2L~4~2=0x40,0x40,Enabled CONFIG2L~5~1=0x80,0x0,Disabled CONFIG2L~5~2=0x80,0x80,Enabled CONFIG2H_unused=0x0 CONFIG2H~1=WDTPS,0xf,Watchdog Postscaler CONFIG2H~2=RESERVED,0xf0,RESERVED CONFIG2H~1~1=0xf,0xf,1:32768 CONFIG2H~1~2=0xf,0xe,1:16384 CONFIG2H~1~3=0xf,0xd,1:8192 CONFIG2H~1~4=0xf,0xc,1:4096 CONFIG2H~1~5=0xf,0xb,1:2048 CONFIG2H~1~6=0xf,0xa,1:1024 CONFIG2H~1~7=0xf,0x9,1:512 CONFIG2H~1~8=0xf,0x8,1:256 CONFIG2H~1~9=0xf,0x7,1:128 CONFIG2H~1~10=0xf,0x6,1:64 CONFIG2H~1~11=0xf,0x5,1:32 CONFIG2H~1~12=0xf,0x4,1:16 CONFIG2H~1~13=0xf,0x3,1:8 CONFIG2H~1~14=0xf,0x2,1:4 CONFIG2H~1~15=0xf,0x1,1:2 CONFIG2H~1~16=0xf,0x0,1:1 CONFIG2H~2~1=0xf0,0xf0,RESERVED CONFIG3L_unused=0x0 CONFIG3L~1=DSWDTOSC,0x1,DSWDT Clock Select CONFIG3L~2=RTCOSC,0x2,RTCC Clock Select CONFIG3L~3=DSBOREN,0x4,Deep Sleep BOR CONFIG3L~4=DSWDTEN,0x8,Deep Sleep Watchdog Timer CONFIG3L~5=DSWDTPS,0xf0,Deep Sleep Watchdog Postscaler CONFIG3L~1~1=0x1,0x1,DSWDT uses INTRC CONFIG3L~1~2=0x1,0x0,DSWDT uses T1OSC/T1CKI CONFIG3L~2~1=0x2,0x2,RTCC uses T1OSC/T1CKI CONFIG3L~2~2=0x2,0x0,RTCC uses INTRC CONFIG3L~3~1=0x4,0x4,Enabled CONFIG3L~3~2=0x4,0x0,Disabled CONFIG3L~4~1=0x8,0x8,Enabled CONFIG3L~4~2=0x8,0x0,Disabled CONFIG3L~5~1=0xf0,0xf0,1:2,147,483,648 (25.7 days) CONFIG3L~5~2=0xf0,0xe0,1:536,870,912 (6.4 days) CONFIG3L~5~3=0xf0,0xd0,1:134,217,728 (38.5 hours) CONFIG3L~5~4=0xf0,0xc0,1:33,554,432 (9.6 hours) CONFIG3L~5~5=0xf0,0xb0,1:8,388,608 (2.4 hours) CONFIG3L~5~6=0xf0,0xa0,1:2,097,152 (36 minutes) CONFIG3L~5~7=0xf0,0x90,1:524,288 (9 minutes) CONFIG3L~5~8=0xf0,0x80,1:131,072 (135 seconds) CONFIG3L~5~9=0xf0,0x70,1:32,768 (34 seconds) CONFIG3L~5~10=0xf0,0x60,1:8,192 (8.5 seconds) CONFIG3L~5~11=0xf0,0x50,1:2,048 (2.1 seconds) CONFIG3L~5~12=0xf0,0x40,1:512 (528 ms) CONFIG3L~5~13=0xf0,0x30,1:128 (132 ms) CONFIG3L~5~14=0xf0,0x20,1:32 (33 ms) CONFIG3L~5~15=0xf0,0x10,1:8 (8.3 ms) CONFIG3L~5~16=0xf0,0x0,1:2 (2.1 ms) CONFIG3H_unused=0x0 CONFIG3H~1=IOL1WAY,0x1,IOLOCK One-Way Set Enable bit CONFIG3H~2=ADCSEL,0x2,ADC 10 or 12 Bit Select CONFIG3H~3=PLLSEL,0x4,PLL Selection Bit CONFIG3H~4=MSSP7B_EN,0x8,MSSP address masking CONFIG3H~5=RESERVED,0xf0,RESERVED CONFIG3H~1~1=0x1,0x1,Enabled CONFIG3H~1~2=0x1,0x0,Disabled CONFIG3H~2~1=0x2,0x2,10 - Bit ADC Enabled CONFIG3H~2~2=0x2,0x0,12 - Bit ADC Enabed CONFIG3H~3~1=0x4,0x0,Selects 96MHz PLL CONFIG3H~3~2=0x4,0x4,Selects 4x PLL CONFIG3H~4~1=0x8,0x8,7 Bit address masking mode CONFIG3H~4~2=0x8,0x0,5 Bit address masking mode CONFIG3H~5~1=0xf0,0xf0,RESERVED CONFIG4L_unused=0x0 CONFIG4L~1=WPFP,0x3f,Write/Erase Protect Page Start/End Location CONFIG4L~2=WPCFG,0x80,Write/Erase Protect Configuration Region CONFIG4L~1~1=0x3f,0x0,Write Protect Program Flash Page 0 CONFIG4L~1~2=0x3f,0x1,Write Protect Program Flash Page 1 CONFIG4L~1~3=0x3f,0x2,Write Protect Program Flash Page 2 CONFIG4L~1~4=0x3f,0x3,Write Protect Program Flash Page 3 CONFIG4L~1~5=0x3f,0x4,Write Protect Program Flash Page 4 CONFIG4L~1~6=0x3f,0x5,Write Protect Program Flash Page 5 CONFIG4L~1~7=0x3f,0x6,Write Protect Program Flash Page 6 CONFIG4L~1~8=0x3f,0x7,Write Protect Program Flash Page 7 CONFIG4L~1~9=0x3f,0x8,Write Protect Program Flash Page 8 CONFIG4L~1~10=0x3f,0x9,Write Protect Program Flash Page 9 CONFIG4L~1~11=0x3f,0xa,Write Protect Program Flash Page 10 CONFIG4L~1~12=0x3f,0xb,Write Protect Program Flash Page 11 CONFIG4L~1~13=0x3f,0xc,Write Protect Program Flash Page 12 CONFIG4L~1~14=0x3f,0xd,Write Protect Program Flash Page 13 CONFIG4L~1~15=0x3f,0xe,Write Protect Program Flash Page 14 CONFIG4L~1~16=0x3f,0xf,Write Protect Program Flash Page 15 CONFIG4L~1~17=0x3f,0x10,Write Protect Program Flash Page 16 CONFIG4L~1~18=0x3f,0x11,Write Protect Program Flash Page 17 CONFIG4L~1~19=0x3f,0x12,Write Protect Program Flash Page 18 CONFIG4L~1~20=0x3f,0x13,Write Protect Program Flash Page 19 CONFIG4L~1~21=0x3f,0x14,Write Protect Program Flash Page 20 CONFIG4L~1~22=0x3f,0x15,Write Protect Program Flash Page 21 CONFIG4L~1~23=0x3f,0x16,Write Protect Program Flash Page 22 CONFIG4L~1~24=0x3f,0x17,Write Protect Program Flash Page 23 CONFIG4L~1~25=0x3f,0x18,Write Protect Program Flash Page 24 CONFIG4L~1~26=0x3f,0x19,Write Protect Program Flash Page 25 CONFIG4L~1~27=0x3f,0x1a,Write Protect Program Flash Page 26 CONFIG4L~1~28=0x3f,0x1b,Write Protect Program Flash Page 27 CONFIG4L~1~29=0x3f,0x1c,Write Protect Program Flash Page 28 CONFIG4L~1~30=0x3f,0x1d,Write Protect Program Flash Page 29 CONFIG4L~1~31=0x3f,0x1e,Write Protect Program Flash Page 30 CONFIG4L~1~32=0x3f,0x1f,Write Protect Program Flash Page 31 CONFIG4L~1~33=0x3f,0x20,Write Protect Program Flash Page 32 CONFIG4L~1~34=0x3f,0x21,Write Protect Program Flash Page 33 CONFIG4L~1~35=0x3f,0x22,Write Protect Program Flash Page 34 CONFIG4L~1~36=0x3f,0x23,Write Protect Program Flash Page 35 CONFIG4L~1~37=0x3f,0x24,Write Protect Program Flash Page 36 CONFIG4L~1~38=0x3f,0x25,Write Protect Program Flash Page 37 CONFIG4L~1~39=0x3f,0x26,Write Protect Program Flash Page 38 CONFIG4L~1~40=0x3f,0x27,Write Protect Program Flash Page 39 CONFIG4L~1~41=0x3f,0x28,Write Protect Program Flash Page 40 CONFIG4L~1~42=0x3f,0x29,Write Protect Program Flash Page 41 CONFIG4L~1~43=0x3f,0x2a,Write Protect Program Flash Page 42 CONFIG4L~1~44=0x3f,0x2b,Write Protect Program Flash Page 43 CONFIG4L~1~45=0x3f,0x2c,Write Protect Program Flash Page 44 CONFIG4L~1~46=0x3f,0x2d,Write Protect Program Flash Page 45 CONFIG4L~1~47=0x3f,0x2e,Write Protect Program Flash Page 46 CONFIG4L~1~48=0x3f,0x2f,Write Protect Program Flash Page 47 CONFIG4L~1~49=0x3f,0x30,Write Protect Program Flash Page 48 CONFIG4L~1~50=0x3f,0x31,Write Protect Program Flash Page 49 CONFIG4L~1~51=0x3f,0x32,Write Protect Program Flash Page 50 CONFIG4L~1~52=0x3f,0x33,Write Protect Program Flash Page 51 CONFIG4L~1~53=0x3f,0x34,Write Protect Program Flash Page 52 CONFIG4L~1~54=0x3f,0x35,Write Protect Program Flash Page 53 CONFIG4L~1~55=0x3f,0x36,Write Protect Program Flash Page 54 CONFIG4L~1~56=0x3f,0x37,Write Protect Program Flash Page 55 CONFIG4L~1~57=0x3f,0x38,Write Protect Program Flash Page 56 CONFIG4L~1~58=0x3f,0x39,Write Protect Program Flash Page 57 CONFIG4L~1~59=0x3f,0x3a,Write Protect Program Flash Page 58 CONFIG4L~1~60=0x3f,0x3b,Write Protect Program Flash Page 59 CONFIG4L~1~61=0x3f,0x3c,Write Protect Program Flash Page 60 CONFIG4L~1~62=0x3f,0x3d,Write Protect Program Flash Page 61 CONFIG4L~1~63=0x3f,0x3e,Write Protect Program Flash Page 62 CONFIG4L~1~64=0x3f,0x3f,Write Protect Program Flash Page 63 CONFIG4L~2~1=0x80,0x80,Disabled CONFIG4L~2~2=0x80,0x0,Enabled CONFIG4H_unused=0x0 CONFIG4H~1=WPDIS,0x1,Write Protect Disable bit CONFIG4H~2=WPEND,0x2,Write/Erase Protect Region Select bit (valid when WPDIS = 0) CONFIG4H~3=RESERVED,0xf0,RESERVED CONFIG4H~1~1=0x1,0x1,Disabled CONFIG4H~1~2=0x1,0x0,Enabled CONFIG4H~2~1=0x2,0x2,Pages WPFP<6:0> to (Configuration Words page) write/erase protected CONFIG4H~2~2=0x2,0x0,Page 0 to WPFP<6:0> erase/write-protected CONFIG4H~3~1=0xf0,0xf0,RESERVED erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F26J50] pgmmem=0x0 ~pgmmem=0xfff7 cfgmem=0xfff8 ~cfgmem=0xffff userid= ~userid= eedata= ~eedata= devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0x4c40 configslots=8 0xfff8=CONFIG1L 0xfff9=CONFIG1H 0xfffa=CONFIG2L 0xfffb=CONFIG2H 0xfffc=CONFIG3L 0xfffd=CONFIG3H 0xfffe=CONFIG4L 0xffff=CONFIG4H CONFIG1L_unused=0x0 CONFIG1L~1=WDTEN,0x1,Watchdog Timer CONFIG1L~2=PLLDIV,0xe,PLL Prescaler Selection bits CONFIG1L~3=STVREN,0x20,Stack Overflow/Underflow Reset CONFIG1L~4=XINST,0x40,Extended Instruction Set CONFIG1L~5=DEBUG,0x80,Background Debug CONFIG1L~1~1=0x1,0x1,Enabled CONFIG1L~1~2=0x1,0x0,Disabled CONFIG1L~2~1=0xe,0xe,No prescale (4 MHz oscillator input drives PLL directly) CONFIG1L~2~2=0xe,0xc,Divide by 2 (8 MHz oscillator input) CONFIG1L~2~3=0xe,0xa,Divide by 3 (12 MHz oscillator input) CONFIG1L~2~4=0xe,0x8,Divide by 4 (16 MHz oscillator input) CONFIG1L~2~5=0xe,0x6,Divide by 5 (20 MHz oscillator input) CONFIG1L~2~6=0xe,0x4,Divide by 6 (24 MHz oscillator input) CONFIG1L~2~7=0xe,0x2,Divide by 10 (40 MHz oscillator input) CONFIG1L~2~8=0xe,0x0,Divide by 12 (48 MHz oscillator input) CONFIG1L~3~1=0x20,0x20,Enabled CONFIG1L~3~2=0x20,0x0,Disabled CONFIG1L~4~1=0x40,0x40,Enabled CONFIG1L~4~2=0x40,0x0,Disabled CONFIG1L~5~1=0x80,0x80,Disabled CONFIG1L~5~2=0x80,0x0,Enabled CONFIG1H_unused=0x0 CONFIG1H~1=CPUDIV,0x3,CPU System Clock Postscaler CONFIG1H~2=CP0,0x4,Code Protect CONFIG1H~3=SIGN,0x8,Config Word Signature Bit CONFIG1H~4=RESERVED,0xf0,RESERVED CONFIG1H~1~1=0x3,0x3,No CPU system clock divide CONFIG1H~1~2=0x3,0x2,CPU system clock divide by 2 CONFIG1H~1~3=0x3,0x1,CPU system clock divide by 3 CONFIG1H~1~4=0x3,0x0,CPU system clock divide by 6 CONFIG1H~2~1=0x4,0x4,Disabled CONFIG1H~2~2=0x4,0x0,Enabled CONFIG1H~3~1=0x8,0x8,Bulk erase of memory not conducated CONFIG1H~3~2=0x8,0x0,Bulk erase of memory area complete CONFIG1H~4~1=0xf0,0xf0,RESERVED CONFIG2L_unused=0x0 CONFIG2L~1=OSC,0x7,Oscillator CONFIG2L~2=T1DIG,0x8,T1OSCEN Enforcement CONFIG2L~3=LPT1OSC,0x10,Low-Power Timer1 Oscillator CONFIG2L~4=FCMEN,0x40,Fail-Safe Clock Monitor CONFIG2L~5=IESO,0x80,Internal External Oscillator Switch Over Mode CONFIG2L~1~1=0x7,0x7,EC+PLL (CLKO-RA6), USB-EC+PLL CONFIG2L~1~2=0x7,0x6,EC (CLKO-RA6), USB-EC CONFIG2L~1~3=0x7,0x5,HS+PLL, USB-HS+PLL CONFIG2L~1~4=0x7,0x4,HS, USB-HS CONFIG2L~1~5=0x7,0x3,INTOSCPLLO (CLKO-RA6) CONFIG2L~1~6=0x7,0x2,INTOSCPLL CONFIG2L~1~7=0x7,0x1,INTOSCO (CLKO-RA6) CONFIG2L~1~8=0x7,0x0,INTOSC CONFIG2L~2~1=0x8,0x8,Enabled CONFIG2L~2~2=0x8,0x0,Disabled CONFIG2L~3~1=0x10,0x10,Disabled CONFIG2L~3~2=0x10,0x0,Enabled CONFIG2L~4~1=0x40,0x0,Disabled CONFIG2L~4~2=0x40,0x40,Enabled CONFIG2L~5~1=0x80,0x0,Disabled CONFIG2L~5~2=0x80,0x80,Enabled CONFIG2H_unused=0x0 CONFIG2H~1=WDTPS,0xf,Watchdog Postscaler CONFIG2H~2=RESERVED,0xf0,RESERVED CONFIG2H~1~1=0xf,0xf,1:32768 CONFIG2H~1~2=0xf,0xe,1:16384 CONFIG2H~1~3=0xf,0xd,1:8192 CONFIG2H~1~4=0xf,0xc,1:4096 CONFIG2H~1~5=0xf,0xb,1:2048 CONFIG2H~1~6=0xf,0xa,1:1024 CONFIG2H~1~7=0xf,0x9,1:512 CONFIG2H~1~8=0xf,0x8,1:256 CONFIG2H~1~9=0xf,0x7,1:128 CONFIG2H~1~10=0xf,0x6,1:64 CONFIG2H~1~11=0xf,0x5,1:32 CONFIG2H~1~12=0xf,0x4,1:16 CONFIG2H~1~13=0xf,0x3,1:8 CONFIG2H~1~14=0xf,0x2,1:4 CONFIG2H~1~15=0xf,0x1,1:2 CONFIG2H~1~16=0xf,0x0,1:1 CONFIG2H~2~1=0xf0,0xf0,RESERVED CONFIG3L_unused=0x0 CONFIG3L~1=DSWDTOSC,0x1,DSWDT Clock Select CONFIG3L~2=RTCOSC,0x2,RTCC Clock Select CONFIG3L~3=DSBOREN,0x4,Deep Sleep BOR CONFIG3L~4=DSWDTEN,0x8,Deep Sleep Watchdog Timer CONFIG3L~5=DSWDTPS,0xf0,Deep Sleep Watchdog Postscaler CONFIG3L~1~1=0x1,0x1,DSWDT uses INTRC CONFIG3L~1~2=0x1,0x0,DSWDT uses T1OSC/T1CKI CONFIG3L~2~1=0x2,0x2,RTCC uses T1OSC/T1CKI CONFIG3L~2~2=0x2,0x0,RTCC uses INTRC CONFIG3L~3~1=0x4,0x4,Enabled CONFIG3L~3~2=0x4,0x0,Disabled CONFIG3L~4~1=0x8,0x8,Enabled CONFIG3L~4~2=0x8,0x0,Disabled CONFIG3L~5~1=0xf0,0xf0,1:2,147,483,648 (25.7 days) CONFIG3L~5~2=0xf0,0xe0,1:536,870,912 (6.4 days) CONFIG3L~5~3=0xf0,0xd0,1:134,217,728 (38.5 hours) CONFIG3L~5~4=0xf0,0xc0,1:33,554,432 (9.6 hours) CONFIG3L~5~5=0xf0,0xb0,1:8,388,608 (2.4 hours) CONFIG3L~5~6=0xf0,0xa0,1:2,097,152 (36 minutes) CONFIG3L~5~7=0xf0,0x90,1:524,288 (9 minutes) CONFIG3L~5~8=0xf0,0x80,1:131,072 (135 seconds) CONFIG3L~5~9=0xf0,0x70,1:32,768 (34 seconds) CONFIG3L~5~10=0xf0,0x60,1:8,192 (8.5 seconds) CONFIG3L~5~11=0xf0,0x50,1:2,048 (2.1 seconds) CONFIG3L~5~12=0xf0,0x40,1:512 (528 ms) CONFIG3L~5~13=0xf0,0x30,1:128 (132 ms) CONFIG3L~5~14=0xf0,0x20,1:32 (33 ms) CONFIG3L~5~15=0xf0,0x10,1:8 (8.3 ms) CONFIG3L~5~16=0xf0,0x0,1:2 (2.1 ms) CONFIG3H_unused=0x0 CONFIG3H~1=IOL1WAY,0x1,IOLOCK One-Way Set Enable bit CONFIG3H~2=MSSP7B_EN,0x8,MSSP address masking CONFIG3H~3=RESERVED,0xf0,RESERVED CONFIG3H~1~1=0x1,0x1,Enabled CONFIG3H~1~2=0x1,0x0,Disabled CONFIG3H~2~1=0x8,0x8,7 Bit address masking mode CONFIG3H~2~2=0x8,0x0,5 Bit address masking mode CONFIG3H~3~1=0xf0,0xf0,RESERVED CONFIG4L_unused=0x0 CONFIG4L~1=WPFP,0x3f,Write/Erase Protect Page Start/End Location CONFIG4L~2=WPEND,0x40,Write/Erase Protect Region Select bit (valid when WPDIS = 0) CONFIG4L~3=WPCFG,0x80,Write/Erase Protect Configuration Region CONFIG4L~1~1=0x3f,0x0,Write Protect Program Flash Page 0 CONFIG4L~1~2=0x3f,0x1,Write Protect Program Flash Page 1 CONFIG4L~1~3=0x3f,0x2,Write Protect Program Flash Page 2 CONFIG4L~1~4=0x3f,0x3,Write Protect Program Flash Page 3 CONFIG4L~1~5=0x3f,0x4,Write Protect Program Flash Page 4 CONFIG4L~1~6=0x3f,0x5,Write Protect Program Flash Page 5 CONFIG4L~1~7=0x3f,0x6,Write Protect Program Flash Page 6 CONFIG4L~1~8=0x3f,0x7,Write Protect Program Flash Page 7 CONFIG4L~1~9=0x3f,0x8,Write Protect Program Flash Page 8 CONFIG4L~1~10=0x3f,0x9,Write Protect Program Flash Page 9 CONFIG4L~1~11=0x3f,0xa,Write Protect Program Flash Page 10 CONFIG4L~1~12=0x3f,0xb,Write Protect Program Flash Page 11 CONFIG4L~1~13=0x3f,0xc,Write Protect Program Flash Page 12 CONFIG4L~1~14=0x3f,0xd,Write Protect Program Flash Page 13 CONFIG4L~1~15=0x3f,0xe,Write Protect Program Flash Page 14 CONFIG4L~1~16=0x3f,0xf,Write Protect Program Flash Page 15 CONFIG4L~1~17=0x3f,0x10,Write Protect Program Flash Page 16 CONFIG4L~1~18=0x3f,0x11,Write Protect Program Flash Page 17 CONFIG4L~1~19=0x3f,0x12,Write Protect Program Flash Page 18 CONFIG4L~1~20=0x3f,0x13,Write Protect Program Flash Page 19 CONFIG4L~1~21=0x3f,0x14,Write Protect Program Flash Page 20 CONFIG4L~1~22=0x3f,0x15,Write Protect Program Flash Page 21 CONFIG4L~1~23=0x3f,0x16,Write Protect Program Flash Page 22 CONFIG4L~1~24=0x3f,0x17,Write Protect Program Flash Page 23 CONFIG4L~1~25=0x3f,0x18,Write Protect Program Flash Page 24 CONFIG4L~1~26=0x3f,0x19,Write Protect Program Flash Page 25 CONFIG4L~1~27=0x3f,0x1a,Write Protect Program Flash Page 26 CONFIG4L~1~28=0x3f,0x1b,Write Protect Program Flash Page 27 CONFIG4L~1~29=0x3f,0x1c,Write Protect Program Flash Page 28 CONFIG4L~1~30=0x3f,0x1d,Write Protect Program Flash Page 29 CONFIG4L~1~31=0x3f,0x1e,Write Protect Program Flash Page 30 CONFIG4L~1~32=0x3f,0x1f,Write Protect Program Flash Page 31 CONFIG4L~1~33=0x3f,0x20,Write Protect Program Flash Page 32 CONFIG4L~1~34=0x3f,0x21,Write Protect Program Flash Page 33 CONFIG4L~1~35=0x3f,0x22,Write Protect Program Flash Page 34 CONFIG4L~1~36=0x3f,0x23,Write Protect Program Flash Page 35 CONFIG4L~1~37=0x3f,0x24,Write Protect Program Flash Page 36 CONFIG4L~1~38=0x3f,0x25,Write Protect Program Flash Page 37 CONFIG4L~1~39=0x3f,0x26,Write Protect Program Flash Page 38 CONFIG4L~1~40=0x3f,0x27,Write Protect Program Flash Page 39 CONFIG4L~1~41=0x3f,0x28,Write Protect Program Flash Page 40 CONFIG4L~1~42=0x3f,0x29,Write Protect Program Flash Page 41 CONFIG4L~1~43=0x3f,0x2a,Write Protect Program Flash Page 42 CONFIG4L~1~44=0x3f,0x2b,Write Protect Program Flash Page 43 CONFIG4L~1~45=0x3f,0x2c,Write Protect Program Flash Page 44 CONFIG4L~1~46=0x3f,0x2d,Write Protect Program Flash Page 45 CONFIG4L~1~47=0x3f,0x2e,Write Protect Program Flash Page 46 CONFIG4L~1~48=0x3f,0x2f,Write Protect Program Flash Page 47 CONFIG4L~1~49=0x3f,0x30,Write Protect Program Flash Page 48 CONFIG4L~1~50=0x3f,0x31,Write Protect Program Flash Page 49 CONFIG4L~1~51=0x3f,0x32,Write Protect Program Flash Page 50 CONFIG4L~1~52=0x3f,0x33,Write Protect Program Flash Page 51 CONFIG4L~1~53=0x3f,0x34,Write Protect Program Flash Page 52 CONFIG4L~1~54=0x3f,0x35,Write Protect Program Flash Page 53 CONFIG4L~1~55=0x3f,0x36,Write Protect Program Flash Page 54 CONFIG4L~1~56=0x3f,0x37,Write Protect Program Flash Page 55 CONFIG4L~1~57=0x3f,0x38,Write Protect Program Flash Page 56 CONFIG4L~1~58=0x3f,0x39,Write Protect Program Flash Page 57 CONFIG4L~1~59=0x3f,0x3a,Write Protect Program Flash Page 58 CONFIG4L~1~60=0x3f,0x3b,Write Protect Program Flash Page 59 CONFIG4L~1~61=0x3f,0x3c,Write Protect Program Flash Page 60 CONFIG4L~1~62=0x3f,0x3d,Write Protect Program Flash Page 61 CONFIG4L~1~63=0x3f,0x3e,Write Protect Program Flash Page 62 CONFIG4L~1~64=0x3f,0x3f,Write Protect Program Flash Page 63 CONFIG4L~2~1=0x40,0x40,Pages WPFP<5:0> to (Configuration Words page) write/erase protected CONFIG4L~2~2=0x40,0x0,Page 0 to WPFP<5:0> erase/write-protected CONFIG4L~3~1=0x80,0x80,Disabled CONFIG4L~3~2=0x80,0x0,Enabled CONFIG4H_unused=0x0 CONFIG4H~1=WPDIS,0x1,Write Protect Disable bit CONFIG4H~2=RESERVED,0xf0,RESERVED CONFIG4H~1~1=0x1,0x1,Disabled CONFIG4H~1~2=0x1,0x0,Enabled CONFIG4H~2~1=0xf0,0xf0,RESERVED erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F26J53] pgmmem=0x0 ~pgmmem=0xfff7 cfgmem=0xfff8 ~cfgmem=0xffff userid= ~userid= eedata= ~eedata= devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0x5820 configslots=8 0xfff8=CONFIG1L 0xfff9=CONFIG1H 0xfffa=CONFIG2L 0xfffb=CONFIG2H 0xfffc=CONFIG3L 0xfffd=CONFIG3H 0xfffe=CONFIG4L 0xffff=CONFIG4H CONFIG1L_unused=0x0 CONFIG1L~1=WDTEN,0x1,Watchdog Timer CONFIG1L~2=PLLDIV,0xe,PLL Prescaler Selection bits (PLLSEL = 0) CONFIG1L~3=CFGPLLEN,0x10,PLL Configuration Enable Bit CONFIG1L~4=STVREN,0x20,Stack Overflow/Underflow Reset CONFIG1L~5=XINST,0x40,Extended Instruction Set CONFIG1L~6=DEBUG,0x80,Background Debug CONFIG1L~1~1=0x1,0x1,Enabled CONFIG1L~1~2=0x1,0x0,Disabled CONFIG1L~2~1=0xe,0xe,No prescale (4 MHz oscillator input drives PLL directly) CONFIG1L~2~2=0xe,0xc,Divide by 2 (8 MHz oscillator input) CONFIG1L~2~3=0xe,0xa,Divide by 3 (12 MHz oscillator input) CONFIG1L~2~4=0xe,0x8,Divide by 4 (16 MHz oscillator input) CONFIG1L~2~5=0xe,0x6,Divide by 5 (20 MHz oscillator input) CONFIG1L~2~6=0xe,0x4,Divide by 6 (24 MHz oscillator input) CONFIG1L~2~7=0xe,0x2,Divide by 10 (40 MHz oscillator input) CONFIG1L~2~8=0xe,0x0,Divide by 12 (48 MHz oscillator input) CONFIG1L~3~1=0x10,0x10,Enabled CONFIG1L~3~2=0x10,0x0,Disabled CONFIG1L~4~1=0x20,0x20,Enabled CONFIG1L~4~2=0x20,0x0,Disabled CONFIG1L~5~1=0x40,0x40,Enabled CONFIG1L~5~2=0x40,0x0,Disabled CONFIG1L~6~1=0x80,0x80,Disabled CONFIG1L~6~2=0x80,0x0,Enabled CONFIG1H_unused=0x0 CONFIG1H~1=CPUDIV,0x3,CPU System Clock Postscaler CONFIG1H~2=CP0,0x4,Code Protect CONFIG1H~3=SIGN,0x8,Config Word Signature Bit CONFIG1H~4=RESERVED,0xf0,RESERVED CONFIG1H~1~1=0x3,0x3,No CPU system clock divide CONFIG1H~1~2=0x3,0x2,CPU system clock divide by 2 CONFIG1H~1~3=0x3,0x1,CPU system clock divide by 3 CONFIG1H~1~4=0x3,0x0,CPU system clock divide by 6 CONFIG1H~2~1=0x4,0x4,Disabled CONFIG1H~2~2=0x4,0x0,Enabled CONFIG1H~3~1=0x8,0x8,Bulk erase of memory not conducated CONFIG1H~3~2=0x8,0x0,Bulk erase of memory area complete CONFIG1H~4~1=0xf0,0xf0,RESERVED CONFIG2L_unused=0x0 CONFIG2L~1=OSC,0x7,Oscillator CONFIG2L~2=SOSCSEL,0x18,T1OSC/SOSC Power Selection Bits CONFIG2L~3=CLKOEC,0x20,EC Clock Out Enable Bit CONFIG2L~4=FCMEN,0x40,Fail-Safe Clock Monitor CONFIG2L~5=IESO,0x80,Internal External Oscillator Switch Over Mode CONFIG2L~1~1=0x7,0x7,EC+PLL (CLKO-RA6), USB-EC+PLL CONFIG2L~1~2=0x7,0x6,EC (CLKO-RA6), USB-EC CONFIG2L~1~3=0x7,0x5,HS+PLL, USB-HS+PLL CONFIG2L~1~4=0x7,0x4,HS, USB-HS CONFIG2L~1~5=0x7,0x3,INTOSCPLLO (CLKO-RA6) CONFIG2L~1~6=0x7,0x2,INTOSCPLL CONFIG2L~1~7=0x7,0x1,INTOSCO (CLKO-RA6) CONFIG2L~1~8=0x7,0x0,INTOSC CONFIG2L~2~1=0x18,0x18,High Security Code Protection Enable CONFIG2L~2~2=0x18,0x10,Digital (SCLKI) mode selected CONFIG2L~2~3=0x18,0x8,Low Power T1OSC/SOSC circuit selected CONFIG2L~2~4=0x18,0x0,Reserved CONFIG2L~3~1=0x20,0x20,Enabled CONFIG2L~3~2=0x20,0x0,Disabled CONFIG2L~4~1=0x40,0x0,Disabled CONFIG2L~4~2=0x40,0x40,Enabled CONFIG2L~5~1=0x80,0x0,Disabled CONFIG2L~5~2=0x80,0x80,Enabled CONFIG2H_unused=0x0 CONFIG2H~1=WDTPS,0xf,Watchdog Postscaler CONFIG2H~2=RESERVED,0xf0,RESERVED CONFIG2H~1~1=0xf,0xf,1:32768 CONFIG2H~1~2=0xf,0xe,1:16384 CONFIG2H~1~3=0xf,0xd,1:8192 CONFIG2H~1~4=0xf,0xc,1:4096 CONFIG2H~1~5=0xf,0xb,1:2048 CONFIG2H~1~6=0xf,0xa,1:1024 CONFIG2H~1~7=0xf,0x9,1:512 CONFIG2H~1~8=0xf,0x8,1:256 CONFIG2H~1~9=0xf,0x7,1:128 CONFIG2H~1~10=0xf,0x6,1:64 CONFIG2H~1~11=0xf,0x5,1:32 CONFIG2H~1~12=0xf,0x4,1:16 CONFIG2H~1~13=0xf,0x3,1:8 CONFIG2H~1~14=0xf,0x2,1:4 CONFIG2H~1~15=0xf,0x1,1:2 CONFIG2H~1~16=0xf,0x0,1:1 CONFIG2H~2~1=0xf0,0xf0,RESERVED CONFIG3L_unused=0x0 CONFIG3L~1=DSWDTOSC,0x1,DSWDT Clock Select CONFIG3L~2=RTCOSC,0x2,RTCC Clock Select CONFIG3L~3=DSBOREN,0x4,Deep Sleep BOR CONFIG3L~4=DSWDTEN,0x8,Deep Sleep Watchdog Timer CONFIG3L~5=DSWDTPS,0xf0,Deep Sleep Watchdog Postscaler CONFIG3L~1~1=0x1,0x1,DSWDT uses INTRC CONFIG3L~1~2=0x1,0x0,DSWDT uses T1OSC/T1CKI CONFIG3L~2~1=0x2,0x2,RTCC uses T1OSC/T1CKI CONFIG3L~2~2=0x2,0x0,RTCC uses INTRC CONFIG3L~3~1=0x4,0x4,Enabled CONFIG3L~3~2=0x4,0x0,Disabled CONFIG3L~4~1=0x8,0x8,Enabled CONFIG3L~4~2=0x8,0x0,Disabled CONFIG3L~5~1=0xf0,0xf0,1:2,147,483,648 (25.7 days) CONFIG3L~5~2=0xf0,0xe0,1:536,870,912 (6.4 days) CONFIG3L~5~3=0xf0,0xd0,1:134,217,728 (38.5 hours) CONFIG3L~5~4=0xf0,0xc0,1:33,554,432 (9.6 hours) CONFIG3L~5~5=0xf0,0xb0,1:8,388,608 (2.4 hours) CONFIG3L~5~6=0xf0,0xa0,1:2,097,152 (36 minutes) CONFIG3L~5~7=0xf0,0x90,1:524,288 (9 minutes) CONFIG3L~5~8=0xf0,0x80,1:131,072 (135 seconds) CONFIG3L~5~9=0xf0,0x70,1:32,768 (34 seconds) CONFIG3L~5~10=0xf0,0x60,1:8,192 (8.5 seconds) CONFIG3L~5~11=0xf0,0x50,1:2,048 (2.1 seconds) CONFIG3L~5~12=0xf0,0x40,1:512 (528 ms) CONFIG3L~5~13=0xf0,0x30,1:128 (132 ms) CONFIG3L~5~14=0xf0,0x20,1:32 (33 ms) CONFIG3L~5~15=0xf0,0x10,1:8 (8.3 ms) CONFIG3L~5~16=0xf0,0x0,1:2 (2.1 ms) CONFIG3H_unused=0x0 CONFIG3H~1=IOL1WAY,0x1,IOLOCK One-Way Set Enable bit CONFIG3H~2=ADCSEL,0x2,ADC 10 or 12 Bit Select CONFIG3H~3=PLLSEL,0x4,PLL Selection Bit CONFIG3H~4=MSSP7B_EN,0x8,MSSP address masking CONFIG3H~5=RESERVED,0xf0,RESERVED CONFIG3H~1~1=0x1,0x1,Enabled CONFIG3H~1~2=0x1,0x0,Disabled CONFIG3H~2~1=0x2,0x2,10 - Bit ADC Enabled CONFIG3H~2~2=0x2,0x0,12 - Bit ADC Enabed CONFIG3H~3~1=0x4,0x0,Selects 96MHz PLL CONFIG3H~3~2=0x4,0x4,Selects 4x PLL CONFIG3H~4~1=0x8,0x8,7 Bit address masking mode CONFIG3H~4~2=0x8,0x0,5 Bit address masking mode CONFIG3H~5~1=0xf0,0xf0,RESERVED CONFIG4L_unused=0x0 CONFIG4L~1=WPFP,0x3f,Write/Erase Protect Page Start/End Location CONFIG4L~2=WPCFG,0x80,Write/Erase Protect Configuration Region CONFIG4L~1~1=0x3f,0x0,Write Protect Program Flash Page 0 CONFIG4L~1~2=0x3f,0x1,Write Protect Program Flash Page 1 CONFIG4L~1~3=0x3f,0x2,Write Protect Program Flash Page 2 CONFIG4L~1~4=0x3f,0x3,Write Protect Program Flash Page 3 CONFIG4L~1~5=0x3f,0x4,Write Protect Program Flash Page 4 CONFIG4L~1~6=0x3f,0x5,Write Protect Program Flash Page 5 CONFIG4L~1~7=0x3f,0x6,Write Protect Program Flash Page 6 CONFIG4L~1~8=0x3f,0x7,Write Protect Program Flash Page 7 CONFIG4L~1~9=0x3f,0x8,Write Protect Program Flash Page 8 CONFIG4L~1~10=0x3f,0x9,Write Protect Program Flash Page 9 CONFIG4L~1~11=0x3f,0xa,Write Protect Program Flash Page 10 CONFIG4L~1~12=0x3f,0xb,Write Protect Program Flash Page 11 CONFIG4L~1~13=0x3f,0xc,Write Protect Program Flash Page 12 CONFIG4L~1~14=0x3f,0xd,Write Protect Program Flash Page 13 CONFIG4L~1~15=0x3f,0xe,Write Protect Program Flash Page 14 CONFIG4L~1~16=0x3f,0xf,Write Protect Program Flash Page 15 CONFIG4L~1~17=0x3f,0x10,Write Protect Program Flash Page 16 CONFIG4L~1~18=0x3f,0x11,Write Protect Program Flash Page 17 CONFIG4L~1~19=0x3f,0x12,Write Protect Program Flash Page 18 CONFIG4L~1~20=0x3f,0x13,Write Protect Program Flash Page 19 CONFIG4L~1~21=0x3f,0x14,Write Protect Program Flash Page 20 CONFIG4L~1~22=0x3f,0x15,Write Protect Program Flash Page 21 CONFIG4L~1~23=0x3f,0x16,Write Protect Program Flash Page 22 CONFIG4L~1~24=0x3f,0x17,Write Protect Program Flash Page 23 CONFIG4L~1~25=0x3f,0x18,Write Protect Program Flash Page 24 CONFIG4L~1~26=0x3f,0x19,Write Protect Program Flash Page 25 CONFIG4L~1~27=0x3f,0x1a,Write Protect Program Flash Page 26 CONFIG4L~1~28=0x3f,0x1b,Write Protect Program Flash Page 27 CONFIG4L~1~29=0x3f,0x1c,Write Protect Program Flash Page 28 CONFIG4L~1~30=0x3f,0x1d,Write Protect Program Flash Page 29 CONFIG4L~1~31=0x3f,0x1e,Write Protect Program Flash Page 30 CONFIG4L~1~32=0x3f,0x1f,Write Protect Program Flash Page 31 CONFIG4L~1~33=0x3f,0x20,Write Protect Program Flash Page 32 CONFIG4L~1~34=0x3f,0x21,Write Protect Program Flash Page 33 CONFIG4L~1~35=0x3f,0x22,Write Protect Program Flash Page 34 CONFIG4L~1~36=0x3f,0x23,Write Protect Program Flash Page 35 CONFIG4L~1~37=0x3f,0x24,Write Protect Program Flash Page 36 CONFIG4L~1~38=0x3f,0x25,Write Protect Program Flash Page 37 CONFIG4L~1~39=0x3f,0x26,Write Protect Program Flash Page 38 CONFIG4L~1~40=0x3f,0x27,Write Protect Program Flash Page 39 CONFIG4L~1~41=0x3f,0x28,Write Protect Program Flash Page 40 CONFIG4L~1~42=0x3f,0x29,Write Protect Program Flash Page 41 CONFIG4L~1~43=0x3f,0x2a,Write Protect Program Flash Page 42 CONFIG4L~1~44=0x3f,0x2b,Write Protect Program Flash Page 43 CONFIG4L~1~45=0x3f,0x2c,Write Protect Program Flash Page 44 CONFIG4L~1~46=0x3f,0x2d,Write Protect Program Flash Page 45 CONFIG4L~1~47=0x3f,0x2e,Write Protect Program Flash Page 46 CONFIG4L~1~48=0x3f,0x2f,Write Protect Program Flash Page 47 CONFIG4L~1~49=0x3f,0x30,Write Protect Program Flash Page 48 CONFIG4L~1~50=0x3f,0x31,Write Protect Program Flash Page 49 CONFIG4L~1~51=0x3f,0x32,Write Protect Program Flash Page 50 CONFIG4L~1~52=0x3f,0x33,Write Protect Program Flash Page 51 CONFIG4L~1~53=0x3f,0x34,Write Protect Program Flash Page 52 CONFIG4L~1~54=0x3f,0x35,Write Protect Program Flash Page 53 CONFIG4L~1~55=0x3f,0x36,Write Protect Program Flash Page 54 CONFIG4L~1~56=0x3f,0x37,Write Protect Program Flash Page 55 CONFIG4L~1~57=0x3f,0x38,Write Protect Program Flash Page 56 CONFIG4L~1~58=0x3f,0x39,Write Protect Program Flash Page 57 CONFIG4L~1~59=0x3f,0x3a,Write Protect Program Flash Page 58 CONFIG4L~1~60=0x3f,0x3b,Write Protect Program Flash Page 59 CONFIG4L~1~61=0x3f,0x3c,Write Protect Program Flash Page 60 CONFIG4L~1~62=0x3f,0x3d,Write Protect Program Flash Page 61 CONFIG4L~1~63=0x3f,0x3e,Write Protect Program Flash Page 62 CONFIG4L~1~64=0x3f,0x3f,Write Protect Program Flash Page 63 CONFIG4L~2~1=0x80,0x80,Disabled CONFIG4L~2~2=0x80,0x0,Enabled CONFIG4H_unused=0x0 CONFIG4H~1=WPDIS,0x1,Write Protect Disable bit CONFIG4H~2=WPEND,0x2,Write/Erase Protect Region Select bit (valid when WPDIS = 0) CONFIG4H~3=LS48MHZ,0x8,Low Speed USB mode with 48 MHz system clock bit CONFIG4H~4=RESERVED,0xf0,RESERVED CONFIG4H~1~1=0x1,0x1,Disabled CONFIG4H~1~2=0x1,0x0,Enabled CONFIG4H~2~1=0x2,0x2,Pages WPFP<6:0> to (Configuration Words page) write/erase protected CONFIG4H~2~2=0x2,0x0,Page 0 to WPFP<6:0> erase/write-protected CONFIG4H~3~1=0x8,0x0,System clock at 24 MHz USB CLKEN divide-by is set to 4 CONFIG4H~3~2=0x8,0x8,System clock at 48 MHz USB CLKEN divide-by is set to 8 CONFIG4H~4~1=0xf0,0xf0,RESERVED erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F26K20] pgmmem=0x0 ~pgmmem=0xffff cfgmem=0x300000 ~cfgmem=0x30000d userid=0x200000 ~userid=0x200007 eedata=0x0 ~eedata=0x3ff devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0x2020 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000a=CONFIG6L 0x30000b=CONFIG6H 0x30000c=CONFIG7L 0x30000d=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=FOSC,0xf,Oscillator Selection bits CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable bit CONFIG1H~3=IESO,0x80,Internal/External Oscillator Switchover bit CONFIG1H~1~1=0xc,0xc,11XX External RC oscillator, CLKOUT function on RA6 CONFIG1H~1~2=0xe,0xa,101X External RC oscillator, CLKOUT function on RA6 CONFIG1H~1~3=0xf,0x9,Internal oscillator block, CLKOUT function on RA6, port function on RA7 CONFIG1H~1~4=0xf,0x8,Internal oscillator block, port function on RA6 and RA7 CONFIG1H~1~5=0xf,0x7,External RC oscillator, port function on RA6 CONFIG1H~1~6=0xf,0x6,HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) CONFIG1H~1~7=0xf,0x5,EC oscillator, port function on RA6 CONFIG1H~1~8=0xf,0x4,EC oscillator, CLKOUT function on RA6 CONFIG1H~1~9=0xf,0x3,External RC oscillator, CLKOUT function on RA6 CONFIG1H~1~10=0xf,0x2,HS oscillator CONFIG1H~1~11=0xf,0x1,XT oscillator CONFIG1H~1~12=0xf,0x0,LP oscillator CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PWRT,0x1,Power-up Timer Enable bit CONFIG2L~2=BOREN,0x6,Brown-out Reset Enable bits CONFIG2L~3=BORV,0x18,Brown Out Reset Voltage bits CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Brown-out Reset enabled in hardware only (SBOREN is disabled) CONFIG2L~2~2=0x6,0x4,Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) CONFIG2L~2~3=0x6,0x2,Enabled CONFIG2L~2~4=0x6,0x0,Disabled CONFIG2L~3~1=0x18,0x18,VBOR set to 1.8 V nominal CONFIG2L~3~2=0x18,0x10,VBOR set to 2.2 V nominal CONFIG2L~3~3=0x18,0x8,VBOR set to 2.7 V nominal CONFIG2L~3~4=0x18,0x0,VBOR set to 3.0 V nominal CONFIG2H_unused=0x0 CONFIG2H~1=WDTEN,0x1,Watchdog Timer Enable bit CONFIG2H~2=WDTPS,0x1e,Watchdog Timer Postscale Select bits CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled CONFIG2H~2~1=0x1e,0x1e,1:32768 CONFIG2H~2~2=0x1e,0x1c,1:16384 CONFIG2H~2~3=0x1e,0x1a,1:8192 CONFIG2H~2~4=0x1e,0x18,1:4096 CONFIG2H~2~5=0x1e,0x16,1:2048 CONFIG2H~2~6=0x1e,0x14,1:1024 CONFIG2H~2~7=0x1e,0x12,1:512 CONFIG2H~2~8=0x1e,0x10,1:256 CONFIG2H~2~9=0x1e,0xe,1:128 CONFIG2H~2~10=0x1e,0xc,1:64 CONFIG2H~2~11=0x1e,0xa,1:32 CONFIG2H~2~12=0x1e,0x8,1:16 CONFIG2H~2~13=0x1e,0x6,1:8 CONFIG2H~2~14=0x1e,0x4,1:4 CONFIG2H~2~15=0x1e,0x2,1:2 CONFIG2H~2~16=0x1e,0x0,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 MUX bit CONFIG3H~2=PBADEN,0x2,PORTB A/D Enable bit CONFIG3H~3=LPT1OSC,0x4,Low-Power Timer1 Oscillator Enable bit CONFIG3H~4=HFOFST,0x8,HFINTOSC Fast Start-up CONFIG3H~5=MCLRE,0x80,MCLR Pin Enable bit CONFIG3H~1~1=0x1,0x1,CCP2 input/output is multiplexed with RC1 CONFIG3H~1~2=0x1,0x0,CCP2 input/output is multiplexed with RB3 CONFIG3H~2~1=0x2,0x2,Enabled CONFIG3H~2~2=0x2,0x0,Disabled CONFIG3H~3~1=0x4,0x4,Enabled CONFIG3H~3~2=0x4,0x0,Disabled CONFIG3H~4~1=0x8,0x8,Enabled CONFIG3H~4~2=0x8,0x0,Disabled CONFIG3H~5~1=0x80,0x80,Enabled CONFIG3H~5~2=0x80,0x0,Disabled CONFIG4L_unused=0x0 CONFIG4L~1=STVREN,0x1,Stack Full/Underflow Reset Enable bit CONFIG4L~2=LVP,0x4,Single-Supply ICSP Enable bit CONFIG4L~3=XINST,0x40,Extended Instruction Set Enable bit CONFIG4L~4=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x40,0x40,Enabled CONFIG4L~3~2=0x40,0x0,Disabled CONFIG4L~4~1=0x80,0x80,Disabled CONFIG4L~4~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP0,0x1,Code Protection Block 0 CONFIG5L~2=CP1,0x2,Code Protection Block 1 CONFIG5L~3=CP2,0x4,Code Protection Block 2 CONFIG5L~4=CP3,0x8,Code Protection Block 3 CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x0,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x0,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x0,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x0,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPB,0x40,Boot Block Code Protection bit CONFIG5H~2=CPD,0x80,Data EEPROM Code Protection bit CONFIG5H~1~1=0x40,0x40,Disabled CONFIG5H~1~2=0x40,0x0,Enabled CONFIG5H~2~1=0x80,0x80,Disabled CONFIG5H~2~2=0x80,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT0,0x1,Write Protection Block 0 CONFIG6L~2=WRT1,0x2,Write Protection Block 1 CONFIG6L~3=WRT2,0x4,Write Protection Block 2 CONFIG6L~4=WRT3,0x8,Write Protection Block 3 CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x0,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x0,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x0,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x0,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTC,0x20,Configuration Register Write Protection bit CONFIG6H~2=WRTB,0x40,Boot Block Write Protection bit CONFIG6H~3=WRTD,0x80,Data EEPROM Write Protection bit CONFIG6H~1~1=0x20,0x20,Disabled CONFIG6H~1~2=0x20,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x80,0x80,Disabled CONFIG6H~3~2=0x80,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR0,0x1,Table Read Protection Block 0 CONFIG7L~2=EBTR1,0x2,Table Read Protection Block 1 CONFIG7L~3=EBTR2,0x4,Table Read Protection Block 2 CONFIG7L~4=EBTR3,0x8,Table Read Protection Block 3 CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x0,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x0,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x0,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x0,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Boot Block Table Read Protection bit CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F27J13] pgmmem=0x0 ~pgmmem=0x1fff7 cfgmem=0x1fff8 ~cfgmem=0x1ffff userid= ~userid= eedata= ~eedata= devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0x5960 configslots=8 0x1fff8=CONFIG1L 0x1fff9=CONFIG1H 0x1fffa=CONFIG2L 0x1fffb=CONFIG2H 0x1fffc=CONFIG3L 0x1fffd=CONFIG3H 0x1fffe=CONFIG4L 0x1ffff=CONFIG4H CONFIG1L_unused=0x0 CONFIG1L~1=WDTEN,0x1,Watchdog Timer CONFIG1L~2=PLLDIV,0xe,PLL Prescaler Selection bits (PLLSEL = 0) CONFIG1L~3=CFGPLLEN,0x10,PLL Configuration Enable Bit CONFIG1L~4=STVREN,0x20,Stack Overflow/Underflow Reset CONFIG1L~5=XINST,0x40,Extended Instruction Set CONFIG1L~6=DEBUG,0x80,Background Debug CONFIG1L~1~1=0x1,0x1,Enabled CONFIG1L~1~2=0x1,0x0,Disabled CONFIG1L~2~1=0xe,0xe,No prescale (4 MHz oscillator input drives PLL directly) CONFIG1L~2~2=0xe,0xc,Divide by 2 (8 MHz oscillator input) CONFIG1L~2~3=0xe,0xa,Divide by 3 (12 MHz oscillator input) CONFIG1L~2~4=0xe,0x8,Divide by 4 (16 MHz oscillator input) CONFIG1L~2~5=0xe,0x6,Divide by 5 (20 MHz oscillator input) CONFIG1L~2~6=0xe,0x4,Divide by 6 (24 MHz oscillator input) CONFIG1L~2~7=0xe,0x2,Divide by 10 (40 MHz oscillator input) CONFIG1L~2~8=0xe,0x0,Divide by 12 (48 MHz oscillator input) CONFIG1L~3~1=0x10,0x10,Enabled CONFIG1L~3~2=0x10,0x0,Disabled CONFIG1L~4~1=0x20,0x20,Enabled CONFIG1L~4~2=0x20,0x0,Disabled CONFIG1L~5~1=0x40,0x40,Enabled CONFIG1L~5~2=0x40,0x0,Disabled CONFIG1L~6~1=0x80,0x80,Disabled CONFIG1L~6~2=0x80,0x0,Enabled CONFIG1H_unused=0x0 CONFIG1H~1=CP0,0x4,Code Protect CONFIG1H~2=SIGN,0x8,Config Word Signature Bit CONFIG1H~3=RESERVED,0xf0,RESERVED CONFIG1H~1~1=0x4,0x4,Disabled CONFIG1H~1~2=0x4,0x0,Enabled CONFIG1H~2~1=0x8,0x8,Bulk erase of memory not conducated CONFIG1H~2~2=0x8,0x0,Bulk erase of memory area complete CONFIG1H~3~1=0xf0,0xf0,RESERVED CONFIG2L_unused=0x0 CONFIG2L~1=OSC,0x7,Oscillator CONFIG2L~2=SOSCSEL,0x18,T1OSC/SOSC Power Selection Bits CONFIG2L~3=CLKOEC,0x20,EC Clock Out Enable Bit CONFIG2L~4=FCMEN,0x40,Fail-Safe Clock Monitor CONFIG2L~5=IESO,0x80,Internal External Oscillator Switch Over Mode CONFIG2L~1~1=0x7,0x7,EC+PLL (CLKO-RA6), USB-EC+PLL CONFIG2L~1~2=0x7,0x6,EC (CLKO-RA6), USB-EC CONFIG2L~1~3=0x7,0x5,HS+PLL, USB-HS+PLL CONFIG2L~1~4=0x7,0x4,HS, USB-HS CONFIG2L~1~5=0x7,0x3,INTOSCPLLO (CLKO-RA6) CONFIG2L~1~6=0x7,0x2,INTOSCPLL CONFIG2L~1~7=0x7,0x1,INTOSCO (CLKO-RA6) CONFIG2L~1~8=0x7,0x0,INTOSC CONFIG2L~2~1=0x18,0x18,High Security Code Protection Enable CONFIG2L~2~2=0x18,0x10,Digital (SCLKI) mode selected CONFIG2L~2~3=0x18,0x8,Low Power T1OSC/SOSC circuit selected CONFIG2L~2~4=0x18,0x0,Reserved CONFIG2L~3~1=0x20,0x20,Enabled CONFIG2L~3~2=0x20,0x0,Disabled CONFIG2L~4~1=0x40,0x0,Disabled CONFIG2L~4~2=0x40,0x40,Enabled CONFIG2L~5~1=0x80,0x0,Disabled CONFIG2L~5~2=0x80,0x80,Enabled CONFIG2H_unused=0x0 CONFIG2H~1=WDTPS,0xf,Watchdog Postscaler CONFIG2H~2=RESERVED,0xf0,RESERVED CONFIG2H~1~1=0xf,0xf,1:32768 CONFIG2H~1~2=0xf,0xe,1:16384 CONFIG2H~1~3=0xf,0xd,1:8192 CONFIG2H~1~4=0xf,0xc,1:4096 CONFIG2H~1~5=0xf,0xb,1:2048 CONFIG2H~1~6=0xf,0xa,1:1024 CONFIG2H~1~7=0xf,0x9,1:512 CONFIG2H~1~8=0xf,0x8,1:256 CONFIG2H~1~9=0xf,0x7,1:128 CONFIG2H~1~10=0xf,0x6,1:64 CONFIG2H~1~11=0xf,0x5,1:32 CONFIG2H~1~12=0xf,0x4,1:16 CONFIG2H~1~13=0xf,0x3,1:8 CONFIG2H~1~14=0xf,0x2,1:4 CONFIG2H~1~15=0xf,0x1,1:2 CONFIG2H~1~16=0xf,0x0,1:1 CONFIG2H~2~1=0xf0,0xf0,RESERVED CONFIG3L_unused=0x0 CONFIG3L~1=DSWDTOSC,0x1,DSWDT Clock Select CONFIG3L~2=RTCOSC,0x2,RTCC Clock Select CONFIG3L~3=DSBOREN,0x4,Deep Sleep BOR CONFIG3L~4=DSWDTEN,0x8,Deep Sleep Watchdog Timer CONFIG3L~5=DSWDTPS,0xf0,Deep Sleep Watchdog Postscaler CONFIG3L~1~1=0x1,0x1,DSWDT uses INTRC CONFIG3L~1~2=0x1,0x0,DSWDT uses T1OSC/T1CKI CONFIG3L~2~1=0x2,0x2,RTCC uses T1OSC/T1CKI CONFIG3L~2~2=0x2,0x0,RTCC uses INTRC CONFIG3L~3~1=0x4,0x4,Enabled CONFIG3L~3~2=0x4,0x0,Disabled CONFIG3L~4~1=0x8,0x8,Enabled CONFIG3L~4~2=0x8,0x0,Disabled CONFIG3L~5~1=0xf0,0xf0,1:2,147,483,648 (25.7 days) CONFIG3L~5~2=0xf0,0xe0,1:536,870,912 (6.4 days) CONFIG3L~5~3=0xf0,0xd0,1:134,217,728 (38.5 hours) CONFIG3L~5~4=0xf0,0xc0,1:33,554,432 (9.6 hours) CONFIG3L~5~5=0xf0,0xb0,1:8,388,608 (2.4 hours) CONFIG3L~5~6=0xf0,0xa0,1:2,097,152 (36 minutes) CONFIG3L~5~7=0xf0,0x90,1:524,288 (9 minutes) CONFIG3L~5~8=0xf0,0x80,1:131,072 (135 seconds) CONFIG3L~5~9=0xf0,0x70,1:32,768 (34 seconds) CONFIG3L~5~10=0xf0,0x60,1:8,192 (8.5 seconds) CONFIG3L~5~11=0xf0,0x50,1:2,048 (2.1 seconds) CONFIG3L~5~12=0xf0,0x40,1:512 (528 ms) CONFIG3L~5~13=0xf0,0x30,1:128 (132 ms) CONFIG3L~5~14=0xf0,0x20,1:32 (33 ms) CONFIG3L~5~15=0xf0,0x10,1:8 (8.3 ms) CONFIG3L~5~16=0xf0,0x0,1:2 (2.1 ms) CONFIG3H_unused=0x0 CONFIG3H~1=IOL1WAY,0x1,IOLOCK One-Way Set Enable bit CONFIG3H~2=ADCSEL,0x2,ADC 10 or 12 Bit Select CONFIG3H~3=PLLSEL,0x4,PLL Selection Bit CONFIG3H~4=MSSP7B_EN,0x8,MSSP address masking CONFIG3H~5=RESERVED,0xf0,RESERVED CONFIG3H~1~1=0x1,0x1,Enabled CONFIG3H~1~2=0x1,0x0,Disabled CONFIG3H~2~1=0x2,0x2,10 - Bit ADC Enabled CONFIG3H~2~2=0x2,0x0,12 - Bit ADC Enabed CONFIG3H~3~1=0x4,0x0,Selects 96MHz PLL CONFIG3H~3~2=0x4,0x4,Selects 4x PLL CONFIG3H~4~1=0x8,0x8,7 Bit address masking mode CONFIG3H~4~2=0x8,0x0,5 Bit address masking mode CONFIG3H~5~1=0xf0,0xf0,RESERVED CONFIG4L_unused=0x0 CONFIG4L~1=WPFP,0x7f,Write/Erase Protect Page Start/End Location CONFIG4L~2=WPCFG,0x80,Write/Erase Protect Configuration Region CONFIG4L~1~1=0x7f,0x0,Write Protect Program Flash Page 0 CONFIG4L~1~2=0x7f,0x1,Write Protect Program Flash Page 1 CONFIG4L~1~3=0x7f,0x2,Write Protect Program Flash Page 2 CONFIG4L~1~4=0x7f,0x3,Write Protect Program Flash Page 3 CONFIG4L~1~5=0x7f,0x4,Write Protect Program Flash Page 4 CONFIG4L~1~6=0x7f,0x5,Write Protect Program Flash Page 5 CONFIG4L~1~7=0x7f,0x6,Write Protect Program Flash Page 6 CONFIG4L~1~8=0x7f,0x7,Write Protect Program Flash Page 7 CONFIG4L~1~9=0x7f,0x8,Write Protect Program Flash Page 8 CONFIG4L~1~10=0x7f,0x9,Write Protect Program Flash Page 9 CONFIG4L~1~11=0x7f,0xa,Write Protect Program Flash Page 10 CONFIG4L~1~12=0x7f,0xb,Write Protect Program Flash Page 11 CONFIG4L~1~13=0x7f,0xc,Write Protect Program Flash Page 12 CONFIG4L~1~14=0x7f,0xd,Write Protect Program Flash Page 13 CONFIG4L~1~15=0x7f,0xe,Write Protect Program Flash Page 14 CONFIG4L~1~16=0x7f,0xf,Write Protect Program Flash Page 15 CONFIG4L~1~17=0x7f,0x10,Write Protect Program Flash Page 16 CONFIG4L~1~18=0x7f,0x11,Write Protect Program Flash Page 17 CONFIG4L~1~19=0x7f,0x12,Write Protect Program Flash Page 18 CONFIG4L~1~20=0x7f,0x13,Write Protect Program Flash Page 19 CONFIG4L~1~21=0x7f,0x14,Write Protect Program Flash Page 20 CONFIG4L~1~22=0x7f,0x15,Write Protect Program Flash Page 21 CONFIG4L~1~23=0x7f,0x16,Write Protect Program Flash Page 22 CONFIG4L~1~24=0x7f,0x17,Write Protect Program Flash Page 23 CONFIG4L~1~25=0x7f,0x18,Write Protect Program Flash Page 24 CONFIG4L~1~26=0x7f,0x19,Write Protect Program Flash Page 25 CONFIG4L~1~27=0x7f,0x1a,Write Protect Program Flash Page 26 CONFIG4L~1~28=0x7f,0x1b,Write Protect Program Flash Page 27 CONFIG4L~1~29=0x7f,0x1c,Write Protect Program Flash Page 28 CONFIG4L~1~30=0x7f,0x1d,Write Protect Program Flash Page 29 CONFIG4L~1~31=0x7f,0x1e,Write Protect Program Flash Page 30 CONFIG4L~1~32=0x7f,0x1f,Write Protect Program Flash Page 31 CONFIG4L~1~33=0x7f,0x20,Write Protect Program Flash Page 32 CONFIG4L~1~34=0x7f,0x21,Write Protect Program Flash Page 33 CONFIG4L~1~35=0x7f,0x22,Write Protect Program Flash Page 34 CONFIG4L~1~36=0x7f,0x23,Write Protect Program Flash Page 35 CONFIG4L~1~37=0x7f,0x24,Write Protect Program Flash Page 36 CONFIG4L~1~38=0x7f,0x25,Write Protect Program Flash Page 37 CONFIG4L~1~39=0x7f,0x26,Write Protect Program Flash Page 38 CONFIG4L~1~40=0x7f,0x27,Write Protect Program Flash Page 39 CONFIG4L~1~41=0x7f,0x28,Write Protect Program Flash Page 40 CONFIG4L~1~42=0x7f,0x29,Write Protect Program Flash Page 41 CONFIG4L~1~43=0x7f,0x2a,Write Protect Program Flash Page 42 CONFIG4L~1~44=0x7f,0x2b,Write Protect Program Flash Page 43 CONFIG4L~1~45=0x7f,0x2c,Write Protect Program Flash Page 44 CONFIG4L~1~46=0x7f,0x2d,Write Protect Program Flash Page 45 CONFIG4L~1~47=0x7f,0x2e,Write Protect Program Flash Page 46 CONFIG4L~1~48=0x7f,0x2f,Write Protect Program Flash Page 47 CONFIG4L~1~49=0x7f,0x30,Write Protect Program Flash Page 48 CONFIG4L~1~50=0x7f,0x31,Write Protect Program Flash Page 49 CONFIG4L~1~51=0x7f,0x32,Write Protect Program Flash Page 50 CONFIG4L~1~52=0x7f,0x33,Write Protect Program Flash Page 51 CONFIG4L~1~53=0x7f,0x34,Write Protect Program Flash Page 52 CONFIG4L~1~54=0x7f,0x35,Write Protect Program Flash Page 53 CONFIG4L~1~55=0x7f,0x36,Write Protect Program Flash Page 54 CONFIG4L~1~56=0x7f,0x37,Write Protect Program Flash Page 55 CONFIG4L~1~57=0x7f,0x38,Write Protect Program Flash Page 56 CONFIG4L~1~58=0x7f,0x39,Write Protect Program Flash Page 57 CONFIG4L~1~59=0x7f,0x3a,Write Protect Program Flash Page 58 CONFIG4L~1~60=0x7f,0x3b,Write Protect Program Flash Page 59 CONFIG4L~1~61=0x7f,0x3c,Write Protect Program Flash Page 60 CONFIG4L~1~62=0x7f,0x3d,Write Protect Program Flash Page 61 CONFIG4L~1~63=0x7f,0x3e,Write Protect Program Flash Page 62 CONFIG4L~1~64=0x7f,0x3f,Write Protect Program Flash Page 63 CONFIG4L~1~65=0x7f,0x40,Write Protect Program Flash Page 64 CONFIG4L~1~66=0x7f,0x41,Write Protect Program Flash Page 65 CONFIG4L~1~67=0x7f,0x42,Write Protect Program Flash Page 66 CONFIG4L~1~68=0x7f,0x43,Write Protect Program Flash Page 67 CONFIG4L~1~69=0x7f,0x44,Write Protect Program Flash Page 68 CONFIG4L~1~70=0x7f,0x45,Write Protect Program Flash Page 69 CONFIG4L~1~71=0x7f,0x46,Write Protect Program Flash Page 70 CONFIG4L~1~72=0x7f,0x47,Write Protect Program Flash Page 71 CONFIG4L~1~73=0x7f,0x48,Write Protect Program Flash Page 72 CONFIG4L~1~74=0x7f,0x49,Write Protect Program Flash Page 73 CONFIG4L~1~75=0x7f,0x4a,Write Protect Program Flash Page 74 CONFIG4L~1~76=0x7f,0x4b,Write Protect Program Flash Page 75 CONFIG4L~1~77=0x7f,0x4c,Write Protect Program Flash Page 76 CONFIG4L~1~78=0x7f,0x4d,Write Protect Program Flash Page 77 CONFIG4L~1~79=0x7f,0x4e,Write Protect Program Flash Page 78 CONFIG4L~1~80=0x7f,0x4f,Write Protect Program Flash Page 79 CONFIG4L~1~81=0x7f,0x50,Write Protect Program Flash Page 80 CONFIG4L~1~82=0x7f,0x51,Write Protect Program Flash Page 81 CONFIG4L~1~83=0x7f,0x52,Write Protect Program Flash Page 82 CONFIG4L~1~84=0x7f,0x53,Write Protect Program Flash Page 83 CONFIG4L~1~85=0x7f,0x54,Write Protect Program Flash Page 84 CONFIG4L~1~86=0x7f,0x55,Write Protect Program Flash Page 85 CONFIG4L~1~87=0x7f,0x56,Write Protect Program Flash Page 86 CONFIG4L~1~88=0x7f,0x57,Write Protect Program Flash Page 87 CONFIG4L~1~89=0x7f,0x58,Write Protect Program Flash Page 88 CONFIG4L~1~90=0x7f,0x59,Write Protect Program Flash Page 89 CONFIG4L~1~91=0x7f,0x5a,Write Protect Program Flash Page 90 CONFIG4L~1~92=0x7f,0x5b,Write Protect Program Flash Page 91 CONFIG4L~1~93=0x7f,0x5c,Write Protect Program Flash Page 92 CONFIG4L~1~94=0x7f,0x5d,Write Protect Program Flash Page 93 CONFIG4L~1~95=0x7f,0x5e,Write Protect Program Flash Page 94 CONFIG4L~1~96=0x7f,0x5f,Write Protect Program Flash Page 95 CONFIG4L~1~97=0x7f,0x60,Write Protect Program Flash Page 96 CONFIG4L~1~98=0x7f,0x61,Write Protect Program Flash Page 97 CONFIG4L~1~99=0x7f,0x62,Write Protect Program Flash Page 98 CONFIG4L~1~100=0x7f,0x63,Write Protect Program Flash Page 99 CONFIG4L~1~101=0x7f,0x64,Write Protect Program Flash Page 100 CONFIG4L~1~102=0x7f,0x65,Write Protect Program Flash Page 101 CONFIG4L~1~103=0x7f,0x66,Write Protect Program Flash Page 102 CONFIG4L~1~104=0x7f,0x67,Write Protect Program Flash Page 103 CONFIG4L~1~105=0x7f,0x68,Write Protect Program Flash Page 104 CONFIG4L~1~106=0x7f,0x69,Write Protect Program Flash Page 105 CONFIG4L~1~107=0x7f,0x6a,Write Protect Program Flash Page 106 CONFIG4L~1~108=0x7f,0x6b,Write Protect Program Flash Page 107 CONFIG4L~1~109=0x7f,0x6c,Write Protect Program Flash Page 108 CONFIG4L~1~110=0x7f,0x6d,Write Protect Program Flash Page 109 CONFIG4L~1~111=0x7f,0x6e,Write Protect Program Flash Page 110 CONFIG4L~1~112=0x7f,0x6f,Write Protect Program Flash Page 111 CONFIG4L~1~113=0x7f,0x70,Write Protect Program Flash Page 112 CONFIG4L~1~114=0x7f,0x71,Write Protect Program Flash Page 113 CONFIG4L~1~115=0x7f,0x72,Write Protect Program Flash Page 114 CONFIG4L~1~116=0x7f,0x73,Write Protect Program Flash Page 115 CONFIG4L~1~117=0x7f,0x74,Write Protect Program Flash Page 116 CONFIG4L~1~118=0x7f,0x75,Write Protect Program Flash Page 117 CONFIG4L~1~119=0x7f,0x76,Write Protect Program Flash Page 118 CONFIG4L~1~120=0x7f,0x77,Write Protect Program Flash Page 119 CONFIG4L~1~121=0x7f,0x78,Write Protect Program Flash Page 120 CONFIG4L~1~122=0x7f,0x79,Write Protect Program Flash Page 121 CONFIG4L~1~123=0x7f,0x7a,Write Protect Program Flash Page 122 CONFIG4L~1~124=0x7f,0x7b,Write Protect Program Flash Page 123 CONFIG4L~1~125=0x7f,0x7c,Write Protect Program Flash Page 124 CONFIG4L~1~126=0x7f,0x7d,Write Protect Program Flash Page 125 CONFIG4L~1~127=0x7f,0x7e,Write Protect Program Flash Page 126 CONFIG4L~1~128=0x7f,0x7f,Write Protect Program Flash Page 127 CONFIG4L~2~1=0x80,0x80,Disabled CONFIG4L~2~2=0x80,0x0,Enabled CONFIG4H_unused=0x0 CONFIG4H~1=WPDIS,0x1,Write Protect Disable bit CONFIG4H~2=WPEND,0x2,Write/Erase Protect Region Select bit (valid when WPDIS = 0) CONFIG4H~3=RESERVED,0xf0,RESERVED CONFIG4H~1~1=0x1,0x1,Disabled CONFIG4H~1~2=0x1,0x0,Enabled CONFIG4H~2~1=0x2,0x2,Pages WPFP<6:0> to (Configuration Words page) write/erase protected CONFIG4H~2~2=0x2,0x0,Page 0 to WPFP<6:0> erase/write-protected CONFIG4H~3~1=0xf0,0xf0,RESERVED erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F27J53] pgmmem=0x0 ~pgmmem=0x1fff7 cfgmem=0x1fff8 ~cfgmem=0x1ffff userid= ~userid= eedata= ~eedata= devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0x5860 configslots=8 0x1fff8=CONFIG1L 0x1fff9=CONFIG1H 0x1fffa=CONFIG2L 0x1fffb=CONFIG2H 0x1fffc=CONFIG3L 0x1fffd=CONFIG3H 0x1fffe=CONFIG4L 0x1ffff=CONFIG4H CONFIG1L_unused=0x0 CONFIG1L~1=WDTEN,0x1,Watchdog Timer CONFIG1L~2=PLLDIV,0xe,PLL Prescaler Selection bits (PLLSEL = 0) CONFIG1L~3=CFGPLLEN,0x10,PLL Configuration Enable Bit CONFIG1L~4=STVREN,0x20,Stack Overflow/Underflow Reset CONFIG1L~5=XINST,0x40,Extended Instruction Set CONFIG1L~6=DEBUG,0x80,Background Debug CONFIG1L~1~1=0x1,0x1,Enabled CONFIG1L~1~2=0x1,0x0,Disabled CONFIG1L~2~1=0xe,0xe,No prescale (4 MHz oscillator input drives PLL directly) CONFIG1L~2~2=0xe,0xc,Divide by 2 (8 MHz oscillator input) CONFIG1L~2~3=0xe,0xa,Divide by 3 (12 MHz oscillator input) CONFIG1L~2~4=0xe,0x8,Divide by 4 (16 MHz oscillator input) CONFIG1L~2~5=0xe,0x6,Divide by 5 (20 MHz oscillator input) CONFIG1L~2~6=0xe,0x4,Divide by 6 (24 MHz oscillator input) CONFIG1L~2~7=0xe,0x2,Divide by 10 (40 MHz oscillator input) CONFIG1L~2~8=0xe,0x0,Divide by 12 (48 MHz oscillator input) CONFIG1L~3~1=0x10,0x10,Enabled CONFIG1L~3~2=0x10,0x0,Disabled CONFIG1L~4~1=0x20,0x20,Enabled CONFIG1L~4~2=0x20,0x0,Disabled CONFIG1L~5~1=0x40,0x40,Enabled CONFIG1L~5~2=0x40,0x0,Disabled CONFIG1L~6~1=0x80,0x80,Disabled CONFIG1L~6~2=0x80,0x0,Enabled CONFIG1H_unused=0x0 CONFIG1H~1=CPUDIV,0x3,CPU System Clock Postscaler CONFIG1H~2=CP0,0x4,Code Protect CONFIG1H~3=SIGN,0x8,Config Word Signature Bit CONFIG1H~4=RESERVED,0xf0,RESERVED CONFIG1H~1~1=0x3,0x3,No CPU system clock divide CONFIG1H~1~2=0x3,0x2,CPU system clock divide by 2 CONFIG1H~1~3=0x3,0x1,CPU system clock divide by 3 CONFIG1H~1~4=0x3,0x0,CPU system clock divide by 6 CONFIG1H~2~1=0x4,0x4,Disabled CONFIG1H~2~2=0x4,0x0,Enabled CONFIG1H~3~1=0x8,0x8,Bulk erase of memory not conducated CONFIG1H~3~2=0x8,0x0,Bulk erase of memory area complete CONFIG1H~4~1=0xf0,0xf0,RESERVED CONFIG2L_unused=0x0 CONFIG2L~1=OSC,0x7,Oscillator CONFIG2L~2=SOSCSEL,0x18,T1OSC/SOSC Power Selection Bits CONFIG2L~3=CLKOEC,0x20,EC Clock Out Enable Bit CONFIG2L~4=FCMEN,0x40,Fail-Safe Clock Monitor CONFIG2L~5=IESO,0x80,Internal External Oscillator Switch Over Mode CONFIG2L~1~1=0x7,0x7,EC+PLL (CLKO-RA6), USB-EC+PLL CONFIG2L~1~2=0x7,0x6,EC (CLKO-RA6), USB-EC CONFIG2L~1~3=0x7,0x5,HS+PLL, USB-HS+PLL CONFIG2L~1~4=0x7,0x4,HS, USB-HS CONFIG2L~1~5=0x7,0x3,INTOSCPLLO (CLKO-RA6) CONFIG2L~1~6=0x7,0x2,INTOSCPLL CONFIG2L~1~7=0x7,0x1,INTOSCO (CLKO-RA6) CONFIG2L~1~8=0x7,0x0,INTOSC CONFIG2L~2~1=0x18,0x18,High Security Code Protection Enable CONFIG2L~2~2=0x18,0x10,Digital (SCLKI) mode selected CONFIG2L~2~3=0x18,0x8,Low Power T1OSC/SOSC circuit selected CONFIG2L~2~4=0x18,0x0,Reserved CONFIG2L~3~1=0x20,0x20,Enabled CONFIG2L~3~2=0x20,0x0,Disabled CONFIG2L~4~1=0x40,0x0,Disabled CONFIG2L~4~2=0x40,0x40,Enabled CONFIG2L~5~1=0x80,0x0,Disabled CONFIG2L~5~2=0x80,0x80,Enabled CONFIG2H_unused=0x0 CONFIG2H~1=WDTPS,0xf,Watchdog Postscaler CONFIG2H~2=RESERVED,0xf0,RESERVED CONFIG2H~1~1=0xf,0xf,1:32768 CONFIG2H~1~2=0xf,0xe,1:16384 CONFIG2H~1~3=0xf,0xd,1:8192 CONFIG2H~1~4=0xf,0xc,1:4096 CONFIG2H~1~5=0xf,0xb,1:2048 CONFIG2H~1~6=0xf,0xa,1:1024 CONFIG2H~1~7=0xf,0x9,1:512 CONFIG2H~1~8=0xf,0x8,1:256 CONFIG2H~1~9=0xf,0x7,1:128 CONFIG2H~1~10=0xf,0x6,1:64 CONFIG2H~1~11=0xf,0x5,1:32 CONFIG2H~1~12=0xf,0x4,1:16 CONFIG2H~1~13=0xf,0x3,1:8 CONFIG2H~1~14=0xf,0x2,1:4 CONFIG2H~1~15=0xf,0x1,1:2 CONFIG2H~1~16=0xf,0x0,1:1 CONFIG2H~2~1=0xf0,0xf0,RESERVED CONFIG3L_unused=0x0 CONFIG3L~1=DSWDTOSC,0x1,DSWDT Clock Select CONFIG3L~2=RTCOSC,0x2,RTCC Clock Select CONFIG3L~3=DSBOREN,0x4,Deep Sleep BOR CONFIG3L~4=DSWDTEN,0x8,Deep Sleep Watchdog Timer CONFIG3L~5=DSWDTPS,0xf0,Deep Sleep Watchdog Postscaler CONFIG3L~1~1=0x1,0x1,DSWDT uses INTRC CONFIG3L~1~2=0x1,0x0,DSWDT uses T1OSC/T1CKI CONFIG3L~2~1=0x2,0x2,RTCC uses T1OSC/T1CKI CONFIG3L~2~2=0x2,0x0,RTCC uses INTRC CONFIG3L~3~1=0x4,0x4,Enabled CONFIG3L~3~2=0x4,0x0,Disabled CONFIG3L~4~1=0x8,0x8,Enabled CONFIG3L~4~2=0x8,0x0,Disabled CONFIG3L~5~1=0xf0,0xf0,1:2,147,483,648 (25.7 days) CONFIG3L~5~2=0xf0,0xe0,1:536,870,912 (6.4 days) CONFIG3L~5~3=0xf0,0xd0,1:134,217,728 (38.5 hours) CONFIG3L~5~4=0xf0,0xc0,1:33,554,432 (9.6 hours) CONFIG3L~5~5=0xf0,0xb0,1:8,388,608 (2.4 hours) CONFIG3L~5~6=0xf0,0xa0,1:2,097,152 (36 minutes) CONFIG3L~5~7=0xf0,0x90,1:524,288 (9 minutes) CONFIG3L~5~8=0xf0,0x80,1:131,072 (135 seconds) CONFIG3L~5~9=0xf0,0x70,1:32,768 (34 seconds) CONFIG3L~5~10=0xf0,0x60,1:8,192 (8.5 seconds) CONFIG3L~5~11=0xf0,0x50,1:2,048 (2.1 seconds) CONFIG3L~5~12=0xf0,0x40,1:512 (528 ms) CONFIG3L~5~13=0xf0,0x30,1:128 (132 ms) CONFIG3L~5~14=0xf0,0x20,1:32 (33 ms) CONFIG3L~5~15=0xf0,0x10,1:8 (8.3 ms) CONFIG3L~5~16=0xf0,0x0,1:2 (2.1 ms) CONFIG3H_unused=0x0 CONFIG3H~1=IOL1WAY,0x1,IOLOCK One-Way Set Enable bit CONFIG3H~2=ADCSEL,0x2,ADC 10 or 12 Bit Select CONFIG3H~3=PLLSEL,0x4,PLL Selection Bit CONFIG3H~4=MSSP7B_EN,0x8,MSSP address masking CONFIG3H~5=RESERVED,0xf0,RESERVED CONFIG3H~1~1=0x1,0x1,Enabled CONFIG3H~1~2=0x1,0x0,Disabled CONFIG3H~2~1=0x2,0x2,10 - Bit ADC Enabled CONFIG3H~2~2=0x2,0x0,12 - Bit ADC Enabed CONFIG3H~3~1=0x4,0x0,Selects 96MHz PLL CONFIG3H~3~2=0x4,0x4,Selects 4x PLL CONFIG3H~4~1=0x8,0x8,7 Bit address masking mode CONFIG3H~4~2=0x8,0x0,5 Bit address masking mode CONFIG3H~5~1=0xf0,0xf0,RESERVED CONFIG4L_unused=0x0 CONFIG4L~1=WPFP,0x7f,Write/Erase Protect Page Start/End Location CONFIG4L~2=WPCFG,0x80,Write/Erase Protect Configuration Region CONFIG4L~1~1=0x7f,0x0,Write Protect Program Flash Page 0 CONFIG4L~1~2=0x7f,0x1,Write Protect Program Flash Page 1 CONFIG4L~1~3=0x7f,0x2,Write Protect Program Flash Page 2 CONFIG4L~1~4=0x7f,0x3,Write Protect Program Flash Page 3 CONFIG4L~1~5=0x7f,0x4,Write Protect Program Flash Page 4 CONFIG4L~1~6=0x7f,0x5,Write Protect Program Flash Page 5 CONFIG4L~1~7=0x7f,0x6,Write Protect Program Flash Page 6 CONFIG4L~1~8=0x7f,0x7,Write Protect Program Flash Page 7 CONFIG4L~1~9=0x7f,0x8,Write Protect Program Flash Page 8 CONFIG4L~1~10=0x7f,0x9,Write Protect Program Flash Page 9 CONFIG4L~1~11=0x7f,0xa,Write Protect Program Flash Page 10 CONFIG4L~1~12=0x7f,0xb,Write Protect Program Flash Page 11 CONFIG4L~1~13=0x7f,0xc,Write Protect Program Flash Page 12 CONFIG4L~1~14=0x7f,0xd,Write Protect Program Flash Page 13 CONFIG4L~1~15=0x7f,0xe,Write Protect Program Flash Page 14 CONFIG4L~1~16=0x7f,0xf,Write Protect Program Flash Page 15 CONFIG4L~1~17=0x7f,0x10,Write Protect Program Flash Page 16 CONFIG4L~1~18=0x7f,0x11,Write Protect Program Flash Page 17 CONFIG4L~1~19=0x7f,0x12,Write Protect Program Flash Page 18 CONFIG4L~1~20=0x7f,0x13,Write Protect Program Flash Page 19 CONFIG4L~1~21=0x7f,0x14,Write Protect Program Flash Page 20 CONFIG4L~1~22=0x7f,0x15,Write Protect Program Flash Page 21 CONFIG4L~1~23=0x7f,0x16,Write Protect Program Flash Page 22 CONFIG4L~1~24=0x7f,0x17,Write Protect Program Flash Page 23 CONFIG4L~1~25=0x7f,0x18,Write Protect Program Flash Page 24 CONFIG4L~1~26=0x7f,0x19,Write Protect Program Flash Page 25 CONFIG4L~1~27=0x7f,0x1a,Write Protect Program Flash Page 26 CONFIG4L~1~28=0x7f,0x1b,Write Protect Program Flash Page 27 CONFIG4L~1~29=0x7f,0x1c,Write Protect Program Flash Page 28 CONFIG4L~1~30=0x7f,0x1d,Write Protect Program Flash Page 29 CONFIG4L~1~31=0x7f,0x1e,Write Protect Program Flash Page 30 CONFIG4L~1~32=0x7f,0x1f,Write Protect Program Flash Page 31 CONFIG4L~1~33=0x7f,0x20,Write Protect Program Flash Page 32 CONFIG4L~1~34=0x7f,0x21,Write Protect Program Flash Page 33 CONFIG4L~1~35=0x7f,0x22,Write Protect Program Flash Page 34 CONFIG4L~1~36=0x7f,0x23,Write Protect Program Flash Page 35 CONFIG4L~1~37=0x7f,0x24,Write Protect Program Flash Page 36 CONFIG4L~1~38=0x7f,0x25,Write Protect Program Flash Page 37 CONFIG4L~1~39=0x7f,0x26,Write Protect Program Flash Page 38 CONFIG4L~1~40=0x7f,0x27,Write Protect Program Flash Page 39 CONFIG4L~1~41=0x7f,0x28,Write Protect Program Flash Page 40 CONFIG4L~1~42=0x7f,0x29,Write Protect Program Flash Page 41 CONFIG4L~1~43=0x7f,0x2a,Write Protect Program Flash Page 42 CONFIG4L~1~44=0x7f,0x2b,Write Protect Program Flash Page 43 CONFIG4L~1~45=0x7f,0x2c,Write Protect Program Flash Page 44 CONFIG4L~1~46=0x7f,0x2d,Write Protect Program Flash Page 45 CONFIG4L~1~47=0x7f,0x2e,Write Protect Program Flash Page 46 CONFIG4L~1~48=0x7f,0x2f,Write Protect Program Flash Page 47 CONFIG4L~1~49=0x7f,0x30,Write Protect Program Flash Page 48 CONFIG4L~1~50=0x7f,0x31,Write Protect Program Flash Page 49 CONFIG4L~1~51=0x7f,0x32,Write Protect Program Flash Page 50 CONFIG4L~1~52=0x7f,0x33,Write Protect Program Flash Page 51 CONFIG4L~1~53=0x7f,0x34,Write Protect Program Flash Page 52 CONFIG4L~1~54=0x7f,0x35,Write Protect Program Flash Page 53 CONFIG4L~1~55=0x7f,0x36,Write Protect Program Flash Page 54 CONFIG4L~1~56=0x7f,0x37,Write Protect Program Flash Page 55 CONFIG4L~1~57=0x7f,0x38,Write Protect Program Flash Page 56 CONFIG4L~1~58=0x7f,0x39,Write Protect Program Flash Page 57 CONFIG4L~1~59=0x7f,0x3a,Write Protect Program Flash Page 58 CONFIG4L~1~60=0x7f,0x3b,Write Protect Program Flash Page 59 CONFIG4L~1~61=0x7f,0x3c,Write Protect Program Flash Page 60 CONFIG4L~1~62=0x7f,0x3d,Write Protect Program Flash Page 61 CONFIG4L~1~63=0x7f,0x3e,Write Protect Program Flash Page 62 CONFIG4L~1~64=0x7f,0x3f,Write Protect Program Flash Page 63 CONFIG4L~1~65=0x7f,0x40,Write Protect Program Flash Page 64 CONFIG4L~1~66=0x7f,0x41,Write Protect Program Flash Page 65 CONFIG4L~1~67=0x7f,0x42,Write Protect Program Flash Page 66 CONFIG4L~1~68=0x7f,0x43,Write Protect Program Flash Page 67 CONFIG4L~1~69=0x7f,0x44,Write Protect Program Flash Page 68 CONFIG4L~1~70=0x7f,0x45,Write Protect Program Flash Page 69 CONFIG4L~1~71=0x7f,0x46,Write Protect Program Flash Page 70 CONFIG4L~1~72=0x7f,0x47,Write Protect Program Flash Page 71 CONFIG4L~1~73=0x7f,0x48,Write Protect Program Flash Page 72 CONFIG4L~1~74=0x7f,0x49,Write Protect Program Flash Page 73 CONFIG4L~1~75=0x7f,0x4a,Write Protect Program Flash Page 74 CONFIG4L~1~76=0x7f,0x4b,Write Protect Program Flash Page 75 CONFIG4L~1~77=0x7f,0x4c,Write Protect Program Flash Page 76 CONFIG4L~1~78=0x7f,0x4d,Write Protect Program Flash Page 77 CONFIG4L~1~79=0x7f,0x4e,Write Protect Program Flash Page 78 CONFIG4L~1~80=0x7f,0x4f,Write Protect Program Flash Page 79 CONFIG4L~1~81=0x7f,0x50,Write Protect Program Flash Page 80 CONFIG4L~1~82=0x7f,0x51,Write Protect Program Flash Page 81 CONFIG4L~1~83=0x7f,0x52,Write Protect Program Flash Page 82 CONFIG4L~1~84=0x7f,0x53,Write Protect Program Flash Page 83 CONFIG4L~1~85=0x7f,0x54,Write Protect Program Flash Page 84 CONFIG4L~1~86=0x7f,0x55,Write Protect Program Flash Page 85 CONFIG4L~1~87=0x7f,0x56,Write Protect Program Flash Page 86 CONFIG4L~1~88=0x7f,0x57,Write Protect Program Flash Page 87 CONFIG4L~1~89=0x7f,0x58,Write Protect Program Flash Page 88 CONFIG4L~1~90=0x7f,0x59,Write Protect Program Flash Page 89 CONFIG4L~1~91=0x7f,0x5a,Write Protect Program Flash Page 90 CONFIG4L~1~92=0x7f,0x5b,Write Protect Program Flash Page 91 CONFIG4L~1~93=0x7f,0x5c,Write Protect Program Flash Page 92 CONFIG4L~1~94=0x7f,0x5d,Write Protect Program Flash Page 93 CONFIG4L~1~95=0x7f,0x5e,Write Protect Program Flash Page 94 CONFIG4L~1~96=0x7f,0x5f,Write Protect Program Flash Page 95 CONFIG4L~1~97=0x7f,0x60,Write Protect Program Flash Page 96 CONFIG4L~1~98=0x7f,0x61,Write Protect Program Flash Page 97 CONFIG4L~1~99=0x7f,0x62,Write Protect Program Flash Page 98 CONFIG4L~1~100=0x7f,0x63,Write Protect Program Flash Page 99 CONFIG4L~1~101=0x7f,0x64,Write Protect Program Flash Page 100 CONFIG4L~1~102=0x7f,0x65,Write Protect Program Flash Page 101 CONFIG4L~1~103=0x7f,0x66,Write Protect Program Flash Page 102 CONFIG4L~1~104=0x7f,0x67,Write Protect Program Flash Page 103 CONFIG4L~1~105=0x7f,0x68,Write Protect Program Flash Page 104 CONFIG4L~1~106=0x7f,0x69,Write Protect Program Flash Page 105 CONFIG4L~1~107=0x7f,0x6a,Write Protect Program Flash Page 106 CONFIG4L~1~108=0x7f,0x6b,Write Protect Program Flash Page 107 CONFIG4L~1~109=0x7f,0x6c,Write Protect Program Flash Page 108 CONFIG4L~1~110=0x7f,0x6d,Write Protect Program Flash Page 109 CONFIG4L~1~111=0x7f,0x6e,Write Protect Program Flash Page 110 CONFIG4L~1~112=0x7f,0x6f,Write Protect Program Flash Page 111 CONFIG4L~1~113=0x7f,0x70,Write Protect Program Flash Page 112 CONFIG4L~1~114=0x7f,0x71,Write Protect Program Flash Page 113 CONFIG4L~1~115=0x7f,0x72,Write Protect Program Flash Page 114 CONFIG4L~1~116=0x7f,0x73,Write Protect Program Flash Page 115 CONFIG4L~1~117=0x7f,0x74,Write Protect Program Flash Page 116 CONFIG4L~1~118=0x7f,0x75,Write Protect Program Flash Page 117 CONFIG4L~1~119=0x7f,0x76,Write Protect Program Flash Page 118 CONFIG4L~1~120=0x7f,0x77,Write Protect Program Flash Page 119 CONFIG4L~1~121=0x7f,0x78,Write Protect Program Flash Page 120 CONFIG4L~1~122=0x7f,0x79,Write Protect Program Flash Page 121 CONFIG4L~1~123=0x7f,0x7a,Write Protect Program Flash Page 122 CONFIG4L~1~124=0x7f,0x7b,Write Protect Program Flash Page 123 CONFIG4L~1~125=0x7f,0x7c,Write Protect Program Flash Page 124 CONFIG4L~1~126=0x7f,0x7d,Write Protect Program Flash Page 125 CONFIG4L~1~127=0x7f,0x7e,Write Protect Program Flash Page 126 CONFIG4L~1~128=0x7f,0x7f,Write Protect Program Flash Page 127 CONFIG4L~2~1=0x80,0x80,Disabled CONFIG4L~2~2=0x80,0x0,Enabled CONFIG4H_unused=0x0 CONFIG4H~1=WPDIS,0x1,Write Protect Disable bit CONFIG4H~2=WPEND,0x2,Write/Erase Protect Region Select bit (valid when WPDIS = 0) CONFIG4H~3=LS48MHZ,0x8,Low Speed USB mode with 48 MHz system clock bit CONFIG4H~4=RESERVED,0xf0,RESERVED CONFIG4H~1~1=0x1,0x1,Disabled CONFIG4H~1~2=0x1,0x0,Enabled CONFIG4H~2~1=0x2,0x2,Pages WPFP<6:0> to (Configuration Words page) write/erase protected CONFIG4H~2~2=0x2,0x0,Page 0 to WPFP<6:0> erase/write-protected CONFIG4H~3~1=0x8,0x0,System clock at 24 MHz USB CLKEN divide-by is set to 4 CONFIG4H~3~2=0x8,0x8,System clock at 48 MHz USB CLKEN divide-by is set to 8 CONFIG4H~4~1=0xf0,0xf0,RESERVED erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F43K20] pgmmem=0x0 ~pgmmem=0x1fff cfgmem=0x300000 ~cfgmem=0x30000d userid=0x200000 ~userid=0x200007 eedata=0x0 ~eedata=0xff devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0x20c0 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000a=CONFIG6L 0x30000b=CONFIG6H 0x30000c=CONFIG7L 0x30000d=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=FOSC,0xf,Oscillator Selection bits CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable bit CONFIG1H~3=IESO,0x80,Internal/External Oscillator Switchover bit CONFIG1H~1~1=0xc,0xc,11XX External RC oscillator, CLKOUT function on RA6 CONFIG1H~1~2=0xe,0xa,101X External RC oscillator, CLKOUT function on RA6 CONFIG1H~1~3=0xf,0x9,Internal oscillator block, CLKOUT function on RA6, port function on RA7 CONFIG1H~1~4=0xf,0x8,Internal oscillator block, port function on RA6 and RA7 CONFIG1H~1~5=0xf,0x7,External RC oscillator, port function on RA6 CONFIG1H~1~6=0xf,0x6,HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) CONFIG1H~1~7=0xf,0x5,EC oscillator, port function on RA6 CONFIG1H~1~8=0xf,0x4,EC oscillator, CLKOUT function on RA6 CONFIG1H~1~9=0xf,0x3,External RC oscillator, CLKOUT function on RA6 CONFIG1H~1~10=0xf,0x2,HS oscillator CONFIG1H~1~11=0xf,0x1,XT oscillator CONFIG1H~1~12=0xf,0x0,LP oscillator CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PWRT,0x1,Power-up Timer Enable bit CONFIG2L~2=BOREN,0x6,Brown-out Reset Enable bits CONFIG2L~3=BORV,0x18,Brown Out Reset Voltage bits CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Brown-out Reset enabled in hardware only (SBOREN is disabled) CONFIG2L~2~2=0x6,0x4,Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) CONFIG2L~2~3=0x6,0x2,Enabled CONFIG2L~2~4=0x6,0x0,Disabled CONFIG2L~3~1=0x18,0x18,VBOR set to 1.8 V nominal CONFIG2L~3~2=0x18,0x10,VBOR set to 2.2 V nominal CONFIG2L~3~3=0x18,0x8,VBOR set to 2.7 V nominal CONFIG2L~3~4=0x18,0x0,VBOR set to 3.0 V nominal CONFIG2H_unused=0x0 CONFIG2H~1=WDTEN,0x1,Watchdog Timer Enable bit CONFIG2H~2=WDTPS,0x1e,Watchdog Timer Postscale Select bits CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled CONFIG2H~2~1=0x1e,0x1e,1:32768 CONFIG2H~2~2=0x1e,0x1c,1:16384 CONFIG2H~2~3=0x1e,0x1a,1:8192 CONFIG2H~2~4=0x1e,0x18,1:4096 CONFIG2H~2~5=0x1e,0x16,1:2048 CONFIG2H~2~6=0x1e,0x14,1:1024 CONFIG2H~2~7=0x1e,0x12,1:512 CONFIG2H~2~8=0x1e,0x10,1:256 CONFIG2H~2~9=0x1e,0xe,1:128 CONFIG2H~2~10=0x1e,0xc,1:64 CONFIG2H~2~11=0x1e,0xa,1:32 CONFIG2H~2~12=0x1e,0x8,1:16 CONFIG2H~2~13=0x1e,0x6,1:8 CONFIG2H~2~14=0x1e,0x4,1:4 CONFIG2H~2~15=0x1e,0x2,1:2 CONFIG2H~2~16=0x1e,0x0,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 MUX bit CONFIG3H~2=PBADEN,0x2,PORTB A/D Enable bit CONFIG3H~3=LPT1OSC,0x4,Low-Power Timer1 Oscillator Enable bit CONFIG3H~4=HFOFST,0x8,HFINTOSC Fast Start-up CONFIG3H~5=MCLRE,0x80,MCLR Pin Enable bit CONFIG3H~1~1=0x1,0x1,CCP2 input/output is multiplexed with RC1 CONFIG3H~1~2=0x1,0x0,CCP2 input/output is multiplexed with RB3 CONFIG3H~2~1=0x2,0x2,Enabled CONFIG3H~2~2=0x2,0x0,Disabled CONFIG3H~3~1=0x4,0x4,Enabled CONFIG3H~3~2=0x4,0x0,Disabled CONFIG3H~4~1=0x8,0x8,Enabled CONFIG3H~4~2=0x8,0x0,Disabled CONFIG3H~5~1=0x80,0x80,Enabled CONFIG3H~5~2=0x80,0x0,Disabled CONFIG4L_unused=0x0 CONFIG4L~1=STVREN,0x1,Stack Full/Underflow Reset Enable bit CONFIG4L~2=LVP,0x4,Single-Supply ICSP Enable bit CONFIG4L~3=XINST,0x40,Extended Instruction Set Enable bit CONFIG4L~4=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x40,0x40,Enabled CONFIG4L~3~2=0x40,0x0,Disabled CONFIG4L~4~1=0x80,0x80,Disabled CONFIG4L~4~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP0,0x1,Code Protection Block 0 CONFIG5L~2=CP1,0x2,Code Protection Block 1 CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x0,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x0,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPB,0x40,Boot Block Code Protection bit CONFIG5H~2=CPD,0x80,Data EEPROM Code Protection bit CONFIG5H~1~1=0x40,0x40,Disabled CONFIG5H~1~2=0x40,0x0,Enabled CONFIG5H~2~1=0x80,0x80,Disabled CONFIG5H~2~2=0x80,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT0,0x1,Write Protection Block 0 CONFIG6L~2=WRT1,0x2,Write Protection Block 1 CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x0,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x0,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTC,0x20,Configuration Register Write Protection bit CONFIG6H~2=WRTB,0x40,Boot Block Write Protection bit CONFIG6H~3=WRTD,0x80,Data EEPROM Write Protection bit CONFIG6H~1~1=0x20,0x20,Disabled CONFIG6H~1~2=0x20,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x80,0x80,Disabled CONFIG6H~3~2=0x80,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR0,0x1,Table Read Protection Block 0 CONFIG7L~2=EBTR1,0x2,Table Read Protection Block 1 CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x0,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x0,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Boot Block Table Read Protection bit CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F4458] pgmmem=0x0 ~pgmmem=0x5fff cfgmem=0x300000 ~cfgmem=0x30000d userid=0x200000 ~userid=0x200007 eedata=0x0 ~eedata=0xff devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0x2a20 configslots=14 0x300000=CONFIG1L 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000a=CONFIG6L 0x30000b=CONFIG6H 0x30000c=CONFIG7L 0x30000d=CONFIG7H CONFIG1L_unused=0x0 CONFIG1L~1=PLLDIV,0x7,96MHz PLL Prescaler CONFIG1L~2=CPUDIV,0x18,CPU System Clock Postscaler CONFIG1L~3=USBPLL,0x20,Full-Speed USB Clock Source Selection CONFIG1L~1~1=0x7,0x7,Divide by 12 (48MHz input) CONFIG1L~1~2=0x7,0x6,Divide by 10 (40MHz input) CONFIG1L~1~3=0x7,0x5,Divide by 6 (24MHz input) CONFIG1L~1~4=0x7,0x4,Divide by 5 (20MHz input) CONFIG1L~1~5=0x7,0x3,Divide by 4 (16MHz input) CONFIG1L~1~6=0x7,0x2,Divide by 3 (12MHz input) CONFIG1L~1~7=0x7,0x1,Divide by 2 (8MHz input) CONFIG1L~1~8=0x7,0x0,No Divide (4MHz input) CONFIG1L~2~1=0x18,0x18,[OSC1/OSC2 Src: /4][96MHz PLL Src: /6] CONFIG1L~2~2=0x18,0x10,[OSC1/OSC2 Src: /3][96MHz PLL Src: /4] CONFIG1L~2~3=0x18,0x8,[OSC1/OSC2 Src: /2][96MHz PLL Src: /3] CONFIG1L~2~4=0x18,0x0,[OSC1/OSC2 Src: /1][96MHz PLL Src: /2] CONFIG1L~3~1=0x20,0x20,Clock src from 96MHz PLL/2 CONFIG1L~3~2=0x20,0x0,Clock src from OSC1/OSC2 CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xf,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xe,0xe,HS: HS+PLL, USB-HS CONFIG1H~1~2=0xe,0xc,HS: USB-HS CONFIG1H~1~3=0xf,0xb,INTOSC: USB-HS CONFIG1H~1~4=0xf,0xa,INTOSC: USB-XT CONFIG1H~1~5=0xf,0x9,INTOSC: INTOSC+CLK0{RA6}, USB-EC CONFIG1H~1~6=0xf,0x8,INTOSC: INTOSC+RA6, USB-EC CONFIG1H~1~7=0xf,0x7,EC: EC+PLL, EC+PLL+CLKO{RA6}, USB-EC CONFIG1H~1~8=0xf,0x6,EC: EC+PLL, EC+PLL+RA6, USB-EC CONFIG1H~1~9=0xf,0x5,EC: EC+CLKO{RA6}, USB-EC CONFIG1H~1~10=0xf,0x4,EC: EC+RA6, USB-EC CONFIG1H~1~11=0xe,0x2,XT: XT+PLL, USB-XT CONFIG1H~1~12=0xe,0x0,XT: USB-XT CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~4=VREGEN,0x20,USB Voltage Regulator CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x8,4.2V CONFIG2L~3~4=0x18,0x0,4.5V CONFIG2L~4~1=0x20,0x20,Enabled CONFIG2L~4~2=0x20,0x0,Disabled CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1e,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1e,0x1e,1:32768 CONFIG2H~2~2=0x1e,0x1c,1:16384 CONFIG2H~2~3=0x1e,0x1a,1:8192 CONFIG2H~2~4=0x1e,0x18,1:4096 CONFIG2H~2~5=0x1e,0x16,1:2048 CONFIG2H~2~6=0x1e,0x14,1:1024 CONFIG2H~2~7=0x1e,0x12,1:512 CONFIG2H~2~8=0x1e,0x10,1:256 CONFIG2H~2~9=0x1e,0xe,1:128 CONFIG2H~2~10=0x1e,0xc,1:64 CONFIG2H~2~11=0x1e,0xa,1:32 CONFIG2H~2~12=0x1e,0x8,1:16 CONFIG2H~2~13=0x1e,0x6,1:8 CONFIG2H~2~14=0x1e,0x4,1:4 CONFIG2H~2~15=0x1e,0x2,1:2 CONFIG2H~2~16=0x1e,0x0,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=PBADEN,0x2,PortB A/D Enable CONFIG3H~3=LPT1OSC,0x4,Low Power Timer1 Osc enable CONFIG3H~4=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RB3 CONFIG3H~2~1=0x2,0x2,PORTB<4:0> configured as analog inputs on RESET CONFIG3H~2~2=0x2,0x0,PORTB<4:0> configured as digital I/O on RESET CONFIG3H~3~1=0x4,0x4,Enabled CONFIG3H~3~2=0x4,0x0,Disabled CONFIG3H~4~1=0x80,0x80,MCLR Enabled,RE3 Disabled CONFIG3H~4~2=0x80,0x0,MCLR Disabled,RE3 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=ENICPORT,0x20,Dedicated In-Circuit Port {ICD/ICSP} CONFIG4L~4=XINST,0x40,Extended Instruction Set Enable bit CONFIG4L~5=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x20,0x20,Enabled CONFIG4L~3~2=0x20,0x0,Disabled CONFIG4L~4~1=0x40,0x40,Enabled CONFIG4L~4~2=0x40,0x0,Disabled CONFIG4L~5~1=0x80,0x80,Disabled CONFIG4L~5~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-01FFF CONFIG5L~2=CP_1,0x2,Code Protect 02000-03FFF CONFIG5L~3=CP_2,0x4,Code Protect 04000-05FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x0,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x0,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x0,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPB,0x40,Code Protect Boot CONFIG5H~2=CPD,0x80,Data EE Read Protect CONFIG5H~1~1=0x40,0x40,Disabled CONFIG5H~1~2=0x40,0x0,Enabled CONFIG5H~2~1=0x80,0x80,Disabled CONFIG5H~2~2=0x80,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-01FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 02000-03FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 04000-05FFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x0,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x0,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x0,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTC,0x20,Config. Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTD,0x80,Data EE Write Protect CONFIG6H~1~1=0x20,0x20,Disabled CONFIG6H~1~2=0x20,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x80,0x80,Disabled CONFIG6H~3~2=0x80,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-01FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 02000-03FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 04000-05FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x0,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x0,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x0,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE_24xx05 prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F44J11] pgmmem=0x0 ~pgmmem=0x3ff7 cfgmem=0x3ff8 ~cfgmem=0x3fff userid= ~userid= eedata= ~eedata= devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0x4de0 configslots=8 0x3ff8=CONFIG1L 0x3ff9=CONFIG1H 0x3ffa=CONFIG2L 0x3ffb=CONFIG2H 0x3ffc=CONFIG3L 0x3ffd=CONFIG3H 0x3ffe=CONFIG4L 0x3fff=CONFIG4H CONFIG1L_unused=0x0 CONFIG1L~1=WDTEN,0x1,Watchdog Timer CONFIG1L~2=STVREN,0x20,Stack Overflow/Underflow Reset CONFIG1L~3=XINST,0x40,Extended Instruction Set CONFIG1L~4=DEBUG,0x80,Background Debug CONFIG1L~1~1=0x1,0x1,Enabled CONFIG1L~1~2=0x1,0x0,Disabled CONFIG1L~2~1=0x20,0x20,Enabled CONFIG1L~2~2=0x20,0x0,Disabled CONFIG1L~3~1=0x40,0x40,Enabled CONFIG1L~3~2=0x40,0x0,Disabled CONFIG1L~4~1=0x80,0x80,Disabled CONFIG1L~4~2=0x80,0x0,Enabled CONFIG1H_unused=0x0 CONFIG1H~1=CP0,0x4,Code Protect CONFIG1H~2=SIGN,0x8,Config Word Signature Bit CONFIG1H~3=RESERVED,0xf0,RESERVED CONFIG1H~1~1=0x4,0x4,Disabled CONFIG1H~1~2=0x4,0x0,Enabled CONFIG1H~2~1=0x8,0x8,Bulk erase of memory not conducated CONFIG1H~2~2=0x8,0x0,Bulk erase of memory area complete CONFIG1H~3~1=0xf0,0xf0,RESERVED CONFIG2L_unused=0x0 CONFIG2L~1=OSC,0x7,Oscillator CONFIG2L~2=T1DIG,0x8,T1OSCEN Enforcement CONFIG2L~3=LPT1OSC,0x10,Low-Power Timer1 Oscillator CONFIG2L~4=FCMEN,0x40,Fail-Safe Clock Monitor CONFIG2L~5=IESO,0x80,Internal External Oscillator Switch Over Mode CONFIG2L~1~1=0x7,0x7,EC+PLL (CLKO-RA6) CONFIG2L~1~2=0x7,0x6,EC (CLKO-RA6) CONFIG2L~1~3=0x7,0x5,HS+PLL CONFIG2L~1~4=0x7,0x4,HS CONFIG2L~1~5=0x7,0x3,INTOSCPLLO (CLKO-RA6) CONFIG2L~1~6=0x7,0x2,INTOSCPLL CONFIG2L~1~7=0x7,0x1,INTOSCO (CLKO-RA6) CONFIG2L~1~8=0x7,0x0,INTOSC CONFIG2L~2~1=0x8,0x8,Enabled CONFIG2L~2~2=0x8,0x0,Disabled CONFIG2L~3~1=0x10,0x10,Disabled CONFIG2L~3~2=0x10,0x0,Enabled CONFIG2L~4~1=0x40,0x0,Disabled CONFIG2L~4~2=0x40,0x40,Enabled CONFIG2L~5~1=0x80,0x0,Disabled CONFIG2L~5~2=0x80,0x80,Enabled CONFIG2H_unused=0x0 CONFIG2H~1=WDTPS,0xf,Watchdog Postscaler CONFIG2H~2=RESERVED,0xf0,RESERVED CONFIG2H~1~1=0xf,0xf,1:32768 CONFIG2H~1~2=0xf,0xe,1:16384 CONFIG2H~1~3=0xf,0xd,1:8192 CONFIG2H~1~4=0xf,0xc,1:4096 CONFIG2H~1~5=0xf,0xb,1:2048 CONFIG2H~1~6=0xf,0xa,1:1024 CONFIG2H~1~7=0xf,0x9,1:512 CONFIG2H~1~8=0xf,0x8,1:256 CONFIG2H~1~9=0xf,0x7,1:128 CONFIG2H~1~10=0xf,0x6,1:64 CONFIG2H~1~11=0xf,0x5,1:32 CONFIG2H~1~12=0xf,0x4,1:16 CONFIG2H~1~13=0xf,0x3,1:8 CONFIG2H~1~14=0xf,0x2,1:4 CONFIG2H~1~15=0xf,0x1,1:2 CONFIG2H~1~16=0xf,0x0,1:1 CONFIG2H~2~1=0xf0,0xf0,RESERVED CONFIG3L_unused=0x0 CONFIG3L~1=DSWDTOSC,0x1,DSWDT Clock Select CONFIG3L~2=RTCOSC,0x2,RTCC Clock Select CONFIG3L~3=DSBOREN,0x4,Deep Sleep BOR CONFIG3L~4=DSWDTEN,0x8,Deep Sleep Watchdog Timer CONFIG3L~5=DSWDTPS,0xf0,Deep Sleep Watchdog Postscaler CONFIG3L~1~1=0x1,0x1,DSWDT uses INTRC CONFIG3L~1~2=0x1,0x0,DSWDT uses T1OSC/T1CKI CONFIG3L~2~1=0x2,0x2,RTCC uses T1OSC/T1CKI CONFIG3L~2~2=0x2,0x0,RTCC uses INTRC CONFIG3L~3~1=0x4,0x4,Enabled CONFIG3L~3~2=0x4,0x0,Disabled CONFIG3L~4~1=0x8,0x8,Enabled CONFIG3L~4~2=0x8,0x0,Disabled CONFIG3L~5~1=0xf0,0xf0,1:2,147,483,648 (25.7 days) CONFIG3L~5~2=0xf0,0xe0,1:536,870,912 (6.4 days) CONFIG3L~5~3=0xf0,0xd0,1:134,217,728 (38.5 hours) CONFIG3L~5~4=0xf0,0xc0,1:33,554,432 (9.6 hours) CONFIG3L~5~5=0xf0,0xb0,1:8,388,608 (2.4 hours) CONFIG3L~5~6=0xf0,0xa0,1:2,097,152 (36 minutes) CONFIG3L~5~7=0xf0,0x90,1:524,288 (9 minutes) CONFIG3L~5~8=0xf0,0x80,1:131,072 (135 seconds) CONFIG3L~5~9=0xf0,0x70,1:32,768 (34 seconds) CONFIG3L~5~10=0xf0,0x60,1:8,192 (8.5 seconds) CONFIG3L~5~11=0xf0,0x50,1:2,048 (2.1 seconds) CONFIG3L~5~12=0xf0,0x40,1:512 (528 ms) CONFIG3L~5~13=0xf0,0x30,1:128 (132 ms) CONFIG3L~5~14=0xf0,0x20,1:32 (33 ms) CONFIG3L~5~15=0xf0,0x10,1:8 (8.3 ms) CONFIG3L~5~16=0xf0,0x0,1:2 (2.1 ms) CONFIG3H_unused=0x0 CONFIG3H~1=IOL1WAY,0x1,IOLOCK One-Way Set Enable bit CONFIG3H~2=MSSP7B_EN,0x8,MSSP address masking CONFIG3H~3=RESERVED,0xf0,RESERVED CONFIG3H~1~1=0x1,0x1,Enabled CONFIG3H~1~2=0x1,0x0,Disabled CONFIG3H~2~1=0x8,0x8,7 Bit address masking mode CONFIG3H~2~2=0x8,0x0,5 Bit address masking mode CONFIG3H~3~1=0xf0,0xf0,RESERVED CONFIG4L_unused=0x0 CONFIG4L~1=WPFP,0xf,Write/Erase Protect Page Start/End Location CONFIG4L~2=WPEND,0x40,Write/Erase Protect Region Select bit (valid when WPDIS = 0) CONFIG4L~3=WPCFG,0x80,Write/Erase Protect Configuration Region CONFIG4L~1~1=0xf,0x0,Write Protect Program Flash Page 0 CONFIG4L~1~2=0xf,0x1,Write Protect Program Flash Page 1 CONFIG4L~1~3=0xf,0x2,Write Protect Program Flash Page 2 CONFIG4L~1~4=0xf,0x3,Write Protect Program Flash Page 3 CONFIG4L~1~5=0xf,0x4,Write Protect Program Flash Page 4 CONFIG4L~1~6=0xf,0x5,Write Protect Program Flash Page 5 CONFIG4L~1~7=0xf,0x6,Write Protect Program Flash Page 6 CONFIG4L~1~8=0xf,0x7,Write Protect Program Flash Page 7 CONFIG4L~1~9=0xf,0x8,Write Protect Program Flash Page 8 CONFIG4L~1~10=0xf,0x9,Write Protect Program Flash Page 9 CONFIG4L~1~11=0xf,0xa,Write Protect Program Flash Page 10 CONFIG4L~1~12=0xf,0xb,Write Protect Program Flash Page 11 CONFIG4L~1~13=0xf,0xc,Write Protect Program Flash Page 12 CONFIG4L~1~14=0xf,0xd,Write Protect Program Flash Page 13 CONFIG4L~1~15=0xf,0xe,Write Protect Program Flash Page 14 CONFIG4L~1~16=0xf,0xf,Write Protect Program Flash Page 15 CONFIG4L~2~1=0x40,0x40,Pages WPFP<5:0> to (Configuration Words page) write/erase protected CONFIG4L~2~2=0x40,0x0,Page 0 to WPFP<5:0> erase/write-protected CONFIG4L~3~1=0x80,0x80,Disabled CONFIG4L~3~2=0x80,0x0,Enabled CONFIG4H_unused=0x0 CONFIG4H~1=WPDIS,0x1,Write Protect Disable bit CONFIG4H~2=RESERVED,0xf0,RESERVED CONFIG4H~1~1=0x1,0x1,Disabled CONFIG4H~1~2=0x1,0x0,Enabled CONFIG4H~2~1=0xf0,0xf0,RESERVED erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F44J50] pgmmem=0x0 ~pgmmem=0x3ff7 cfgmem=0x3ff8 ~cfgmem=0x3fff userid= ~userid= eedata= ~eedata= devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0x4c60 configslots=8 0x3ff8=CONFIG1L 0x3ff9=CONFIG1H 0x3ffa=CONFIG2L 0x3ffb=CONFIG2H 0x3ffc=CONFIG3L 0x3ffd=CONFIG3H 0x3ffe=CONFIG4L 0x3fff=CONFIG4H CONFIG1L_unused=0x0 CONFIG1L~1=WDTEN,0x1,Watchdog Timer CONFIG1L~2=PLLDIV,0xe,PLL Prescaler Selection bits CONFIG1L~3=STVREN,0x20,Stack Overflow/Underflow Reset CONFIG1L~4=XINST,0x40,Extended Instruction Set CONFIG1L~5=DEBUG,0x80,Background Debug CONFIG1L~1~1=0x1,0x1,Enabled CONFIG1L~1~2=0x1,0x0,Disabled CONFIG1L~2~1=0xe,0xe,No prescale (4 MHz oscillator input drives PLL directly) CONFIG1L~2~2=0xe,0xc,Divide by 2 (8 MHz oscillator input) CONFIG1L~2~3=0xe,0xa,Divide by 3 (12 MHz oscillator input) CONFIG1L~2~4=0xe,0x8,Divide by 4 (16 MHz oscillator input) CONFIG1L~2~5=0xe,0x6,Divide by 5 (20 MHz oscillator input) CONFIG1L~2~6=0xe,0x4,Divide by 6 (24 MHz oscillator input) CONFIG1L~2~7=0xe,0x2,Divide by 10 (40 MHz oscillator input) CONFIG1L~2~8=0xe,0x0,Divide by 12 (48 MHz oscillator input) CONFIG1L~3~1=0x20,0x20,Enabled CONFIG1L~3~2=0x20,0x0,Disabled CONFIG1L~4~1=0x40,0x40,Enabled CONFIG1L~4~2=0x40,0x0,Disabled CONFIG1L~5~1=0x80,0x80,Disabled CONFIG1L~5~2=0x80,0x0,Enabled CONFIG1H_unused=0x0 CONFIG1H~1=CPUDIV,0x3,CPU System Clock Postscaler CONFIG1H~2=CP0,0x4,Code Protect CONFIG1H~3=SIGN,0x8,Config Word Signature Bit CONFIG1H~4=RESERVED,0xf0,RESERVED CONFIG1H~1~1=0x3,0x3,No CPU system clock divide CONFIG1H~1~2=0x3,0x2,CPU system clock divide by 2 CONFIG1H~1~3=0x3,0x1,CPU system clock divide by 3 CONFIG1H~1~4=0x3,0x0,CPU system clock divide by 6 CONFIG1H~2~1=0x4,0x4,Disabled CONFIG1H~2~2=0x4,0x0,Enabled CONFIG1H~3~1=0x8,0x8,Bulk erase of memory not conducated CONFIG1H~3~2=0x8,0x0,Bulk erase of memory area complete CONFIG1H~4~1=0xf0,0xf0,RESERVED CONFIG2L_unused=0x0 CONFIG2L~1=OSC,0x7,Oscillator CONFIG2L~2=T1DIG,0x8,T1OSCEN Enforcement CONFIG2L~3=LPT1OSC,0x10,Low-Power Timer1 Oscillator CONFIG2L~4=FCMEN,0x40,Fail-Safe Clock Monitor CONFIG2L~5=IESO,0x80,Internal External Oscillator Switch Over Mode CONFIG2L~1~1=0x7,0x7,EC+PLL (CLKO-RA6), USB-EC+PLL CONFIG2L~1~2=0x7,0x6,EC (CLKO-RA6), USB-EC CONFIG2L~1~3=0x7,0x5,HS+PLL, USB-HS+PLL CONFIG2L~1~4=0x7,0x4,HS, USB-HS CONFIG2L~1~5=0x7,0x3,INTOSCPLLO (CLKO-RA6) CONFIG2L~1~6=0x7,0x2,INTOSCPLL CONFIG2L~1~7=0x7,0x1,INTOSCO (CLKO-RA6) CONFIG2L~1~8=0x7,0x0,INTOSC CONFIG2L~2~1=0x8,0x8,Enabled CONFIG2L~2~2=0x8,0x0,Disabled CONFIG2L~3~1=0x10,0x10,Disabled CONFIG2L~3~2=0x10,0x0,Enabled CONFIG2L~4~1=0x40,0x0,Disabled CONFIG2L~4~2=0x40,0x40,Enabled CONFIG2L~5~1=0x80,0x0,Disabled CONFIG2L~5~2=0x80,0x80,Enabled CONFIG2H_unused=0x0 CONFIG2H~1=WDTPS,0xf,Watchdog Postscaler CONFIG2H~2=RESERVED,0xf0,RESERVED CONFIG2H~1~1=0xf,0xf,1:32768 CONFIG2H~1~2=0xf,0xe,1:16384 CONFIG2H~1~3=0xf,0xd,1:8192 CONFIG2H~1~4=0xf,0xc,1:4096 CONFIG2H~1~5=0xf,0xb,1:2048 CONFIG2H~1~6=0xf,0xa,1:1024 CONFIG2H~1~7=0xf,0x9,1:512 CONFIG2H~1~8=0xf,0x8,1:256 CONFIG2H~1~9=0xf,0x7,1:128 CONFIG2H~1~10=0xf,0x6,1:64 CONFIG2H~1~11=0xf,0x5,1:32 CONFIG2H~1~12=0xf,0x4,1:16 CONFIG2H~1~13=0xf,0x3,1:8 CONFIG2H~1~14=0xf,0x2,1:4 CONFIG2H~1~15=0xf,0x1,1:2 CONFIG2H~1~16=0xf,0x0,1:1 CONFIG2H~2~1=0xf0,0xf0,RESERVED CONFIG3L_unused=0x0 CONFIG3L~1=DSWDTOSC,0x1,DSWDT Clock Select CONFIG3L~2=RTCOSC,0x2,RTCC Clock Select CONFIG3L~3=DSBOREN,0x4,Deep Sleep BOR CONFIG3L~4=DSWDTEN,0x8,Deep Sleep Watchdog Timer CONFIG3L~5=DSWDTPS,0xf0,Deep Sleep Watchdog Postscaler CONFIG3L~1~1=0x1,0x1,DSWDT uses INTRC CONFIG3L~1~2=0x1,0x0,DSWDT uses T1OSC/T1CKI CONFIG3L~2~1=0x2,0x2,RTCC uses T1OSC/T1CKI CONFIG3L~2~2=0x2,0x0,RTCC uses INTRC CONFIG3L~3~1=0x4,0x4,Enabled CONFIG3L~3~2=0x4,0x0,Disabled CONFIG3L~4~1=0x8,0x8,Enabled CONFIG3L~4~2=0x8,0x0,Disabled CONFIG3L~5~1=0xf0,0xf0,1:2,147,483,648 (25.7 days) CONFIG3L~5~2=0xf0,0xe0,1:536,870,912 (6.4 days) CONFIG3L~5~3=0xf0,0xd0,1:134,217,728 (38.5 hours) CONFIG3L~5~4=0xf0,0xc0,1:33,554,432 (9.6 hours) CONFIG3L~5~5=0xf0,0xb0,1:8,388,608 (2.4 hours) CONFIG3L~5~6=0xf0,0xa0,1:2,097,152 (36 minutes) CONFIG3L~5~7=0xf0,0x90,1:524,288 (9 minutes) CONFIG3L~5~8=0xf0,0x80,1:131,072 (135 seconds) CONFIG3L~5~9=0xf0,0x70,1:32,768 (34 seconds) CONFIG3L~5~10=0xf0,0x60,1:8,192 (8.5 seconds) CONFIG3L~5~11=0xf0,0x50,1:2,048 (2.1 seconds) CONFIG3L~5~12=0xf0,0x40,1:512 (528 ms) CONFIG3L~5~13=0xf0,0x30,1:128 (132 ms) CONFIG3L~5~14=0xf0,0x20,1:32 (33 ms) CONFIG3L~5~15=0xf0,0x10,1:8 (8.3 ms) CONFIG3L~5~16=0xf0,0x0,1:2 (2.1 ms) CONFIG3H_unused=0x0 CONFIG3H~1=IOL1WAY,0x1,IOLOCK One-Way Set Enable bit CONFIG3H~2=MSSP7B_EN,0x8,MSSP address masking CONFIG3H~3=RESERVED,0xf0,RESERVED CONFIG3H~1~1=0x1,0x1,Enabled CONFIG3H~1~2=0x1,0x0,Disabled CONFIG3H~2~1=0x8,0x8,7 Bit address masking mode CONFIG3H~2~2=0x8,0x0,5 Bit address masking mode CONFIG3H~3~1=0xf0,0xf0,RESERVED CONFIG4L_unused=0x0 CONFIG4L~1=WPFP,0xf,Write/Erase Protect Page Start/End Location CONFIG4L~2=WPEND,0x40,Write/Erase Protect Region Select bit (valid when WPDIS = 0) CONFIG4L~3=WPCFG,0x80,Write/Erase Protect Configuration Region CONFIG4L~1~1=0xf,0x0,Write Protect Program Flash Page 0 CONFIG4L~1~2=0xf,0x1,Write Protect Program Flash Page 1 CONFIG4L~1~3=0xf,0x2,Write Protect Program Flash Page 2 CONFIG4L~1~4=0xf,0x3,Write Protect Program Flash Page 3 CONFIG4L~1~5=0xf,0x4,Write Protect Program Flash Page 4 CONFIG4L~1~6=0xf,0x5,Write Protect Program Flash Page 5 CONFIG4L~1~7=0xf,0x6,Write Protect Program Flash Page 6 CONFIG4L~1~8=0xf,0x7,Write Protect Program Flash Page 7 CONFIG4L~1~9=0xf,0x8,Write Protect Program Flash Page 8 CONFIG4L~1~10=0xf,0x9,Write Protect Program Flash Page 9 CONFIG4L~1~11=0xf,0xa,Write Protect Program Flash Page 10 CONFIG4L~1~12=0xf,0xb,Write Protect Program Flash Page 11 CONFIG4L~1~13=0xf,0xc,Write Protect Program Flash Page 12 CONFIG4L~1~14=0xf,0xd,Write Protect Program Flash Page 13 CONFIG4L~1~15=0xf,0xe,Write Protect Program Flash Page 14 CONFIG4L~1~16=0xf,0xf,Write Protect Program Flash Page 15 CONFIG4L~2~1=0x40,0x40,Pages WPFP<5:0> to (Configuration Words page) write/erase protected CONFIG4L~2~2=0x40,0x0,Page 0 to WPFP<5:0> erase/write-protected CONFIG4L~3~1=0x80,0x80,Disabled CONFIG4L~3~2=0x80,0x0,Enabled CONFIG4H_unused=0x0 CONFIG4H~1=WPDIS,0x1,Write Protect Disable bit CONFIG4H~2=RESERVED,0xf0,RESERVED CONFIG4H~1~1=0x1,0x1,Disabled CONFIG4H~1~2=0x1,0x0,Enabled CONFIG4H~2~1=0xf0,0xf0,RESERVED erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F4553] pgmmem=0x0 ~pgmmem=0x7fff cfgmem=0x300000 ~cfgmem=0x30000d userid=0x200000 ~userid=0x200007 eedata=0x0 ~eedata=0xff devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0x2a00 configslots=14 0x300000=CONFIG1L 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000a=CONFIG6L 0x30000b=CONFIG6H 0x30000c=CONFIG7L 0x30000d=CONFIG7H CONFIG1L_unused=0x0 CONFIG1L~1=PLLDIV,0x7,96MHz PLL Prescaler CONFIG1L~2=CPUDIV,0x18,CPU System Clock Postscaler CONFIG1L~3=USBPLL,0x20,Full-Speed USB Clock Source Selection CONFIG1L~1~1=0x7,0x7,Divide by 12 (48MHz input) CONFIG1L~1~2=0x7,0x6,Divide by 10 (40MHz input) CONFIG1L~1~3=0x7,0x5,Divide by 6 (24MHz input) CONFIG1L~1~4=0x7,0x4,Divide by 5 (20MHz input) CONFIG1L~1~5=0x7,0x3,Divide by 4 (16MHz input) CONFIG1L~1~6=0x7,0x2,Divide by 3 (12MHz input) CONFIG1L~1~7=0x7,0x1,Divide by 2 (8MHz input) CONFIG1L~1~8=0x7,0x0,No Divide (4MHz input) CONFIG1L~2~1=0x18,0x18,[OSC1/OSC2 Src: /4][96MHz PLL Src: /6] CONFIG1L~2~2=0x18,0x10,[OSC1/OSC2 Src: /3][96MHz PLL Src: /4] CONFIG1L~2~3=0x18,0x8,[OSC1/OSC2 Src: /2][96MHz PLL Src: /3] CONFIG1L~2~4=0x18,0x0,[OSC1/OSC2 Src: /1][96MHz PLL Src: /2] CONFIG1L~3~1=0x20,0x20,Clock src from 96MHz PLL/2 CONFIG1L~3~2=0x20,0x0,Clock src from OSC1/OSC2 CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xf,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xe,0xe,HS: HS+PLL, USB-HS CONFIG1H~1~2=0xe,0xc,HS: USB-HS CONFIG1H~1~3=0xf,0xb,INTOSC: USB-HS CONFIG1H~1~4=0xf,0xa,INTOSC: USB-XT CONFIG1H~1~5=0xf,0x9,INTOSC: INTOSC+CLK0{RA6}, USB-EC CONFIG1H~1~6=0xf,0x8,INTOSC: INTOSC+RA6, USB-EC CONFIG1H~1~7=0xf,0x7,EC: EC+PLL, EC+PLL+CLKO{RA6}, USB-EC CONFIG1H~1~8=0xf,0x6,EC: EC+PLL, EC+PLL+RA6, USB-EC CONFIG1H~1~9=0xf,0x5,EC: EC+CLKO{RA6}, USB-EC CONFIG1H~1~10=0xf,0x4,EC: EC+RA6, USB-EC CONFIG1H~1~11=0xe,0x2,XT: XT+PLL, USB-XT CONFIG1H~1~12=0xe,0x0,XT: USB-XT CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~4=VREGEN,0x20,USB Voltage Regulator CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x8,4.2V CONFIG2L~3~4=0x18,0x0,4.5V CONFIG2L~4~1=0x20,0x20,Enabled CONFIG2L~4~2=0x20,0x0,Disabled CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1e,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1e,0x1e,1:32768 CONFIG2H~2~2=0x1e,0x1c,1:16384 CONFIG2H~2~3=0x1e,0x1a,1:8192 CONFIG2H~2~4=0x1e,0x18,1:4096 CONFIG2H~2~5=0x1e,0x16,1:2048 CONFIG2H~2~6=0x1e,0x14,1:1024 CONFIG2H~2~7=0x1e,0x12,1:512 CONFIG2H~2~8=0x1e,0x10,1:256 CONFIG2H~2~9=0x1e,0xe,1:128 CONFIG2H~2~10=0x1e,0xc,1:64 CONFIG2H~2~11=0x1e,0xa,1:32 CONFIG2H~2~12=0x1e,0x8,1:16 CONFIG2H~2~13=0x1e,0x6,1:8 CONFIG2H~2~14=0x1e,0x4,1:4 CONFIG2H~2~15=0x1e,0x2,1:2 CONFIG2H~2~16=0x1e,0x0,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=PBADEN,0x2,PortB A/D Enable CONFIG3H~3=LPT1OSC,0x4,Low Power Timer1 Osc enable CONFIG3H~4=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RB3 CONFIG3H~2~1=0x2,0x2,PORTB<4:0> configured as analog inputs on RESET CONFIG3H~2~2=0x2,0x0,PORTB<4:0> configured as digital I/O on RESET CONFIG3H~3~1=0x4,0x4,Enabled CONFIG3H~3~2=0x4,0x0,Disabled CONFIG3H~4~1=0x80,0x80,MCLR Enabled,RE3 Disabled CONFIG3H~4~2=0x80,0x0,MCLR Disabled,RE3 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=ENICPORT,0x20,Dedicated In-Circuit Port {ICD/ICSP} CONFIG4L~4=XINST,0x40,Extended Instruction Set Enable bit CONFIG4L~5=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x20,0x20,Enabled CONFIG4L~3~2=0x20,0x0,Disabled CONFIG4L~4~1=0x40,0x40,Enabled CONFIG4L~4~2=0x40,0x0,Disabled CONFIG4L~5~1=0x80,0x80,Disabled CONFIG4L~5~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-01FFF CONFIG5L~2=CP_1,0x2,Code Protect 02000-03FFF CONFIG5L~3=CP_2,0x4,Code Protect 04000-05FFF CONFIG5L~4=CP_3,0x8,Code Protect 06000-07FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x0,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x0,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x0,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x0,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPB,0x40,Code Protect Boot CONFIG5H~2=CPD,0x80,Data EE Read Protect CONFIG5H~1~1=0x40,0x40,Disabled CONFIG5H~1~2=0x40,0x0,Enabled CONFIG5H~2~1=0x80,0x80,Disabled CONFIG5H~2~2=0x80,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-01FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 02000-03FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 04000-05FFF CONFIG6L~4=WRT_3,0x8,Table Write Protect 06000-07FFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x0,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x0,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x0,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x0,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTC,0x20,Config. Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTD,0x80,Data EE Write Protect CONFIG6H~1~1=0x20,0x20,Disabled CONFIG6H~1~2=0x20,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x80,0x80,Disabled CONFIG6H~3~2=0x80,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-01FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 02000-03FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 04000-05FFF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 06000-07FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x0,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x0,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x0,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x0,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE_24xx05 prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F45J11] pgmmem=0x0 ~pgmmem=0x7ff7 cfgmem=0x7ff8 ~cfgmem=0x7fff userid= ~userid= eedata= ~eedata= devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0x4e00 configslots=8 0x7ff8=CONFIG1L 0x7ff9=CONFIG1H 0x7ffa=CONFIG2L 0x7ffb=CONFIG2H 0x7ffc=CONFIG3L 0x7ffd=CONFIG3H 0x7ffe=CONFIG4L 0x7fff=CONFIG4H CONFIG1L_unused=0x0 CONFIG1L~1=WDTEN,0x1,Watchdog Timer CONFIG1L~2=STVREN,0x20,Stack Overflow/Underflow Reset CONFIG1L~3=XINST,0x40,Extended Instruction Set CONFIG1L~4=DEBUG,0x80,Background Debug CONFIG1L~1~1=0x1,0x1,Enabled CONFIG1L~1~2=0x1,0x0,Disabled CONFIG1L~2~1=0x20,0x20,Enabled CONFIG1L~2~2=0x20,0x0,Disabled CONFIG1L~3~1=0x40,0x40,Enabled CONFIG1L~3~2=0x40,0x0,Disabled CONFIG1L~4~1=0x80,0x80,Disabled CONFIG1L~4~2=0x80,0x0,Enabled CONFIG1H_unused=0x0 CONFIG1H~1=CP0,0x4,Code Protect CONFIG1H~2=SIGN,0x8,Config Word Signature Bit CONFIG1H~3=RESERVED,0xf0,RESERVED CONFIG1H~1~1=0x4,0x4,Disabled CONFIG1H~1~2=0x4,0x0,Enabled CONFIG1H~2~1=0x8,0x8,Bulk erase of memory not conducated CONFIG1H~2~2=0x8,0x0,Bulk erase of memory area complete CONFIG1H~3~1=0xf0,0xf0,RESERVED CONFIG2L_unused=0x0 CONFIG2L~1=OSC,0x7,Oscillator CONFIG2L~2=T1DIG,0x8,T1OSCEN Enforcement CONFIG2L~3=LPT1OSC,0x10,Low-Power Timer1 Oscillator CONFIG2L~4=FCMEN,0x40,Fail-Safe Clock Monitor CONFIG2L~5=IESO,0x80,Internal External Oscillator Switch Over Mode CONFIG2L~1~1=0x7,0x7,EC+PLL (CLKO-RA6) CONFIG2L~1~2=0x7,0x6,EC (CLKO-RA6) CONFIG2L~1~3=0x7,0x5,HS+PLL CONFIG2L~1~4=0x7,0x4,HS CONFIG2L~1~5=0x7,0x3,INTOSCPLLO (CLKO-RA6) CONFIG2L~1~6=0x7,0x2,INTOSCPLL CONFIG2L~1~7=0x7,0x1,INTOSCO (CLKO-RA6) CONFIG2L~1~8=0x7,0x0,INTOSC CONFIG2L~2~1=0x8,0x8,Enabled CONFIG2L~2~2=0x8,0x0,Disabled CONFIG2L~3~1=0x10,0x10,Disabled CONFIG2L~3~2=0x10,0x0,Enabled CONFIG2L~4~1=0x40,0x0,Disabled CONFIG2L~4~2=0x40,0x40,Enabled CONFIG2L~5~1=0x80,0x0,Disabled CONFIG2L~5~2=0x80,0x80,Enabled CONFIG2H_unused=0x0 CONFIG2H~1=WDTPS,0xf,Watchdog Postscaler CONFIG2H~2=RESERVED,0xf0,RESERVED CONFIG2H~1~1=0xf,0xf,1:32768 CONFIG2H~1~2=0xf,0xe,1:16384 CONFIG2H~1~3=0xf,0xd,1:8192 CONFIG2H~1~4=0xf,0xc,1:4096 CONFIG2H~1~5=0xf,0xb,1:2048 CONFIG2H~1~6=0xf,0xa,1:1024 CONFIG2H~1~7=0xf,0x9,1:512 CONFIG2H~1~8=0xf,0x8,1:256 CONFIG2H~1~9=0xf,0x7,1:128 CONFIG2H~1~10=0xf,0x6,1:64 CONFIG2H~1~11=0xf,0x5,1:32 CONFIG2H~1~12=0xf,0x4,1:16 CONFIG2H~1~13=0xf,0x3,1:8 CONFIG2H~1~14=0xf,0x2,1:4 CONFIG2H~1~15=0xf,0x1,1:2 CONFIG2H~1~16=0xf,0x0,1:1 CONFIG2H~2~1=0xf0,0xf0,RESERVED CONFIG3L_unused=0x0 CONFIG3L~1=DSWDTOSC,0x1,DSWDT Clock Select CONFIG3L~2=RTCOSC,0x2,RTCC Clock Select CONFIG3L~3=DSBOREN,0x4,Deep Sleep BOR CONFIG3L~4=DSWDTEN,0x8,Deep Sleep Watchdog Timer CONFIG3L~5=DSWDTPS,0xf0,Deep Sleep Watchdog Postscaler CONFIG3L~1~1=0x1,0x1,DSWDT uses INTRC CONFIG3L~1~2=0x1,0x0,DSWDT uses T1OSC/T1CKI CONFIG3L~2~1=0x2,0x2,RTCC uses T1OSC/T1CKI CONFIG3L~2~2=0x2,0x0,RTCC uses INTRC CONFIG3L~3~1=0x4,0x4,Enabled CONFIG3L~3~2=0x4,0x0,Disabled CONFIG3L~4~1=0x8,0x8,Enabled CONFIG3L~4~2=0x8,0x0,Disabled CONFIG3L~5~1=0xf0,0xf0,1:2,147,483,648 (25.7 days) CONFIG3L~5~2=0xf0,0xe0,1:536,870,912 (6.4 days) CONFIG3L~5~3=0xf0,0xd0,1:134,217,728 (38.5 hours) CONFIG3L~5~4=0xf0,0xc0,1:33,554,432 (9.6 hours) CONFIG3L~5~5=0xf0,0xb0,1:8,388,608 (2.4 hours) CONFIG3L~5~6=0xf0,0xa0,1:2,097,152 (36 minutes) CONFIG3L~5~7=0xf0,0x90,1:524,288 (9 minutes) CONFIG3L~5~8=0xf0,0x80,1:131,072 (135 seconds) CONFIG3L~5~9=0xf0,0x70,1:32,768 (34 seconds) CONFIG3L~5~10=0xf0,0x60,1:8,192 (8.5 seconds) CONFIG3L~5~11=0xf0,0x50,1:2,048 (2.1 seconds) CONFIG3L~5~12=0xf0,0x40,1:512 (528 ms) CONFIG3L~5~13=0xf0,0x30,1:128 (132 ms) CONFIG3L~5~14=0xf0,0x20,1:32 (33 ms) CONFIG3L~5~15=0xf0,0x10,1:8 (8.3 ms) CONFIG3L~5~16=0xf0,0x0,1:2 (2.1 ms) CONFIG3H_unused=0x0 CONFIG3H~1=IOL1WAY,0x1,IOLOCK One-Way Set Enable bit CONFIG3H~2=MSSP7B_EN,0x8,MSSP address masking CONFIG3H~3=RESERVED,0xf0,RESERVED CONFIG3H~1~1=0x1,0x1,Enabled CONFIG3H~1~2=0x1,0x0,Disabled CONFIG3H~2~1=0x8,0x8,7 Bit address masking mode CONFIG3H~2~2=0x8,0x0,5 Bit address masking mode CONFIG3H~3~1=0xf0,0xf0,RESERVED CONFIG4L_unused=0x0 CONFIG4L~1=WPFP,0x1f,Write/Erase Protect Page Start/End Location CONFIG4L~2=WPEND,0x40,Write/Erase Protect Region Select bit (valid when WPDIS = 0) CONFIG4L~3=WPCFG,0x80,Write/Erase Protect Configuration Region CONFIG4L~1~1=0x1f,0x0,Write Protect Program Flash Page 0 CONFIG4L~1~2=0x1f,0x1,Write Protect Program Flash Page 1 CONFIG4L~1~3=0x1f,0x2,Write Protect Program Flash Page 2 CONFIG4L~1~4=0x1f,0x3,Write Protect Program Flash Page 3 CONFIG4L~1~5=0x1f,0x4,Write Protect Program Flash Page 4 CONFIG4L~1~6=0x1f,0x5,Write Protect Program Flash Page 5 CONFIG4L~1~7=0x1f,0x6,Write Protect Program Flash Page 6 CONFIG4L~1~8=0x1f,0x7,Write Protect Program Flash Page 7 CONFIG4L~1~9=0x1f,0x8,Write Protect Program Flash Page 8 CONFIG4L~1~10=0x1f,0x9,Write Protect Program Flash Page 9 CONFIG4L~1~11=0x1f,0xa,Write Protect Program Flash Page 10 CONFIG4L~1~12=0x1f,0xb,Write Protect Program Flash Page 11 CONFIG4L~1~13=0x1f,0xc,Write Protect Program Flash Page 12 CONFIG4L~1~14=0x1f,0xd,Write Protect Program Flash Page 13 CONFIG4L~1~15=0x1f,0xe,Write Protect Program Flash Page 14 CONFIG4L~1~16=0x1f,0xf,Write Protect Program Flash Page 15 CONFIG4L~1~17=0x1f,0x10,Write Protect Program Flash Page 16 CONFIG4L~1~18=0x1f,0x11,Write Protect Program Flash Page 17 CONFIG4L~1~19=0x1f,0x12,Write Protect Program Flash Page 18 CONFIG4L~1~20=0x1f,0x13,Write Protect Program Flash Page 19 CONFIG4L~1~21=0x1f,0x14,Write Protect Program Flash Page 20 CONFIG4L~1~22=0x1f,0x15,Write Protect Program Flash Page 21 CONFIG4L~1~23=0x1f,0x16,Write Protect Program Flash Page 22 CONFIG4L~1~24=0x1f,0x17,Write Protect Program Flash Page 23 CONFIG4L~1~25=0x1f,0x18,Write Protect Program Flash Page 24 CONFIG4L~1~26=0x1f,0x19,Write Protect Program Flash Page 25 CONFIG4L~1~27=0x1f,0x1a,Write Protect Program Flash Page 26 CONFIG4L~1~28=0x1f,0x1b,Write Protect Program Flash Page 27 CONFIG4L~1~29=0x1f,0x1c,Write Protect Program Flash Page 28 CONFIG4L~1~30=0x1f,0x1d,Write Protect Program Flash Page 29 CONFIG4L~1~31=0x1f,0x1e,Write Protect Program Flash Page 30 CONFIG4L~1~32=0x1f,0x1f,Write Protect Program Flash Page 31 CONFIG4L~2~1=0x40,0x40,Pages WPFP<5:0> to (Configuration Words page) write/erase protected CONFIG4L~2~2=0x40,0x0,Page 0 to WPFP<5:0> erase/write-protected CONFIG4L~3~1=0x80,0x80,Disabled CONFIG4L~3~2=0x80,0x0,Enabled CONFIG4H_unused=0x0 CONFIG4H~1=WPDIS,0x1,Write Protect Disable bit CONFIG4H~2=RESERVED,0xf0,RESERVED CONFIG4H~1~1=0x1,0x1,Disabled CONFIG4H~1~2=0x1,0x0,Enabled CONFIG4H~2~1=0xf0,0xf0,RESERVED erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F45J50] pgmmem=0x0 ~pgmmem=0x7ff7 cfgmem=0x7ff8 ~cfgmem=0x7fff userid= ~userid= eedata= ~eedata= devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0x4c80 configslots=8 0x7ff8=CONFIG1L 0x7ff9=CONFIG1H 0x7ffa=CONFIG2L 0x7ffb=CONFIG2H 0x7ffc=CONFIG3L 0x7ffd=CONFIG3H 0x7ffe=CONFIG4L 0x7fff=CONFIG4H CONFIG1L_unused=0x0 CONFIG1L~1=WDTEN,0x1,Watchdog Timer CONFIG1L~2=PLLDIV,0xe,PLL Prescaler Selection bits CONFIG1L~3=STVREN,0x20,Stack Overflow/Underflow Reset CONFIG1L~4=XINST,0x40,Extended Instruction Set CONFIG1L~5=DEBUG,0x80,Background Debug CONFIG1L~1~1=0x1,0x1,Enabled CONFIG1L~1~2=0x1,0x0,Disabled CONFIG1L~2~1=0xe,0xe,No prescale (4 MHz oscillator input drives PLL directly) CONFIG1L~2~2=0xe,0xc,Divide by 2 (8 MHz oscillator input) CONFIG1L~2~3=0xe,0xa,Divide by 3 (12 MHz oscillator input) CONFIG1L~2~4=0xe,0x8,Divide by 4 (16 MHz oscillator input) CONFIG1L~2~5=0xe,0x6,Divide by 5 (20 MHz oscillator input) CONFIG1L~2~6=0xe,0x4,Divide by 6 (24 MHz oscillator input) CONFIG1L~2~7=0xe,0x2,Divide by 10 (40 MHz oscillator input) CONFIG1L~2~8=0xe,0x0,Divide by 12 (48 MHz oscillator input) CONFIG1L~3~1=0x20,0x20,Enabled CONFIG1L~3~2=0x20,0x0,Disabled CONFIG1L~4~1=0x40,0x40,Enabled CONFIG1L~4~2=0x40,0x0,Disabled CONFIG1L~5~1=0x80,0x80,Disabled CONFIG1L~5~2=0x80,0x0,Enabled CONFIG1H_unused=0x0 CONFIG1H~1=CPUDIV,0x3,CPU System Clock Postscaler CONFIG1H~2=CP0,0x4,Code Protect CONFIG1H~3=SIGN,0x8,Config Word Signature Bit CONFIG1H~4=RESERVED,0xf0,RESERVED CONFIG1H~1~1=0x3,0x3,No CPU system clock divide CONFIG1H~1~2=0x3,0x2,CPU system clock divide by 2 CONFIG1H~1~3=0x3,0x1,CPU system clock divide by 3 CONFIG1H~1~4=0x3,0x0,CPU system clock divide by 6 CONFIG1H~2~1=0x4,0x4,Disabled CONFIG1H~2~2=0x4,0x0,Enabled CONFIG1H~3~1=0x8,0x8,Bulk erase of memory not conducated CONFIG1H~3~2=0x8,0x0,Bulk erase of memory area complete CONFIG1H~4~1=0xf0,0xf0,RESERVED CONFIG2L_unused=0x0 CONFIG2L~1=OSC,0x7,Oscillator CONFIG2L~2=T1DIG,0x8,T1OSCEN Enforcement CONFIG2L~3=LPT1OSC,0x10,Low-Power Timer1 Oscillator CONFIG2L~4=FCMEN,0x40,Fail-Safe Clock Monitor CONFIG2L~5=IESO,0x80,Internal External Oscillator Switch Over Mode CONFIG2L~1~1=0x7,0x7,EC+PLL (CLKO-RA6), USB-EC+PLL CONFIG2L~1~2=0x7,0x6,EC (CLKO-RA6), USB-EC CONFIG2L~1~3=0x7,0x5,HS+PLL, USB-HS+PLL CONFIG2L~1~4=0x7,0x4,HS, USB-HS CONFIG2L~1~5=0x7,0x3,INTOSCPLLO (CLKO-RA6) CONFIG2L~1~6=0x7,0x2,INTOSCPLL CONFIG2L~1~7=0x7,0x1,INTOSCO (CLKO-RA6) CONFIG2L~1~8=0x7,0x0,INTOSC CONFIG2L~2~1=0x8,0x8,Enabled CONFIG2L~2~2=0x8,0x0,Disabled CONFIG2L~3~1=0x10,0x10,Disabled CONFIG2L~3~2=0x10,0x0,Enabled CONFIG2L~4~1=0x40,0x0,Disabled CONFIG2L~4~2=0x40,0x40,Enabled CONFIG2L~5~1=0x80,0x0,Disabled CONFIG2L~5~2=0x80,0x80,Enabled CONFIG2H_unused=0x0 CONFIG2H~1=WDTPS,0xf,Watchdog Postscaler CONFIG2H~2=RESERVED,0xf0,RESERVED CONFIG2H~1~1=0xf,0xf,1:32768 CONFIG2H~1~2=0xf,0xe,1:16384 CONFIG2H~1~3=0xf,0xd,1:8192 CONFIG2H~1~4=0xf,0xc,1:4096 CONFIG2H~1~5=0xf,0xb,1:2048 CONFIG2H~1~6=0xf,0xa,1:1024 CONFIG2H~1~7=0xf,0x9,1:512 CONFIG2H~1~8=0xf,0x8,1:256 CONFIG2H~1~9=0xf,0x7,1:128 CONFIG2H~1~10=0xf,0x6,1:64 CONFIG2H~1~11=0xf,0x5,1:32 CONFIG2H~1~12=0xf,0x4,1:16 CONFIG2H~1~13=0xf,0x3,1:8 CONFIG2H~1~14=0xf,0x2,1:4 CONFIG2H~1~15=0xf,0x1,1:2 CONFIG2H~1~16=0xf,0x0,1:1 CONFIG2H~2~1=0xf0,0xf0,RESERVED CONFIG3L_unused=0x0 CONFIG3L~1=DSWDTOSC,0x1,DSWDT Clock Select CONFIG3L~2=RTCOSC,0x2,RTCC Clock Select CONFIG3L~3=DSBOREN,0x4,Deep Sleep BOR CONFIG3L~4=DSWDTEN,0x8,Deep Sleep Watchdog Timer CONFIG3L~5=DSWDTPS,0xf0,Deep Sleep Watchdog Postscaler CONFIG3L~1~1=0x1,0x1,DSWDT uses INTRC CONFIG3L~1~2=0x1,0x0,DSWDT uses T1OSC/T1CKI CONFIG3L~2~1=0x2,0x2,RTCC uses T1OSC/T1CKI CONFIG3L~2~2=0x2,0x0,RTCC uses INTRC CONFIG3L~3~1=0x4,0x4,Enabled CONFIG3L~3~2=0x4,0x0,Disabled CONFIG3L~4~1=0x8,0x8,Enabled CONFIG3L~4~2=0x8,0x0,Disabled CONFIG3L~5~1=0xf0,0xf0,1:2,147,483,648 (25.7 days) CONFIG3L~5~2=0xf0,0xe0,1:536,870,912 (6.4 days) CONFIG3L~5~3=0xf0,0xd0,1:134,217,728 (38.5 hours) CONFIG3L~5~4=0xf0,0xc0,1:33,554,432 (9.6 hours) CONFIG3L~5~5=0xf0,0xb0,1:8,388,608 (2.4 hours) CONFIG3L~5~6=0xf0,0xa0,1:2,097,152 (36 minutes) CONFIG3L~5~7=0xf0,0x90,1:524,288 (9 minutes) CONFIG3L~5~8=0xf0,0x80,1:131,072 (135 seconds) CONFIG3L~5~9=0xf0,0x70,1:32,768 (34 seconds) CONFIG3L~5~10=0xf0,0x60,1:8,192 (8.5 seconds) CONFIG3L~5~11=0xf0,0x50,1:2,048 (2.1 seconds) CONFIG3L~5~12=0xf0,0x40,1:512 (528 ms) CONFIG3L~5~13=0xf0,0x30,1:128 (132 ms) CONFIG3L~5~14=0xf0,0x20,1:32 (33 ms) CONFIG3L~5~15=0xf0,0x10,1:8 (8.3 ms) CONFIG3L~5~16=0xf0,0x0,1:2 (2.1 ms) CONFIG3H_unused=0x0 CONFIG3H~1=IOL1WAY,0x1,IOLOCK One-Way Set Enable bit CONFIG3H~2=MSSP7B_EN,0x8,MSSP address masking CONFIG3H~3=RESERVED,0xf0,RESERVED CONFIG3H~1~1=0x1,0x1,Enabled CONFIG3H~1~2=0x1,0x0,Disabled CONFIG3H~2~1=0x8,0x8,7 Bit address masking mode CONFIG3H~2~2=0x8,0x0,5 Bit address masking mode CONFIG3H~3~1=0xf0,0xf0,RESERVED CONFIG4L_unused=0x0 CONFIG4L~1=WPFP,0x1f,Write/Erase Protect Page Start/End Location CONFIG4L~2=WPEND,0x40,Write/Erase Protect Region Select bit (valid when WPDIS = 0) CONFIG4L~3=WPCFG,0x80,Write/Erase Protect Configuration Region CONFIG4L~1~1=0x1f,0x0,Write Protect Program Flash Page 0 CONFIG4L~1~2=0x1f,0x1,Write Protect Program Flash Page 1 CONFIG4L~1~3=0x1f,0x2,Write Protect Program Flash Page 2 CONFIG4L~1~4=0x1f,0x3,Write Protect Program Flash Page 3 CONFIG4L~1~5=0x1f,0x4,Write Protect Program Flash Page 4 CONFIG4L~1~6=0x1f,0x5,Write Protect Program Flash Page 5 CONFIG4L~1~7=0x1f,0x6,Write Protect Program Flash Page 6 CONFIG4L~1~8=0x1f,0x7,Write Protect Program Flash Page 7 CONFIG4L~1~9=0x1f,0x8,Write Protect Program Flash Page 8 CONFIG4L~1~10=0x1f,0x9,Write Protect Program Flash Page 9 CONFIG4L~1~11=0x1f,0xa,Write Protect Program Flash Page 10 CONFIG4L~1~12=0x1f,0xb,Write Protect Program Flash Page 11 CONFIG4L~1~13=0x1f,0xc,Write Protect Program Flash Page 12 CONFIG4L~1~14=0x1f,0xd,Write Protect Program Flash Page 13 CONFIG4L~1~15=0x1f,0xe,Write Protect Program Flash Page 14 CONFIG4L~1~16=0x1f,0xf,Write Protect Program Flash Page 15 CONFIG4L~1~17=0x1f,0x10,Write Protect Program Flash Page 16 CONFIG4L~1~18=0x1f,0x11,Write Protect Program Flash Page 17 CONFIG4L~1~19=0x1f,0x12,Write Protect Program Flash Page 18 CONFIG4L~1~20=0x1f,0x13,Write Protect Program Flash Page 19 CONFIG4L~1~21=0x1f,0x14,Write Protect Program Flash Page 20 CONFIG4L~1~22=0x1f,0x15,Write Protect Program Flash Page 21 CONFIG4L~1~23=0x1f,0x16,Write Protect Program Flash Page 22 CONFIG4L~1~24=0x1f,0x17,Write Protect Program Flash Page 23 CONFIG4L~1~25=0x1f,0x18,Write Protect Program Flash Page 24 CONFIG4L~1~26=0x1f,0x19,Write Protect Program Flash Page 25 CONFIG4L~1~27=0x1f,0x1a,Write Protect Program Flash Page 26 CONFIG4L~1~28=0x1f,0x1b,Write Protect Program Flash Page 27 CONFIG4L~1~29=0x1f,0x1c,Write Protect Program Flash Page 28 CONFIG4L~1~30=0x1f,0x1d,Write Protect Program Flash Page 29 CONFIG4L~1~31=0x1f,0x1e,Write Protect Program Flash Page 30 CONFIG4L~1~32=0x1f,0x1f,Write Protect Program Flash Page 31 CONFIG4L~2~1=0x40,0x40,Pages WPFP<5:0> to (Configuration Words page) write/erase protected CONFIG4L~2~2=0x40,0x0,Page 0 to WPFP<5:0> erase/write-protected CONFIG4L~3~1=0x80,0x80,Disabled CONFIG4L~3~2=0x80,0x0,Enabled CONFIG4H_unused=0x0 CONFIG4H~1=WPDIS,0x1,Write Protect Disable bit CONFIG4H~2=RESERVED,0xf0,RESERVED CONFIG4H~1~1=0x1,0x1,Disabled CONFIG4H~1~2=0x1,0x0,Enabled CONFIG4H~2~1=0xf0,0xf0,RESERVED erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F4681] pgmmem=0x0 ~pgmmem=0xFFFF cfgmem=0x300000 ~cfgmem=0x30000D userid=0x200000 ~userid=0x200007 eedata= ~eedata= devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x0E00 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000a= 0x30000b= 0x30000c= 0x30000d= CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xF,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xC,0xC,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xA,0xA,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xF,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xF,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xF,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xF,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xF,0x5,EC-Port on RA6 CONFIG1H~1~8=0xF,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xF,0x3,EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xF,0x2,HS CONFIG1H~1~11=0xF,0x1,XT CONFIG1H~1~12=0xF,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x08,4.2V CONFIG2L~3~4=0x18,0x00,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1E,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1E,0x1E,1:32768 CONFIG2H~2~2=0x1E,0x1C,1:16384 CONFIG2H~2~3=0x1E,0x1A,1:8192 CONFIG2H~2~4=0x1E,0x18,1:4096 CONFIG2H~2~5=0x1E,0x16,1:2048 CONFIG2H~2~6=0x1E,0x14,1:1024 CONFIG2H~2~7=0x1E,0x12,1:512 CONFIG2H~2~8=0x1E,0x10,1:256 CONFIG2H~2~9=0x1E,0x0E,1:128 CONFIG2H~2~10=0x1E,0x0C,1:64 CONFIG2H~2~11=0x1E,0x0A,1:32 CONFIG2H~2~12=0x1E,0x08,1:16 CONFIG2H~2~13=0x1E,0x06,1:8 CONFIG2H~2~14=0x1E,0x04,1:4 CONFIG2H~2~15=0x1E,0x02,1:2 CONFIG2H~2~16=0x1E,0x00,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=PBADEN,0x2,PortB A/D Enable CONFIG3H~2=LPT1OSC,0x04,Low Power Timer1 Osc enable CONFIG3H~3=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x2,0x2,PORTB<4> and <1:0> configured as analog inputs on RESET CONFIG3H~1~2=0x2,0x0,PORTB<4> and <1:0> configured as digital I/O on RESET CONFIG3H~2~1=0x04,0x04,Enabled CONFIG3H~2~2=0x04,0x00,Disabled CONFIG3H~3~1=0x80,0x80,MCLR Enabled,RE3 Disabled CONFIG3H~3~2=0x80,0x00,MCLR Disabled, RE3 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=ENHCPU,0x40,Extended CPU Enable CONFIG4L~4=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x40,0x40,Enabled CONFIG4L~3~2=0x40,0x00,Disabled CONFIG4L~4~1=0x80,0x80,Disabled CONFIG4L~4~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-03FFF CONFIG5L~2=CP_1,0x2,Code Protect 04000-07FFF CONFIG5L~3=CP_2,0x4,Code Protect 08000-0BFFF CONFIG5L~4=CP_3,0x8,Code Protect 0C000-0FFFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x00,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x00,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x00,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x00,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPD,0x80,Data EE Read Protect CONFIG5H~2=CPB,0x40,Code Protect Boot CONFIG5H~1~1=0x80,0x80,Disabled CONFIG5H~1~2=0x80,0x0,Enabled CONFIG5H~2~1=0x40,0x40,Disabled CONFIG5H~2~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F46J11] pgmmem=0x0 ~pgmmem=0xfff7 cfgmem=0xfff8 ~cfgmem=0xffff userid= ~userid= eedata= ~eedata= devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0x4e20 configslots=8 0xfff8=CONFIG1L 0xfff9=CONFIG1H 0xfffa=CONFIG2L 0xfffb=CONFIG2H 0xfffc=CONFIG3L 0xfffd=CONFIG3H 0xfffe=CONFIG4L 0xffff=CONFIG4H CONFIG1L_unused=0x0 CONFIG1L~1=WDTEN,0x1,Watchdog Timer CONFIG1L~2=STVREN,0x20,Stack Overflow/Underflow Reset CONFIG1L~3=XINST,0x40,Extended Instruction Set CONFIG1L~4=DEBUG,0x80,Background Debug CONFIG1L~1~1=0x1,0x1,Enabled CONFIG1L~1~2=0x1,0x0,Disabled CONFIG1L~2~1=0x20,0x20,Enabled CONFIG1L~2~2=0x20,0x0,Disabled CONFIG1L~3~1=0x40,0x40,Enabled CONFIG1L~3~2=0x40,0x0,Disabled CONFIG1L~4~1=0x80,0x80,Disabled CONFIG1L~4~2=0x80,0x0,Enabled CONFIG1H_unused=0x0 CONFIG1H~1=CP0,0x4,Code Protect CONFIG1H~2=SIGN,0x8,Config Word Signature Bit CONFIG1H~3=RESERVED,0xf0,RESERVED CONFIG1H~1~1=0x4,0x4,Disabled CONFIG1H~1~2=0x4,0x0,Enabled CONFIG1H~2~1=0x8,0x8,Bulk erase of memory not conducated CONFIG1H~2~2=0x8,0x0,Bulk erase of memory area complete CONFIG1H~3~1=0xf0,0xf0,RESERVED CONFIG2L_unused=0x0 CONFIG2L~1=OSC,0x7,Oscillator CONFIG2L~2=T1DIG,0x8,T1OSCEN Enforcement CONFIG2L~3=LPT1OSC,0x10,Low-Power Timer1 Oscillator CONFIG2L~4=FCMEN,0x40,Fail-Safe Clock Monitor CONFIG2L~5=IESO,0x80,Internal External Oscillator Switch Over Mode CONFIG2L~1~1=0x7,0x7,EC+PLL (CLKO-RA6) CONFIG2L~1~2=0x7,0x6,EC (CLKO-RA6) CONFIG2L~1~3=0x7,0x5,HS+PLL CONFIG2L~1~4=0x7,0x4,HS CONFIG2L~1~5=0x7,0x3,INTOSCPLLO (CLKO-RA6) CONFIG2L~1~6=0x7,0x2,INTOSCPLL CONFIG2L~1~7=0x7,0x1,INTOSCO (CLKO-RA6) CONFIG2L~1~8=0x7,0x0,INTOSC CONFIG2L~2~1=0x8,0x8,Enabled CONFIG2L~2~2=0x8,0x0,Disabled CONFIG2L~3~1=0x10,0x10,Disabled CONFIG2L~3~2=0x10,0x0,Enabled CONFIG2L~4~1=0x40,0x0,Disabled CONFIG2L~4~2=0x40,0x40,Enabled CONFIG2L~5~1=0x80,0x0,Disabled CONFIG2L~5~2=0x80,0x80,Enabled CONFIG2H_unused=0x0 CONFIG2H~1=WDTPS,0xf,Watchdog Postscaler CONFIG2H~2=RESERVED,0xf0,RESERVED CONFIG2H~1~1=0xf,0xf,1:32768 CONFIG2H~1~2=0xf,0xe,1:16384 CONFIG2H~1~3=0xf,0xd,1:8192 CONFIG2H~1~4=0xf,0xc,1:4096 CONFIG2H~1~5=0xf,0xb,1:2048 CONFIG2H~1~6=0xf,0xa,1:1024 CONFIG2H~1~7=0xf,0x9,1:512 CONFIG2H~1~8=0xf,0x8,1:256 CONFIG2H~1~9=0xf,0x7,1:128 CONFIG2H~1~10=0xf,0x6,1:64 CONFIG2H~1~11=0xf,0x5,1:32 CONFIG2H~1~12=0xf,0x4,1:16 CONFIG2H~1~13=0xf,0x3,1:8 CONFIG2H~1~14=0xf,0x2,1:4 CONFIG2H~1~15=0xf,0x1,1:2 CONFIG2H~1~16=0xf,0x0,1:1 CONFIG2H~2~1=0xf0,0xf0,RESERVED CONFIG3L_unused=0x0 CONFIG3L~1=DSWDTOSC,0x1,DSWDT Clock Select CONFIG3L~2=RTCOSC,0x2,RTCC Clock Select CONFIG3L~3=DSBOREN,0x4,Deep Sleep BOR CONFIG3L~4=DSWDTEN,0x8,Deep Sleep Watchdog Timer CONFIG3L~5=DSWDTPS,0xf0,Deep Sleep Watchdog Postscaler CONFIG3L~1~1=0x1,0x1,DSWDT uses INTRC CONFIG3L~1~2=0x1,0x0,DSWDT uses T1OSC/T1CKI CONFIG3L~2~1=0x2,0x2,RTCC uses T1OSC/T1CKI CONFIG3L~2~2=0x2,0x0,RTCC uses INTRC CONFIG3L~3~1=0x4,0x4,Enabled CONFIG3L~3~2=0x4,0x0,Disabled CONFIG3L~4~1=0x8,0x8,Enabled CONFIG3L~4~2=0x8,0x0,Disabled CONFIG3L~5~1=0xf0,0xf0,1:2,147,483,648 (25.7 days) CONFIG3L~5~2=0xf0,0xe0,1:536,870,912 (6.4 days) CONFIG3L~5~3=0xf0,0xd0,1:134,217,728 (38.5 hours) CONFIG3L~5~4=0xf0,0xc0,1:33,554,432 (9.6 hours) CONFIG3L~5~5=0xf0,0xb0,1:8,388,608 (2.4 hours) CONFIG3L~5~6=0xf0,0xa0,1:2,097,152 (36 minutes) CONFIG3L~5~7=0xf0,0x90,1:524,288 (9 minutes) CONFIG3L~5~8=0xf0,0x80,1:131,072 (135 seconds) CONFIG3L~5~9=0xf0,0x70,1:32,768 (34 seconds) CONFIG3L~5~10=0xf0,0x60,1:8,192 (8.5 seconds) CONFIG3L~5~11=0xf0,0x50,1:2,048 (2.1 seconds) CONFIG3L~5~12=0xf0,0x40,1:512 (528 ms) CONFIG3L~5~13=0xf0,0x30,1:128 (132 ms) CONFIG3L~5~14=0xf0,0x20,1:32 (33 ms) CONFIG3L~5~15=0xf0,0x10,1:8 (8.3 ms) CONFIG3L~5~16=0xf0,0x0,1:2 (2.1 ms) CONFIG3H_unused=0x0 CONFIG3H~1=IOL1WAY,0x1,IOLOCK One-Way Set Enable bit CONFIG3H~2=MSSP7B_EN,0x8,MSSP address masking CONFIG3H~3=RESERVED,0xf0,RESERVED CONFIG3H~1~1=0x1,0x1,Enabled CONFIG3H~1~2=0x1,0x0,Disabled CONFIG3H~2~1=0x8,0x8,7 Bit address masking mode CONFIG3H~2~2=0x8,0x0,5 Bit address masking mode CONFIG3H~3~1=0xf0,0xf0,RESERVED CONFIG4L_unused=0x0 CONFIG4L~1=WPFP,0x3f,Write/Erase Protect Page Start/End Location CONFIG4L~2=WPEND,0x40,Write/Erase Protect Region Select bit (valid when WPDIS = 0) CONFIG4L~3=WPCFG,0x80,Write/Erase Protect Configuration Region CONFIG4L~1~1=0x3f,0x0,Write Protect Program Flash Page 0 CONFIG4L~1~2=0x3f,0x1,Write Protect Program Flash Page 1 CONFIG4L~1~3=0x3f,0x2,Write Protect Program Flash Page 2 CONFIG4L~1~4=0x3f,0x3,Write Protect Program Flash Page 3 CONFIG4L~1~5=0x3f,0x4,Write Protect Program Flash Page 4 CONFIG4L~1~6=0x3f,0x5,Write Protect Program Flash Page 5 CONFIG4L~1~7=0x3f,0x6,Write Protect Program Flash Page 6 CONFIG4L~1~8=0x3f,0x7,Write Protect Program Flash Page 7 CONFIG4L~1~9=0x3f,0x8,Write Protect Program Flash Page 8 CONFIG4L~1~10=0x3f,0x9,Write Protect Program Flash Page 9 CONFIG4L~1~11=0x3f,0xa,Write Protect Program Flash Page 10 CONFIG4L~1~12=0x3f,0xb,Write Protect Program Flash Page 11 CONFIG4L~1~13=0x3f,0xc,Write Protect Program Flash Page 12 CONFIG4L~1~14=0x3f,0xd,Write Protect Program Flash Page 13 CONFIG4L~1~15=0x3f,0xe,Write Protect Program Flash Page 14 CONFIG4L~1~16=0x3f,0xf,Write Protect Program Flash Page 15 CONFIG4L~1~17=0x3f,0x10,Write Protect Program Flash Page 16 CONFIG4L~1~18=0x3f,0x11,Write Protect Program Flash Page 17 CONFIG4L~1~19=0x3f,0x12,Write Protect Program Flash Page 18 CONFIG4L~1~20=0x3f,0x13,Write Protect Program Flash Page 19 CONFIG4L~1~21=0x3f,0x14,Write Protect Program Flash Page 20 CONFIG4L~1~22=0x3f,0x15,Write Protect Program Flash Page 21 CONFIG4L~1~23=0x3f,0x16,Write Protect Program Flash Page 22 CONFIG4L~1~24=0x3f,0x17,Write Protect Program Flash Page 23 CONFIG4L~1~25=0x3f,0x18,Write Protect Program Flash Page 24 CONFIG4L~1~26=0x3f,0x19,Write Protect Program Flash Page 25 CONFIG4L~1~27=0x3f,0x1a,Write Protect Program Flash Page 26 CONFIG4L~1~28=0x3f,0x1b,Write Protect Program Flash Page 27 CONFIG4L~1~29=0x3f,0x1c,Write Protect Program Flash Page 28 CONFIG4L~1~30=0x3f,0x1d,Write Protect Program Flash Page 29 CONFIG4L~1~31=0x3f,0x1e,Write Protect Program Flash Page 30 CONFIG4L~1~32=0x3f,0x1f,Write Protect Program Flash Page 31 CONFIG4L~1~33=0x3f,0x20,Write Protect Program Flash Page 32 CONFIG4L~1~34=0x3f,0x21,Write Protect Program Flash Page 33 CONFIG4L~1~35=0x3f,0x22,Write Protect Program Flash Page 34 CONFIG4L~1~36=0x3f,0x23,Write Protect Program Flash Page 35 CONFIG4L~1~37=0x3f,0x24,Write Protect Program Flash Page 36 CONFIG4L~1~38=0x3f,0x25,Write Protect Program Flash Page 37 CONFIG4L~1~39=0x3f,0x26,Write Protect Program Flash Page 38 CONFIG4L~1~40=0x3f,0x27,Write Protect Program Flash Page 39 CONFIG4L~1~41=0x3f,0x28,Write Protect Program Flash Page 40 CONFIG4L~1~42=0x3f,0x29,Write Protect Program Flash Page 41 CONFIG4L~1~43=0x3f,0x2a,Write Protect Program Flash Page 42 CONFIG4L~1~44=0x3f,0x2b,Write Protect Program Flash Page 43 CONFIG4L~1~45=0x3f,0x2c,Write Protect Program Flash Page 44 CONFIG4L~1~46=0x3f,0x2d,Write Protect Program Flash Page 45 CONFIG4L~1~47=0x3f,0x2e,Write Protect Program Flash Page 46 CONFIG4L~1~48=0x3f,0x2f,Write Protect Program Flash Page 47 CONFIG4L~1~49=0x3f,0x30,Write Protect Program Flash Page 48 CONFIG4L~1~50=0x3f,0x31,Write Protect Program Flash Page 49 CONFIG4L~1~51=0x3f,0x32,Write Protect Program Flash Page 50 CONFIG4L~1~52=0x3f,0x33,Write Protect Program Flash Page 51 CONFIG4L~1~53=0x3f,0x34,Write Protect Program Flash Page 52 CONFIG4L~1~54=0x3f,0x35,Write Protect Program Flash Page 53 CONFIG4L~1~55=0x3f,0x36,Write Protect Program Flash Page 54 CONFIG4L~1~56=0x3f,0x37,Write Protect Program Flash Page 55 CONFIG4L~1~57=0x3f,0x38,Write Protect Program Flash Page 56 CONFIG4L~1~58=0x3f,0x39,Write Protect Program Flash Page 57 CONFIG4L~1~59=0x3f,0x3a,Write Protect Program Flash Page 58 CONFIG4L~1~60=0x3f,0x3b,Write Protect Program Flash Page 59 CONFIG4L~1~61=0x3f,0x3c,Write Protect Program Flash Page 60 CONFIG4L~1~62=0x3f,0x3d,Write Protect Program Flash Page 61 CONFIG4L~1~63=0x3f,0x3e,Write Protect Program Flash Page 62 CONFIG4L~1~64=0x3f,0x3f,Write Protect Program Flash Page 63 CONFIG4L~2~1=0x40,0x40,Pages WPFP<5:0> to (Configuration Words page) write/erase protected CONFIG4L~2~2=0x40,0x0,Page 0 to WPFP<5:0> erase/write-protected CONFIG4L~3~1=0x80,0x80,Disabled CONFIG4L~3~2=0x80,0x0,Enabled CONFIG4H_unused=0x0 CONFIG4H~1=WPDIS,0x1,Write Protect Disable bit CONFIG4H~2=RESERVED,0xf0,RESERVED CONFIG4H~1~1=0x1,0x1,Disabled CONFIG4H~1~2=0x1,0x0,Enabled CONFIG4H~2~1=0xf0,0xf0,RESERVED erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F46J13] pgmmem=0x0 ~pgmmem=0xfff7 cfgmem=0xfff8 ~cfgmem=0xffff userid= ~userid= eedata= ~eedata= devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0x59a0 configslots=8 0xfff8=CONFIG1L 0xfff9=CONFIG1H 0xfffa=CONFIG2L 0xfffb=CONFIG2H 0xfffc=CONFIG3L 0xfffd=CONFIG3H 0xfffe=CONFIG4L 0xffff=CONFIG4H CONFIG1L_unused=0x0 CONFIG1L~1=WDTEN,0x1,Watchdog Timer CONFIG1L~2=PLLDIV,0xe,PLL Prescaler Selection bits (PLLSEL = 0) CONFIG1L~3=CFGPLLEN,0x10,PLL Configuration Enable Bit CONFIG1L~4=STVREN,0x20,Stack Overflow/Underflow Reset CONFIG1L~5=XINST,0x40,Extended Instruction Set CONFIG1L~6=DEBUG,0x80,Background Debug CONFIG1L~1~1=0x1,0x1,Enabled CONFIG1L~1~2=0x1,0x0,Disabled CONFIG1L~2~1=0xe,0xe,No prescale (4 MHz oscillator input drives PLL directly) CONFIG1L~2~2=0xe,0xc,Divide by 2 (8 MHz oscillator input) CONFIG1L~2~3=0xe,0xa,Divide by 3 (12 MHz oscillator input) CONFIG1L~2~4=0xe,0x8,Divide by 4 (16 MHz oscillator input) CONFIG1L~2~5=0xe,0x6,Divide by 5 (20 MHz oscillator input) CONFIG1L~2~6=0xe,0x4,Divide by 6 (24 MHz oscillator input) CONFIG1L~2~7=0xe,0x2,Divide by 10 (40 MHz oscillator input) CONFIG1L~2~8=0xe,0x0,Divide by 12 (48 MHz oscillator input) CONFIG1L~3~1=0x10,0x10,Enabled CONFIG1L~3~2=0x10,0x0,Disabled CONFIG1L~4~1=0x20,0x20,Enabled CONFIG1L~4~2=0x20,0x0,Disabled CONFIG1L~5~1=0x40,0x40,Enabled CONFIG1L~5~2=0x40,0x0,Disabled CONFIG1L~6~1=0x80,0x80,Disabled CONFIG1L~6~2=0x80,0x0,Enabled CONFIG1H_unused=0x0 CONFIG1H~1=CP0,0x4,Code Protect CONFIG1H~2=SIGN,0x8,Config Word Signature Bit CONFIG1H~3=RESERVED,0xf0,RESERVED CONFIG1H~1~1=0x4,0x4,Disabled CONFIG1H~1~2=0x4,0x0,Enabled CONFIG1H~2~1=0x8,0x8,Bulk erase of memory not conducated CONFIG1H~2~2=0x8,0x0,Bulk erase of memory area complete CONFIG1H~3~1=0xf0,0xf0,RESERVED CONFIG2L_unused=0x0 CONFIG2L~1=OSC,0x7,Oscillator CONFIG2L~2=SOSCSEL,0x18,T1OSC/SOSC Power Selection Bits CONFIG2L~3=CLKOEC,0x20,EC Clock Out Enable Bit CONFIG2L~4=FCMEN,0x40,Fail-Safe Clock Monitor CONFIG2L~5=IESO,0x80,Internal External Oscillator Switch Over Mode CONFIG2L~1~1=0x7,0x7,EC+PLL (CLKO-RA6), USB-EC+PLL CONFIG2L~1~2=0x7,0x6,EC (CLKO-RA6), USB-EC CONFIG2L~1~3=0x7,0x5,HS+PLL, USB-HS+PLL CONFIG2L~1~4=0x7,0x4,HS, USB-HS CONFIG2L~1~5=0x7,0x3,INTOSCPLLO (CLKO-RA6) CONFIG2L~1~6=0x7,0x2,INTOSCPLL CONFIG2L~1~7=0x7,0x1,INTOSCO (CLKO-RA6) CONFIG2L~1~8=0x7,0x0,INTOSC CONFIG2L~2~1=0x18,0x18,High Security Code Protection Enable CONFIG2L~2~2=0x18,0x10,Digital (SCLKI) mode selected CONFIG2L~2~3=0x18,0x8,Low Power T1OSC/SOSC circuit selected CONFIG2L~2~4=0x18,0x0,Reserved CONFIG2L~3~1=0x20,0x20,Enabled CONFIG2L~3~2=0x20,0x0,Disabled CONFIG2L~4~1=0x40,0x0,Disabled CONFIG2L~4~2=0x40,0x40,Enabled CONFIG2L~5~1=0x80,0x0,Disabled CONFIG2L~5~2=0x80,0x80,Enabled CONFIG2H_unused=0x0 CONFIG2H~1=WDTPS,0xf,Watchdog Postscaler CONFIG2H~2=RESERVED,0xf0,RESERVED CONFIG2H~1~1=0xf,0xf,1:32768 CONFIG2H~1~2=0xf,0xe,1:16384 CONFIG2H~1~3=0xf,0xd,1:8192 CONFIG2H~1~4=0xf,0xc,1:4096 CONFIG2H~1~5=0xf,0xb,1:2048 CONFIG2H~1~6=0xf,0xa,1:1024 CONFIG2H~1~7=0xf,0x9,1:512 CONFIG2H~1~8=0xf,0x8,1:256 CONFIG2H~1~9=0xf,0x7,1:128 CONFIG2H~1~10=0xf,0x6,1:64 CONFIG2H~1~11=0xf,0x5,1:32 CONFIG2H~1~12=0xf,0x4,1:16 CONFIG2H~1~13=0xf,0x3,1:8 CONFIG2H~1~14=0xf,0x2,1:4 CONFIG2H~1~15=0xf,0x1,1:2 CONFIG2H~1~16=0xf,0x0,1:1 CONFIG2H~2~1=0xf0,0xf0,RESERVED CONFIG3L_unused=0x0 CONFIG3L~1=DSWDTOSC,0x1,DSWDT Clock Select CONFIG3L~2=RTCOSC,0x2,RTCC Clock Select CONFIG3L~3=DSBOREN,0x4,Deep Sleep BOR CONFIG3L~4=DSWDTEN,0x8,Deep Sleep Watchdog Timer CONFIG3L~5=DSWDTPS,0xf0,Deep Sleep Watchdog Postscaler CONFIG3L~1~1=0x1,0x1,DSWDT uses INTRC CONFIG3L~1~2=0x1,0x0,DSWDT uses T1OSC/T1CKI CONFIG3L~2~1=0x2,0x2,RTCC uses T1OSC/T1CKI CONFIG3L~2~2=0x2,0x0,RTCC uses INTRC CONFIG3L~3~1=0x4,0x4,Enabled CONFIG3L~3~2=0x4,0x0,Disabled CONFIG3L~4~1=0x8,0x8,Enabled CONFIG3L~4~2=0x8,0x0,Disabled CONFIG3L~5~1=0xf0,0xf0,1:2,147,483,648 (25.7 days) CONFIG3L~5~2=0xf0,0xe0,1:536,870,912 (6.4 days) CONFIG3L~5~3=0xf0,0xd0,1:134,217,728 (38.5 hours) CONFIG3L~5~4=0xf0,0xc0,1:33,554,432 (9.6 hours) CONFIG3L~5~5=0xf0,0xb0,1:8,388,608 (2.4 hours) CONFIG3L~5~6=0xf0,0xa0,1:2,097,152 (36 minutes) CONFIG3L~5~7=0xf0,0x90,1:524,288 (9 minutes) CONFIG3L~5~8=0xf0,0x80,1:131,072 (135 seconds) CONFIG3L~5~9=0xf0,0x70,1:32,768 (34 seconds) CONFIG3L~5~10=0xf0,0x60,1:8,192 (8.5 seconds) CONFIG3L~5~11=0xf0,0x50,1:2,048 (2.1 seconds) CONFIG3L~5~12=0xf0,0x40,1:512 (528 ms) CONFIG3L~5~13=0xf0,0x30,1:128 (132 ms) CONFIG3L~5~14=0xf0,0x20,1:32 (33 ms) CONFIG3L~5~15=0xf0,0x10,1:8 (8.3 ms) CONFIG3L~5~16=0xf0,0x0,1:2 (2.1 ms) CONFIG3H_unused=0x0 CONFIG3H~1=IOL1WAY,0x1,IOLOCK One-Way Set Enable bit CONFIG3H~2=ADCSEL,0x2,ADC 10 or 12 Bit Select CONFIG3H~3=PLLSEL,0x4,PLL Selection Bit CONFIG3H~4=MSSP7B_EN,0x8,MSSP address masking CONFIG3H~5=RESERVED,0xf0,RESERVED CONFIG3H~1~1=0x1,0x1,Enabled CONFIG3H~1~2=0x1,0x0,Disabled CONFIG3H~2~1=0x2,0x2,10 - Bit ADC Enabled CONFIG3H~2~2=0x2,0x0,12 - Bit ADC Enabed CONFIG3H~3~1=0x4,0x0,Selects 96MHz PLL CONFIG3H~3~2=0x4,0x4,Selects 4x PLL CONFIG3H~4~1=0x8,0x8,7 Bit address masking mode CONFIG3H~4~2=0x8,0x0,5 Bit address masking mode CONFIG3H~5~1=0xf0,0xf0,RESERVED CONFIG4L_unused=0x0 CONFIG4L~1=WPFP,0x3f,Write/Erase Protect Page Start/End Location CONFIG4L~2=WPCFG,0x80,Write/Erase Protect Configuration Region CONFIG4L~1~1=0x3f,0x0,Write Protect Program Flash Page 0 CONFIG4L~1~2=0x3f,0x1,Write Protect Program Flash Page 1 CONFIG4L~1~3=0x3f,0x2,Write Protect Program Flash Page 2 CONFIG4L~1~4=0x3f,0x3,Write Protect Program Flash Page 3 CONFIG4L~1~5=0x3f,0x4,Write Protect Program Flash Page 4 CONFIG4L~1~6=0x3f,0x5,Write Protect Program Flash Page 5 CONFIG4L~1~7=0x3f,0x6,Write Protect Program Flash Page 6 CONFIG4L~1~8=0x3f,0x7,Write Protect Program Flash Page 7 CONFIG4L~1~9=0x3f,0x8,Write Protect Program Flash Page 8 CONFIG4L~1~10=0x3f,0x9,Write Protect Program Flash Page 9 CONFIG4L~1~11=0x3f,0xa,Write Protect Program Flash Page 10 CONFIG4L~1~12=0x3f,0xb,Write Protect Program Flash Page 11 CONFIG4L~1~13=0x3f,0xc,Write Protect Program Flash Page 12 CONFIG4L~1~14=0x3f,0xd,Write Protect Program Flash Page 13 CONFIG4L~1~15=0x3f,0xe,Write Protect Program Flash Page 14 CONFIG4L~1~16=0x3f,0xf,Write Protect Program Flash Page 15 CONFIG4L~1~17=0x3f,0x10,Write Protect Program Flash Page 16 CONFIG4L~1~18=0x3f,0x11,Write Protect Program Flash Page 17 CONFIG4L~1~19=0x3f,0x12,Write Protect Program Flash Page 18 CONFIG4L~1~20=0x3f,0x13,Write Protect Program Flash Page 19 CONFIG4L~1~21=0x3f,0x14,Write Protect Program Flash Page 20 CONFIG4L~1~22=0x3f,0x15,Write Protect Program Flash Page 21 CONFIG4L~1~23=0x3f,0x16,Write Protect Program Flash Page 22 CONFIG4L~1~24=0x3f,0x17,Write Protect Program Flash Page 23 CONFIG4L~1~25=0x3f,0x18,Write Protect Program Flash Page 24 CONFIG4L~1~26=0x3f,0x19,Write Protect Program Flash Page 25 CONFIG4L~1~27=0x3f,0x1a,Write Protect Program Flash Page 26 CONFIG4L~1~28=0x3f,0x1b,Write Protect Program Flash Page 27 CONFIG4L~1~29=0x3f,0x1c,Write Protect Program Flash Page 28 CONFIG4L~1~30=0x3f,0x1d,Write Protect Program Flash Page 29 CONFIG4L~1~31=0x3f,0x1e,Write Protect Program Flash Page 30 CONFIG4L~1~32=0x3f,0x1f,Write Protect Program Flash Page 31 CONFIG4L~1~33=0x3f,0x20,Write Protect Program Flash Page 32 CONFIG4L~1~34=0x3f,0x21,Write Protect Program Flash Page 33 CONFIG4L~1~35=0x3f,0x22,Write Protect Program Flash Page 34 CONFIG4L~1~36=0x3f,0x23,Write Protect Program Flash Page 35 CONFIG4L~1~37=0x3f,0x24,Write Protect Program Flash Page 36 CONFIG4L~1~38=0x3f,0x25,Write Protect Program Flash Page 37 CONFIG4L~1~39=0x3f,0x26,Write Protect Program Flash Page 38 CONFIG4L~1~40=0x3f,0x27,Write Protect Program Flash Page 39 CONFIG4L~1~41=0x3f,0x28,Write Protect Program Flash Page 40 CONFIG4L~1~42=0x3f,0x29,Write Protect Program Flash Page 41 CONFIG4L~1~43=0x3f,0x2a,Write Protect Program Flash Page 42 CONFIG4L~1~44=0x3f,0x2b,Write Protect Program Flash Page 43 CONFIG4L~1~45=0x3f,0x2c,Write Protect Program Flash Page 44 CONFIG4L~1~46=0x3f,0x2d,Write Protect Program Flash Page 45 CONFIG4L~1~47=0x3f,0x2e,Write Protect Program Flash Page 46 CONFIG4L~1~48=0x3f,0x2f,Write Protect Program Flash Page 47 CONFIG4L~1~49=0x3f,0x30,Write Protect Program Flash Page 48 CONFIG4L~1~50=0x3f,0x31,Write Protect Program Flash Page 49 CONFIG4L~1~51=0x3f,0x32,Write Protect Program Flash Page 50 CONFIG4L~1~52=0x3f,0x33,Write Protect Program Flash Page 51 CONFIG4L~1~53=0x3f,0x34,Write Protect Program Flash Page 52 CONFIG4L~1~54=0x3f,0x35,Write Protect Program Flash Page 53 CONFIG4L~1~55=0x3f,0x36,Write Protect Program Flash Page 54 CONFIG4L~1~56=0x3f,0x37,Write Protect Program Flash Page 55 CONFIG4L~1~57=0x3f,0x38,Write Protect Program Flash Page 56 CONFIG4L~1~58=0x3f,0x39,Write Protect Program Flash Page 57 CONFIG4L~1~59=0x3f,0x3a,Write Protect Program Flash Page 58 CONFIG4L~1~60=0x3f,0x3b,Write Protect Program Flash Page 59 CONFIG4L~1~61=0x3f,0x3c,Write Protect Program Flash Page 60 CONFIG4L~1~62=0x3f,0x3d,Write Protect Program Flash Page 61 CONFIG4L~1~63=0x3f,0x3e,Write Protect Program Flash Page 62 CONFIG4L~1~64=0x3f,0x3f,Write Protect Program Flash Page 63 CONFIG4L~2~1=0x80,0x80,Disabled CONFIG4L~2~2=0x80,0x0,Enabled CONFIG4H_unused=0x0 CONFIG4H~1=WPDIS,0x1,Write Protect Disable bit CONFIG4H~2=WPEND,0x2,Write/Erase Protect Region Select bit (valid when WPDIS = 0) CONFIG4H~3=RESERVED,0xf0,RESERVED CONFIG4H~1~1=0x1,0x1,Disabled CONFIG4H~1~2=0x1,0x0,Enabled CONFIG4H~2~1=0x2,0x2,Pages WPFP<6:0> to (Configuration Words page) write/erase protected CONFIG4H~2~2=0x2,0x0,Page 0 to WPFP<6:0> erase/write-protected CONFIG4H~3~1=0xf0,0xf0,RESERVED erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F46J50] pgmmem=0x0 ~pgmmem=0xfff7 cfgmem=0xfff8 ~cfgmem=0xffff userid= ~userid= eedata= ~eedata= devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0x4ca0 configslots=8 0xfff8=CONFIG1L 0xfff9=CONFIG1H 0xfffa=CONFIG2L 0xfffb=CONFIG2H 0xfffc=CONFIG3L 0xfffd=CONFIG3H 0xfffe=CONFIG4L 0xffff=CONFIG4H CONFIG1L_unused=0x0 CONFIG1L~1=WDTEN,0x1,Watchdog Timer CONFIG1L~2=PLLDIV,0xe,PLL Prescaler Selection bits CONFIG1L~3=STVREN,0x20,Stack Overflow/Underflow Reset CONFIG1L~4=XINST,0x40,Extended Instruction Set CONFIG1L~5=DEBUG,0x80,Background Debug CONFIG1L~1~1=0x1,0x1,Enabled CONFIG1L~1~2=0x1,0x0,Disabled CONFIG1L~2~1=0xe,0xe,No prescale (4 MHz oscillator input drives PLL directly) CONFIG1L~2~2=0xe,0xc,Divide by 2 (8 MHz oscillator input) CONFIG1L~2~3=0xe,0xa,Divide by 3 (12 MHz oscillator input) CONFIG1L~2~4=0xe,0x8,Divide by 4 (16 MHz oscillator input) CONFIG1L~2~5=0xe,0x6,Divide by 5 (20 MHz oscillator input) CONFIG1L~2~6=0xe,0x4,Divide by 6 (24 MHz oscillator input) CONFIG1L~2~7=0xe,0x2,Divide by 10 (40 MHz oscillator input) CONFIG1L~2~8=0xe,0x0,Divide by 12 (48 MHz oscillator input) CONFIG1L~3~1=0x20,0x20,Enabled CONFIG1L~3~2=0x20,0x0,Disabled CONFIG1L~4~1=0x40,0x40,Enabled CONFIG1L~4~2=0x40,0x0,Disabled CONFIG1L~5~1=0x80,0x80,Disabled CONFIG1L~5~2=0x80,0x0,Enabled CONFIG1H_unused=0x0 CONFIG1H~1=CPUDIV,0x3,CPU System Clock Postscaler CONFIG1H~2=CP0,0x4,Code Protect CONFIG1H~3=SIGN,0x8,Config Word Signature Bit CONFIG1H~4=RESERVED,0xf0,RESERVED CONFIG1H~1~1=0x3,0x3,No CPU system clock divide CONFIG1H~1~2=0x3,0x2,CPU system clock divide by 2 CONFIG1H~1~3=0x3,0x1,CPU system clock divide by 3 CONFIG1H~1~4=0x3,0x0,CPU system clock divide by 6 CONFIG1H~2~1=0x4,0x4,Disabled CONFIG1H~2~2=0x4,0x0,Enabled CONFIG1H~3~1=0x8,0x8,Bulk erase of memory not conducated CONFIG1H~3~2=0x8,0x0,Bulk erase of memory area complete CONFIG1H~4~1=0xf0,0xf0,RESERVED CONFIG2L_unused=0x0 CONFIG2L~1=OSC,0x7,Oscillator CONFIG2L~2=T1DIG,0x8,T1OSCEN Enforcement CONFIG2L~3=LPT1OSC,0x10,Low-Power Timer1 Oscillator CONFIG2L~4=FCMEN,0x40,Fail-Safe Clock Monitor CONFIG2L~5=IESO,0x80,Internal External Oscillator Switch Over Mode CONFIG2L~1~1=0x7,0x7,EC+PLL (CLKO-RA6), USB-EC+PLL CONFIG2L~1~2=0x7,0x6,EC (CLKO-RA6), USB-EC CONFIG2L~1~3=0x7,0x5,HS+PLL, USB-HS+PLL CONFIG2L~1~4=0x7,0x4,HS, USB-HS CONFIG2L~1~5=0x7,0x3,INTOSCPLLO (CLKO-RA6) CONFIG2L~1~6=0x7,0x2,INTOSCPLL CONFIG2L~1~7=0x7,0x1,INTOSCO (CLKO-RA6) CONFIG2L~1~8=0x7,0x0,INTOSC CONFIG2L~2~1=0x8,0x8,Enabled CONFIG2L~2~2=0x8,0x0,Disabled CONFIG2L~3~1=0x10,0x10,Disabled CONFIG2L~3~2=0x10,0x0,Enabled CONFIG2L~4~1=0x40,0x0,Disabled CONFIG2L~4~2=0x40,0x40,Enabled CONFIG2L~5~1=0x80,0x0,Disabled CONFIG2L~5~2=0x80,0x80,Enabled CONFIG2H_unused=0x0 CONFIG2H~1=WDTPS,0xf,Watchdog Postscaler CONFIG2H~2=RESERVED,0xf0,RESERVED CONFIG2H~1~1=0xf,0xf,1:32768 CONFIG2H~1~2=0xf,0xe,1:16384 CONFIG2H~1~3=0xf,0xd,1:8192 CONFIG2H~1~4=0xf,0xc,1:4096 CONFIG2H~1~5=0xf,0xb,1:2048 CONFIG2H~1~6=0xf,0xa,1:1024 CONFIG2H~1~7=0xf,0x9,1:512 CONFIG2H~1~8=0xf,0x8,1:256 CONFIG2H~1~9=0xf,0x7,1:128 CONFIG2H~1~10=0xf,0x6,1:64 CONFIG2H~1~11=0xf,0x5,1:32 CONFIG2H~1~12=0xf,0x4,1:16 CONFIG2H~1~13=0xf,0x3,1:8 CONFIG2H~1~14=0xf,0x2,1:4 CONFIG2H~1~15=0xf,0x1,1:2 CONFIG2H~1~16=0xf,0x0,1:1 CONFIG2H~2~1=0xf0,0xf0,RESERVED CONFIG3L_unused=0x0 CONFIG3L~1=DSWDTOSC,0x1,DSWDT Clock Select CONFIG3L~2=RTCOSC,0x2,RTCC Clock Select CONFIG3L~3=DSBOREN,0x4,Deep Sleep BOR CONFIG3L~4=DSWDTEN,0x8,Deep Sleep Watchdog Timer CONFIG3L~5=DSWDTPS,0xf0,Deep Sleep Watchdog Postscaler CONFIG3L~1~1=0x1,0x1,DSWDT uses INTRC CONFIG3L~1~2=0x1,0x0,DSWDT uses T1OSC/T1CKI CONFIG3L~2~1=0x2,0x2,RTCC uses T1OSC/T1CKI CONFIG3L~2~2=0x2,0x0,RTCC uses INTRC CONFIG3L~3~1=0x4,0x4,Enabled CONFIG3L~3~2=0x4,0x0,Disabled CONFIG3L~4~1=0x8,0x8,Enabled CONFIG3L~4~2=0x8,0x0,Disabled CONFIG3L~5~1=0xf0,0xf0,1:2,147,483,648 (25.7 days) CONFIG3L~5~2=0xf0,0xe0,1:536,870,912 (6.4 days) CONFIG3L~5~3=0xf0,0xd0,1:134,217,728 (38.5 hours) CONFIG3L~5~4=0xf0,0xc0,1:33,554,432 (9.6 hours) CONFIG3L~5~5=0xf0,0xb0,1:8,388,608 (2.4 hours) CONFIG3L~5~6=0xf0,0xa0,1:2,097,152 (36 minutes) CONFIG3L~5~7=0xf0,0x90,1:524,288 (9 minutes) CONFIG3L~5~8=0xf0,0x80,1:131,072 (135 seconds) CONFIG3L~5~9=0xf0,0x70,1:32,768 (34 seconds) CONFIG3L~5~10=0xf0,0x60,1:8,192 (8.5 seconds) CONFIG3L~5~11=0xf0,0x50,1:2,048 (2.1 seconds) CONFIG3L~5~12=0xf0,0x40,1:512 (528 ms) CONFIG3L~5~13=0xf0,0x30,1:128 (132 ms) CONFIG3L~5~14=0xf0,0x20,1:32 (33 ms) CONFIG3L~5~15=0xf0,0x10,1:8 (8.3 ms) CONFIG3L~5~16=0xf0,0x0,1:2 (2.1 ms) CONFIG3H_unused=0x0 CONFIG3H~1=IOL1WAY,0x1,IOLOCK One-Way Set Enable bit CONFIG3H~2=MSSP7B_EN,0x8,MSSP address masking CONFIG3H~3=RESERVED,0xf0,RESERVED CONFIG3H~1~1=0x1,0x1,Enabled CONFIG3H~1~2=0x1,0x0,Disabled CONFIG3H~2~1=0x8,0x8,7 Bit address masking mode CONFIG3H~2~2=0x8,0x0,5 Bit address masking mode CONFIG3H~3~1=0xf0,0xf0,RESERVED CONFIG4L_unused=0x0 CONFIG4L~1=WPFP,0x3f,Write/Erase Protect Page Start/End Location CONFIG4L~2=WPEND,0x40,Write/Erase Protect Region Select bit (valid when WPDIS = 0) CONFIG4L~3=WPCFG,0x80,Write/Erase Protect Configuration Region CONFIG4L~1~1=0x3f,0x0,Write Protect Program Flash Page 0 CONFIG4L~1~2=0x3f,0x1,Write Protect Program Flash Page 1 CONFIG4L~1~3=0x3f,0x2,Write Protect Program Flash Page 2 CONFIG4L~1~4=0x3f,0x3,Write Protect Program Flash Page 3 CONFIG4L~1~5=0x3f,0x4,Write Protect Program Flash Page 4 CONFIG4L~1~6=0x3f,0x5,Write Protect Program Flash Page 5 CONFIG4L~1~7=0x3f,0x6,Write Protect Program Flash Page 6 CONFIG4L~1~8=0x3f,0x7,Write Protect Program Flash Page 7 CONFIG4L~1~9=0x3f,0x8,Write Protect Program Flash Page 8 CONFIG4L~1~10=0x3f,0x9,Write Protect Program Flash Page 9 CONFIG4L~1~11=0x3f,0xa,Write Protect Program Flash Page 10 CONFIG4L~1~12=0x3f,0xb,Write Protect Program Flash Page 11 CONFIG4L~1~13=0x3f,0xc,Write Protect Program Flash Page 12 CONFIG4L~1~14=0x3f,0xd,Write Protect Program Flash Page 13 CONFIG4L~1~15=0x3f,0xe,Write Protect Program Flash Page 14 CONFIG4L~1~16=0x3f,0xf,Write Protect Program Flash Page 15 CONFIG4L~1~17=0x3f,0x10,Write Protect Program Flash Page 16 CONFIG4L~1~18=0x3f,0x11,Write Protect Program Flash Page 17 CONFIG4L~1~19=0x3f,0x12,Write Protect Program Flash Page 18 CONFIG4L~1~20=0x3f,0x13,Write Protect Program Flash Page 19 CONFIG4L~1~21=0x3f,0x14,Write Protect Program Flash Page 20 CONFIG4L~1~22=0x3f,0x15,Write Protect Program Flash Page 21 CONFIG4L~1~23=0x3f,0x16,Write Protect Program Flash Page 22 CONFIG4L~1~24=0x3f,0x17,Write Protect Program Flash Page 23 CONFIG4L~1~25=0x3f,0x18,Write Protect Program Flash Page 24 CONFIG4L~1~26=0x3f,0x19,Write Protect Program Flash Page 25 CONFIG4L~1~27=0x3f,0x1a,Write Protect Program Flash Page 26 CONFIG4L~1~28=0x3f,0x1b,Write Protect Program Flash Page 27 CONFIG4L~1~29=0x3f,0x1c,Write Protect Program Flash Page 28 CONFIG4L~1~30=0x3f,0x1d,Write Protect Program Flash Page 29 CONFIG4L~1~31=0x3f,0x1e,Write Protect Program Flash Page 30 CONFIG4L~1~32=0x3f,0x1f,Write Protect Program Flash Page 31 CONFIG4L~1~33=0x3f,0x20,Write Protect Program Flash Page 32 CONFIG4L~1~34=0x3f,0x21,Write Protect Program Flash Page 33 CONFIG4L~1~35=0x3f,0x22,Write Protect Program Flash Page 34 CONFIG4L~1~36=0x3f,0x23,Write Protect Program Flash Page 35 CONFIG4L~1~37=0x3f,0x24,Write Protect Program Flash Page 36 CONFIG4L~1~38=0x3f,0x25,Write Protect Program Flash Page 37 CONFIG4L~1~39=0x3f,0x26,Write Protect Program Flash Page 38 CONFIG4L~1~40=0x3f,0x27,Write Protect Program Flash Page 39 CONFIG4L~1~41=0x3f,0x28,Write Protect Program Flash Page 40 CONFIG4L~1~42=0x3f,0x29,Write Protect Program Flash Page 41 CONFIG4L~1~43=0x3f,0x2a,Write Protect Program Flash Page 42 CONFIG4L~1~44=0x3f,0x2b,Write Protect Program Flash Page 43 CONFIG4L~1~45=0x3f,0x2c,Write Protect Program Flash Page 44 CONFIG4L~1~46=0x3f,0x2d,Write Protect Program Flash Page 45 CONFIG4L~1~47=0x3f,0x2e,Write Protect Program Flash Page 46 CONFIG4L~1~48=0x3f,0x2f,Write Protect Program Flash Page 47 CONFIG4L~1~49=0x3f,0x30,Write Protect Program Flash Page 48 CONFIG4L~1~50=0x3f,0x31,Write Protect Program Flash Page 49 CONFIG4L~1~51=0x3f,0x32,Write Protect Program Flash Page 50 CONFIG4L~1~52=0x3f,0x33,Write Protect Program Flash Page 51 CONFIG4L~1~53=0x3f,0x34,Write Protect Program Flash Page 52 CONFIG4L~1~54=0x3f,0x35,Write Protect Program Flash Page 53 CONFIG4L~1~55=0x3f,0x36,Write Protect Program Flash Page 54 CONFIG4L~1~56=0x3f,0x37,Write Protect Program Flash Page 55 CONFIG4L~1~57=0x3f,0x38,Write Protect Program Flash Page 56 CONFIG4L~1~58=0x3f,0x39,Write Protect Program Flash Page 57 CONFIG4L~1~59=0x3f,0x3a,Write Protect Program Flash Page 58 CONFIG4L~1~60=0x3f,0x3b,Write Protect Program Flash Page 59 CONFIG4L~1~61=0x3f,0x3c,Write Protect Program Flash Page 60 CONFIG4L~1~62=0x3f,0x3d,Write Protect Program Flash Page 61 CONFIG4L~1~63=0x3f,0x3e,Write Protect Program Flash Page 62 CONFIG4L~1~64=0x3f,0x3f,Write Protect Program Flash Page 63 CONFIG4L~2~1=0x40,0x40,Pages WPFP<5:0> to (Configuration Words page) write/erase protected CONFIG4L~2~2=0x40,0x0,Page 0 to WPFP<5:0> erase/write-protected CONFIG4L~3~1=0x80,0x80,Disabled CONFIG4L~3~2=0x80,0x0,Enabled CONFIG4H_unused=0x0 CONFIG4H~1=WPDIS,0x1,Write Protect Disable bit CONFIG4H~2=RESERVED,0xf0,RESERVED CONFIG4H~1~1=0x1,0x1,Disabled CONFIG4H~1~2=0x1,0x0,Enabled CONFIG4H~2~1=0xf0,0xf0,RESERVED erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F46J53] pgmmem=0x0 ~pgmmem=0xfff7 cfgmem=0xfff8 ~cfgmem=0xffff userid= ~userid= eedata= ~eedata= devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0x58a0 configslots=8 0xfff8=CONFIG1L 0xfff9=CONFIG1H 0xfffa=CONFIG2L 0xfffb=CONFIG2H 0xfffc=CONFIG3L 0xfffd=CONFIG3H 0xfffe=CONFIG4L 0xffff=CONFIG4H CONFIG1L_unused=0x0 CONFIG1L~1=WDTEN,0x1,Watchdog Timer CONFIG1L~2=PLLDIV,0xe,PLL Prescaler Selection bits (PLLSEL = 0) CONFIG1L~3=CFGPLLEN,0x10,PLL Configuration Enable Bit CONFIG1L~4=STVREN,0x20,Stack Overflow/Underflow Reset CONFIG1L~5=XINST,0x40,Extended Instruction Set CONFIG1L~6=DEBUG,0x80,Background Debug CONFIG1L~1~1=0x1,0x1,Enabled CONFIG1L~1~2=0x1,0x0,Disabled CONFIG1L~2~1=0xe,0xe,No prescale (4 MHz oscillator input drives PLL directly) CONFIG1L~2~2=0xe,0xc,Divide by 2 (8 MHz oscillator input) CONFIG1L~2~3=0xe,0xa,Divide by 3 (12 MHz oscillator input) CONFIG1L~2~4=0xe,0x8,Divide by 4 (16 MHz oscillator input) CONFIG1L~2~5=0xe,0x6,Divide by 5 (20 MHz oscillator input) CONFIG1L~2~6=0xe,0x4,Divide by 6 (24 MHz oscillator input) CONFIG1L~2~7=0xe,0x2,Divide by 10 (40 MHz oscillator input) CONFIG1L~2~8=0xe,0x0,Divide by 12 (48 MHz oscillator input) CONFIG1L~3~1=0x10,0x10,Enabled CONFIG1L~3~2=0x10,0x0,Disabled CONFIG1L~4~1=0x20,0x20,Enabled CONFIG1L~4~2=0x20,0x0,Disabled CONFIG1L~5~1=0x40,0x40,Enabled CONFIG1L~5~2=0x40,0x0,Disabled CONFIG1L~6~1=0x80,0x80,Disabled CONFIG1L~6~2=0x80,0x0,Enabled CONFIG1H_unused=0x0 CONFIG1H~1=CPUDIV,0x3,CPU System Clock Postscaler CONFIG1H~2=CP0,0x4,Code Protect CONFIG1H~3=SIGN,0x8,Config Word Signature Bit CONFIG1H~4=RESERVED,0xf0,RESERVED CONFIG1H~1~1=0x3,0x3,No CPU system clock divide CONFIG1H~1~2=0x3,0x2,CPU system clock divide by 2 CONFIG1H~1~3=0x3,0x1,CPU system clock divide by 3 CONFIG1H~1~4=0x3,0x0,CPU system clock divide by 6 CONFIG1H~2~1=0x4,0x4,Disabled CONFIG1H~2~2=0x4,0x0,Enabled CONFIG1H~3~1=0x8,0x8,Bulk erase of memory not conducated CONFIG1H~3~2=0x8,0x0,Bulk erase of memory area complete CONFIG1H~4~1=0xf0,0xf0,RESERVED CONFIG2L_unused=0x0 CONFIG2L~1=OSC,0x7,Oscillator CONFIG2L~2=SOSCSEL,0x18,T1OSC/SOSC Power Selection Bits CONFIG2L~3=CLKOEC,0x20,EC Clock Out Enable Bit CONFIG2L~4=FCMEN,0x40,Fail-Safe Clock Monitor CONFIG2L~5=IESO,0x80,Internal External Oscillator Switch Over Mode CONFIG2L~1~1=0x7,0x7,EC+PLL (CLKO-RA6), USB-EC+PLL CONFIG2L~1~2=0x7,0x6,EC (CLKO-RA6), USB-EC CONFIG2L~1~3=0x7,0x5,HS+PLL, USB-HS+PLL CONFIG2L~1~4=0x7,0x4,HS, USB-HS CONFIG2L~1~5=0x7,0x3,INTOSCPLLO (CLKO-RA6) CONFIG2L~1~6=0x7,0x2,INTOSCPLL CONFIG2L~1~7=0x7,0x1,INTOSCO (CLKO-RA6) CONFIG2L~1~8=0x7,0x0,INTOSC CONFIG2L~2~1=0x18,0x18,High Security Code Protection Enable CONFIG2L~2~2=0x18,0x10,Digital (SCLKI) mode selected CONFIG2L~2~3=0x18,0x8,Low Power T1OSC/SOSC circuit selected CONFIG2L~2~4=0x18,0x0,Reserved CONFIG2L~3~1=0x20,0x20,Enabled CONFIG2L~3~2=0x20,0x0,Disabled CONFIG2L~4~1=0x40,0x0,Disabled CONFIG2L~4~2=0x40,0x40,Enabled CONFIG2L~5~1=0x80,0x0,Disabled CONFIG2L~5~2=0x80,0x80,Enabled CONFIG2H_unused=0x0 CONFIG2H~1=WDTPS,0xf,Watchdog Postscaler CONFIG2H~2=RESERVED,0xf0,RESERVED CONFIG2H~1~1=0xf,0xf,1:32768 CONFIG2H~1~2=0xf,0xe,1:16384 CONFIG2H~1~3=0xf,0xd,1:8192 CONFIG2H~1~4=0xf,0xc,1:4096 CONFIG2H~1~5=0xf,0xb,1:2048 CONFIG2H~1~6=0xf,0xa,1:1024 CONFIG2H~1~7=0xf,0x9,1:512 CONFIG2H~1~8=0xf,0x8,1:256 CONFIG2H~1~9=0xf,0x7,1:128 CONFIG2H~1~10=0xf,0x6,1:64 CONFIG2H~1~11=0xf,0x5,1:32 CONFIG2H~1~12=0xf,0x4,1:16 CONFIG2H~1~13=0xf,0x3,1:8 CONFIG2H~1~14=0xf,0x2,1:4 CONFIG2H~1~15=0xf,0x1,1:2 CONFIG2H~1~16=0xf,0x0,1:1 CONFIG2H~2~1=0xf0,0xf0,RESERVED CONFIG3L_unused=0x0 CONFIG3L~1=DSWDTOSC,0x1,DSWDT Clock Select CONFIG3L~2=RTCOSC,0x2,RTCC Clock Select CONFIG3L~3=DSBOREN,0x4,Deep Sleep BOR CONFIG3L~4=DSWDTEN,0x8,Deep Sleep Watchdog Timer CONFIG3L~5=DSWDTPS,0xf0,Deep Sleep Watchdog Postscaler CONFIG3L~1~1=0x1,0x1,DSWDT uses INTRC CONFIG3L~1~2=0x1,0x0,DSWDT uses T1OSC/T1CKI CONFIG3L~2~1=0x2,0x2,RTCC uses T1OSC/T1CKI CONFIG3L~2~2=0x2,0x0,RTCC uses INTRC CONFIG3L~3~1=0x4,0x4,Enabled CONFIG3L~3~2=0x4,0x0,Disabled CONFIG3L~4~1=0x8,0x8,Enabled CONFIG3L~4~2=0x8,0x0,Disabled CONFIG3L~5~1=0xf0,0xf0,1:2,147,483,648 (25.7 days) CONFIG3L~5~2=0xf0,0xe0,1:536,870,912 (6.4 days) CONFIG3L~5~3=0xf0,0xd0,1:134,217,728 (38.5 hours) CONFIG3L~5~4=0xf0,0xc0,1:33,554,432 (9.6 hours) CONFIG3L~5~5=0xf0,0xb0,1:8,388,608 (2.4 hours) CONFIG3L~5~6=0xf0,0xa0,1:2,097,152 (36 minutes) CONFIG3L~5~7=0xf0,0x90,1:524,288 (9 minutes) CONFIG3L~5~8=0xf0,0x80,1:131,072 (135 seconds) CONFIG3L~5~9=0xf0,0x70,1:32,768 (34 seconds) CONFIG3L~5~10=0xf0,0x60,1:8,192 (8.5 seconds) CONFIG3L~5~11=0xf0,0x50,1:2,048 (2.1 seconds) CONFIG3L~5~12=0xf0,0x40,1:512 (528 ms) CONFIG3L~5~13=0xf0,0x30,1:128 (132 ms) CONFIG3L~5~14=0xf0,0x20,1:32 (33 ms) CONFIG3L~5~15=0xf0,0x10,1:8 (8.3 ms) CONFIG3L~5~16=0xf0,0x0,1:2 (2.1 ms) CONFIG3H_unused=0x0 CONFIG3H~1=IOL1WAY,0x1,IOLOCK One-Way Set Enable bit CONFIG3H~2=ADCSEL,0x2,ADC 10 or 12 Bit Select CONFIG3H~3=PLLSEL,0x4,PLL Selection Bit CONFIG3H~4=MSSP7B_EN,0x8,MSSP address masking CONFIG3H~5=RESERVED,0xf0,RESERVED CONFIG3H~1~1=0x1,0x1,Enabled CONFIG3H~1~2=0x1,0x0,Disabled CONFIG3H~2~1=0x2,0x2,10 - Bit ADC Enabled CONFIG3H~2~2=0x2,0x0,12 - Bit ADC Enabed CONFIG3H~3~1=0x4,0x0,Selects 96MHz PLL CONFIG3H~3~2=0x4,0x4,Selects 4x PLL CONFIG3H~4~1=0x8,0x8,7 Bit address masking mode CONFIG3H~4~2=0x8,0x0,5 Bit address masking mode CONFIG3H~5~1=0xf0,0xf0,RESERVED CONFIG4L_unused=0x0 CONFIG4L~1=WPFP,0x3f,Write/Erase Protect Page Start/End Location CONFIG4L~2=WPCFG,0x80,Write/Erase Protect Configuration Region CONFIG4L~1~1=0x3f,0x0,Write Protect Program Flash Page 0 CONFIG4L~1~2=0x3f,0x1,Write Protect Program Flash Page 1 CONFIG4L~1~3=0x3f,0x2,Write Protect Program Flash Page 2 CONFIG4L~1~4=0x3f,0x3,Write Protect Program Flash Page 3 CONFIG4L~1~5=0x3f,0x4,Write Protect Program Flash Page 4 CONFIG4L~1~6=0x3f,0x5,Write Protect Program Flash Page 5 CONFIG4L~1~7=0x3f,0x6,Write Protect Program Flash Page 6 CONFIG4L~1~8=0x3f,0x7,Write Protect Program Flash Page 7 CONFIG4L~1~9=0x3f,0x8,Write Protect Program Flash Page 8 CONFIG4L~1~10=0x3f,0x9,Write Protect Program Flash Page 9 CONFIG4L~1~11=0x3f,0xa,Write Protect Program Flash Page 10 CONFIG4L~1~12=0x3f,0xb,Write Protect Program Flash Page 11 CONFIG4L~1~13=0x3f,0xc,Write Protect Program Flash Page 12 CONFIG4L~1~14=0x3f,0xd,Write Protect Program Flash Page 13 CONFIG4L~1~15=0x3f,0xe,Write Protect Program Flash Page 14 CONFIG4L~1~16=0x3f,0xf,Write Protect Program Flash Page 15 CONFIG4L~1~17=0x3f,0x10,Write Protect Program Flash Page 16 CONFIG4L~1~18=0x3f,0x11,Write Protect Program Flash Page 17 CONFIG4L~1~19=0x3f,0x12,Write Protect Program Flash Page 18 CONFIG4L~1~20=0x3f,0x13,Write Protect Program Flash Page 19 CONFIG4L~1~21=0x3f,0x14,Write Protect Program Flash Page 20 CONFIG4L~1~22=0x3f,0x15,Write Protect Program Flash Page 21 CONFIG4L~1~23=0x3f,0x16,Write Protect Program Flash Page 22 CONFIG4L~1~24=0x3f,0x17,Write Protect Program Flash Page 23 CONFIG4L~1~25=0x3f,0x18,Write Protect Program Flash Page 24 CONFIG4L~1~26=0x3f,0x19,Write Protect Program Flash Page 25 CONFIG4L~1~27=0x3f,0x1a,Write Protect Program Flash Page 26 CONFIG4L~1~28=0x3f,0x1b,Write Protect Program Flash Page 27 CONFIG4L~1~29=0x3f,0x1c,Write Protect Program Flash Page 28 CONFIG4L~1~30=0x3f,0x1d,Write Protect Program Flash Page 29 CONFIG4L~1~31=0x3f,0x1e,Write Protect Program Flash Page 30 CONFIG4L~1~32=0x3f,0x1f,Write Protect Program Flash Page 31 CONFIG4L~1~33=0x3f,0x20,Write Protect Program Flash Page 32 CONFIG4L~1~34=0x3f,0x21,Write Protect Program Flash Page 33 CONFIG4L~1~35=0x3f,0x22,Write Protect Program Flash Page 34 CONFIG4L~1~36=0x3f,0x23,Write Protect Program Flash Page 35 CONFIG4L~1~37=0x3f,0x24,Write Protect Program Flash Page 36 CONFIG4L~1~38=0x3f,0x25,Write Protect Program Flash Page 37 CONFIG4L~1~39=0x3f,0x26,Write Protect Program Flash Page 38 CONFIG4L~1~40=0x3f,0x27,Write Protect Program Flash Page 39 CONFIG4L~1~41=0x3f,0x28,Write Protect Program Flash Page 40 CONFIG4L~1~42=0x3f,0x29,Write Protect Program Flash Page 41 CONFIG4L~1~43=0x3f,0x2a,Write Protect Program Flash Page 42 CONFIG4L~1~44=0x3f,0x2b,Write Protect Program Flash Page 43 CONFIG4L~1~45=0x3f,0x2c,Write Protect Program Flash Page 44 CONFIG4L~1~46=0x3f,0x2d,Write Protect Program Flash Page 45 CONFIG4L~1~47=0x3f,0x2e,Write Protect Program Flash Page 46 CONFIG4L~1~48=0x3f,0x2f,Write Protect Program Flash Page 47 CONFIG4L~1~49=0x3f,0x30,Write Protect Program Flash Page 48 CONFIG4L~1~50=0x3f,0x31,Write Protect Program Flash Page 49 CONFIG4L~1~51=0x3f,0x32,Write Protect Program Flash Page 50 CONFIG4L~1~52=0x3f,0x33,Write Protect Program Flash Page 51 CONFIG4L~1~53=0x3f,0x34,Write Protect Program Flash Page 52 CONFIG4L~1~54=0x3f,0x35,Write Protect Program Flash Page 53 CONFIG4L~1~55=0x3f,0x36,Write Protect Program Flash Page 54 CONFIG4L~1~56=0x3f,0x37,Write Protect Program Flash Page 55 CONFIG4L~1~57=0x3f,0x38,Write Protect Program Flash Page 56 CONFIG4L~1~58=0x3f,0x39,Write Protect Program Flash Page 57 CONFIG4L~1~59=0x3f,0x3a,Write Protect Program Flash Page 58 CONFIG4L~1~60=0x3f,0x3b,Write Protect Program Flash Page 59 CONFIG4L~1~61=0x3f,0x3c,Write Protect Program Flash Page 60 CONFIG4L~1~62=0x3f,0x3d,Write Protect Program Flash Page 61 CONFIG4L~1~63=0x3f,0x3e,Write Protect Program Flash Page 62 CONFIG4L~1~64=0x3f,0x3f,Write Protect Program Flash Page 63 CONFIG4L~2~1=0x80,0x80,Disabled CONFIG4L~2~2=0x80,0x0,Enabled CONFIG4H_unused=0x0 CONFIG4H~1=WPDIS,0x1,Write Protect Disable bit CONFIG4H~2=WPEND,0x2,Write/Erase Protect Region Select bit (valid when WPDIS = 0) CONFIG4H~3=LS48MHZ,0x8,Low Speed USB mode with 48 MHz system clock bit CONFIG4H~4=RESERVED,0xf0,RESERVED CONFIG4H~1~1=0x1,0x1,Disabled CONFIG4H~1~2=0x1,0x0,Enabled CONFIG4H~2~1=0x2,0x2,Pages WPFP<6:0> to (Configuration Words page) write/erase protected CONFIG4H~2~2=0x2,0x0,Page 0 to WPFP<6:0> erase/write-protected CONFIG4H~3~1=0x8,0x0,System clock at 24 MHz USB CLKEN divide-by is set to 4 CONFIG4H~3~2=0x8,0x8,System clock at 48 MHz USB CLKEN divide-by is set to 8 CONFIG4H~4~1=0xf0,0xf0,RESERVED erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F47J13] pgmmem=0x0 ~pgmmem=0x1fff7 cfgmem=0x1fff8 ~cfgmem=0x1ffff userid= ~userid= eedata= ~eedata= devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0x59e0 configslots=8 0x1fff8=CONFIG1L 0x1fff9=CONFIG1H 0x1fffa=CONFIG2L 0x1fffb=CONFIG2H 0x1fffc=CONFIG3L 0x1fffd=CONFIG3H 0x1fffe=CONFIG4L 0x1ffff=CONFIG4H CONFIG1L_unused=0x0 CONFIG1L~1=WDTEN,0x1,Watchdog Timer CONFIG1L~2=PLLDIV,0xe,PLL Prescaler Selection bits (PLLSEL = 0) CONFIG1L~3=CFGPLLEN,0x10,PLL Configuration Enable Bit CONFIG1L~4=STVREN,0x20,Stack Overflow/Underflow Reset CONFIG1L~5=XINST,0x40,Extended Instruction Set CONFIG1L~6=DEBUG,0x80,Background Debug CONFIG1L~1~1=0x1,0x1,Enabled CONFIG1L~1~2=0x1,0x0,Disabled CONFIG1L~2~1=0xe,0xe,No prescale (4 MHz oscillator input drives PLL directly) CONFIG1L~2~2=0xe,0xc,Divide by 2 (8 MHz oscillator input) CONFIG1L~2~3=0xe,0xa,Divide by 3 (12 MHz oscillator input) CONFIG1L~2~4=0xe,0x8,Divide by 4 (16 MHz oscillator input) CONFIG1L~2~5=0xe,0x6,Divide by 5 (20 MHz oscillator input) CONFIG1L~2~6=0xe,0x4,Divide by 6 (24 MHz oscillator input) CONFIG1L~2~7=0xe,0x2,Divide by 10 (40 MHz oscillator input) CONFIG1L~2~8=0xe,0x0,Divide by 12 (48 MHz oscillator input) CONFIG1L~3~1=0x10,0x10,Enabled CONFIG1L~3~2=0x10,0x0,Disabled CONFIG1L~4~1=0x20,0x20,Enabled CONFIG1L~4~2=0x20,0x0,Disabled CONFIG1L~5~1=0x40,0x40,Enabled CONFIG1L~5~2=0x40,0x0,Disabled CONFIG1L~6~1=0x80,0x80,Disabled CONFIG1L~6~2=0x80,0x0,Enabled CONFIG1H_unused=0x0 CONFIG1H~1=CP0,0x4,Code Protect CONFIG1H~2=SIGN,0x8,Config Word Signature Bit CONFIG1H~3=RESERVED,0xf0,RESERVED CONFIG1H~1~1=0x4,0x4,Disabled CONFIG1H~1~2=0x4,0x0,Enabled CONFIG1H~2~1=0x8,0x8,Bulk erase of memory not conducated CONFIG1H~2~2=0x8,0x0,Bulk erase of memory area complete CONFIG1H~3~1=0xf0,0xf0,RESERVED CONFIG2L_unused=0x0 CONFIG2L~1=OSC,0x7,Oscillator CONFIG2L~2=SOSCSEL,0x18,T1OSC/SOSC Power Selection Bits CONFIG2L~3=CLKOEC,0x20,EC Clock Out Enable Bit CONFIG2L~4=FCMEN,0x40,Fail-Safe Clock Monitor CONFIG2L~5=IESO,0x80,Internal External Oscillator Switch Over Mode CONFIG2L~1~1=0x7,0x7,EC+PLL (CLKO-RA6), USB-EC+PLL CONFIG2L~1~2=0x7,0x6,EC (CLKO-RA6), USB-EC CONFIG2L~1~3=0x7,0x5,HS+PLL, USB-HS+PLL CONFIG2L~1~4=0x7,0x4,HS, USB-HS CONFIG2L~1~5=0x7,0x3,INTOSCPLLO (CLKO-RA6) CONFIG2L~1~6=0x7,0x2,INTOSCPLL CONFIG2L~1~7=0x7,0x1,INTOSCO (CLKO-RA6) CONFIG2L~1~8=0x7,0x0,INTOSC CONFIG2L~2~1=0x18,0x18,High Security Code Protection Enable CONFIG2L~2~2=0x18,0x10,Digital (SCLKI) mode selected CONFIG2L~2~3=0x18,0x8,Low Power T1OSC/SOSC circuit selected CONFIG2L~2~4=0x18,0x0,Reserved CONFIG2L~3~1=0x20,0x20,Enabled CONFIG2L~3~2=0x20,0x0,Disabled CONFIG2L~4~1=0x40,0x0,Disabled CONFIG2L~4~2=0x40,0x40,Enabled CONFIG2L~5~1=0x80,0x0,Disabled CONFIG2L~5~2=0x80,0x80,Enabled CONFIG2H_unused=0x0 CONFIG2H~1=WDTPS,0xf,Watchdog Postscaler CONFIG2H~2=RESERVED,0xf0,RESERVED CONFIG2H~1~1=0xf,0xf,1:32768 CONFIG2H~1~2=0xf,0xe,1:16384 CONFIG2H~1~3=0xf,0xd,1:8192 CONFIG2H~1~4=0xf,0xc,1:4096 CONFIG2H~1~5=0xf,0xb,1:2048 CONFIG2H~1~6=0xf,0xa,1:1024 CONFIG2H~1~7=0xf,0x9,1:512 CONFIG2H~1~8=0xf,0x8,1:256 CONFIG2H~1~9=0xf,0x7,1:128 CONFIG2H~1~10=0xf,0x6,1:64 CONFIG2H~1~11=0xf,0x5,1:32 CONFIG2H~1~12=0xf,0x4,1:16 CONFIG2H~1~13=0xf,0x3,1:8 CONFIG2H~1~14=0xf,0x2,1:4 CONFIG2H~1~15=0xf,0x1,1:2 CONFIG2H~1~16=0xf,0x0,1:1 CONFIG2H~2~1=0xf0,0xf0,RESERVED CONFIG3L_unused=0x0 CONFIG3L~1=DSWDTOSC,0x1,DSWDT Clock Select CONFIG3L~2=RTCOSC,0x2,RTCC Clock Select CONFIG3L~3=DSBOREN,0x4,Deep Sleep BOR CONFIG3L~4=DSWDTEN,0x8,Deep Sleep Watchdog Timer CONFIG3L~5=DSWDTPS,0xf0,Deep Sleep Watchdog Postscaler CONFIG3L~1~1=0x1,0x1,DSWDT uses INTRC CONFIG3L~1~2=0x1,0x0,DSWDT uses T1OSC/T1CKI CONFIG3L~2~1=0x2,0x2,RTCC uses T1OSC/T1CKI CONFIG3L~2~2=0x2,0x0,RTCC uses INTRC CONFIG3L~3~1=0x4,0x4,Enabled CONFIG3L~3~2=0x4,0x0,Disabled CONFIG3L~4~1=0x8,0x8,Enabled CONFIG3L~4~2=0x8,0x0,Disabled CONFIG3L~5~1=0xf0,0xf0,1:2,147,483,648 (25.7 days) CONFIG3L~5~2=0xf0,0xe0,1:536,870,912 (6.4 days) CONFIG3L~5~3=0xf0,0xd0,1:134,217,728 (38.5 hours) CONFIG3L~5~4=0xf0,0xc0,1:33,554,432 (9.6 hours) CONFIG3L~5~5=0xf0,0xb0,1:8,388,608 (2.4 hours) CONFIG3L~5~6=0xf0,0xa0,1:2,097,152 (36 minutes) CONFIG3L~5~7=0xf0,0x90,1:524,288 (9 minutes) CONFIG3L~5~8=0xf0,0x80,1:131,072 (135 seconds) CONFIG3L~5~9=0xf0,0x70,1:32,768 (34 seconds) CONFIG3L~5~10=0xf0,0x60,1:8,192 (8.5 seconds) CONFIG3L~5~11=0xf0,0x50,1:2,048 (2.1 seconds) CONFIG3L~5~12=0xf0,0x40,1:512 (528 ms) CONFIG3L~5~13=0xf0,0x30,1:128 (132 ms) CONFIG3L~5~14=0xf0,0x20,1:32 (33 ms) CONFIG3L~5~15=0xf0,0x10,1:8 (8.3 ms) CONFIG3L~5~16=0xf0,0x0,1:2 (2.1 ms) CONFIG3H_unused=0x0 CONFIG3H~1=IOL1WAY,0x1,IOLOCK One-Way Set Enable bit CONFIG3H~2=ADCSEL,0x2,ADC 10 or 12 Bit Select CONFIG3H~3=PLLSEL,0x4,PLL Selection Bit CONFIG3H~4=MSSP7B_EN,0x8,MSSP address masking CONFIG3H~5=RESERVED,0xf0,RESERVED CONFIG3H~1~1=0x1,0x1,Enabled CONFIG3H~1~2=0x1,0x0,Disabled CONFIG3H~2~1=0x2,0x2,10 - Bit ADC Enabled CONFIG3H~2~2=0x2,0x0,12 - Bit ADC Enabed CONFIG3H~3~1=0x4,0x0,Selects 96MHz PLL CONFIG3H~3~2=0x4,0x4,Selects 4x PLL CONFIG3H~4~1=0x8,0x8,7 Bit address masking mode CONFIG3H~4~2=0x8,0x0,5 Bit address masking mode CONFIG3H~5~1=0xf0,0xf0,RESERVED CONFIG4L_unused=0x0 CONFIG4L~1=WPFP,0x7f,Write/Erase Protect Page Start/End Location CONFIG4L~2=WPCFG,0x80,Write/Erase Protect Configuration Region CONFIG4L~1~1=0x7f,0x0,Write Protect Program Flash Page 0 CONFIG4L~1~2=0x7f,0x1,Write Protect Program Flash Page 1 CONFIG4L~1~3=0x7f,0x2,Write Protect Program Flash Page 2 CONFIG4L~1~4=0x7f,0x3,Write Protect Program Flash Page 3 CONFIG4L~1~5=0x7f,0x4,Write Protect Program Flash Page 4 CONFIG4L~1~6=0x7f,0x5,Write Protect Program Flash Page 5 CONFIG4L~1~7=0x7f,0x6,Write Protect Program Flash Page 6 CONFIG4L~1~8=0x7f,0x7,Write Protect Program Flash Page 7 CONFIG4L~1~9=0x7f,0x8,Write Protect Program Flash Page 8 CONFIG4L~1~10=0x7f,0x9,Write Protect Program Flash Page 9 CONFIG4L~1~11=0x7f,0xa,Write Protect Program Flash Page 10 CONFIG4L~1~12=0x7f,0xb,Write Protect Program Flash Page 11 CONFIG4L~1~13=0x7f,0xc,Write Protect Program Flash Page 12 CONFIG4L~1~14=0x7f,0xd,Write Protect Program Flash Page 13 CONFIG4L~1~15=0x7f,0xe,Write Protect Program Flash Page 14 CONFIG4L~1~16=0x7f,0xf,Write Protect Program Flash Page 15 CONFIG4L~1~17=0x7f,0x10,Write Protect Program Flash Page 16 CONFIG4L~1~18=0x7f,0x11,Write Protect Program Flash Page 17 CONFIG4L~1~19=0x7f,0x12,Write Protect Program Flash Page 18 CONFIG4L~1~20=0x7f,0x13,Write Protect Program Flash Page 19 CONFIG4L~1~21=0x7f,0x14,Write Protect Program Flash Page 20 CONFIG4L~1~22=0x7f,0x15,Write Protect Program Flash Page 21 CONFIG4L~1~23=0x7f,0x16,Write Protect Program Flash Page 22 CONFIG4L~1~24=0x7f,0x17,Write Protect Program Flash Page 23 CONFIG4L~1~25=0x7f,0x18,Write Protect Program Flash Page 24 CONFIG4L~1~26=0x7f,0x19,Write Protect Program Flash Page 25 CONFIG4L~1~27=0x7f,0x1a,Write Protect Program Flash Page 26 CONFIG4L~1~28=0x7f,0x1b,Write Protect Program Flash Page 27 CONFIG4L~1~29=0x7f,0x1c,Write Protect Program Flash Page 28 CONFIG4L~1~30=0x7f,0x1d,Write Protect Program Flash Page 29 CONFIG4L~1~31=0x7f,0x1e,Write Protect Program Flash Page 30 CONFIG4L~1~32=0x7f,0x1f,Write Protect Program Flash Page 31 CONFIG4L~1~33=0x7f,0x20,Write Protect Program Flash Page 32 CONFIG4L~1~34=0x7f,0x21,Write Protect Program Flash Page 33 CONFIG4L~1~35=0x7f,0x22,Write Protect Program Flash Page 34 CONFIG4L~1~36=0x7f,0x23,Write Protect Program Flash Page 35 CONFIG4L~1~37=0x7f,0x24,Write Protect Program Flash Page 36 CONFIG4L~1~38=0x7f,0x25,Write Protect Program Flash Page 37 CONFIG4L~1~39=0x7f,0x26,Write Protect Program Flash Page 38 CONFIG4L~1~40=0x7f,0x27,Write Protect Program Flash Page 39 CONFIG4L~1~41=0x7f,0x28,Write Protect Program Flash Page 40 CONFIG4L~1~42=0x7f,0x29,Write Protect Program Flash Page 41 CONFIG4L~1~43=0x7f,0x2a,Write Protect Program Flash Page 42 CONFIG4L~1~44=0x7f,0x2b,Write Protect Program Flash Page 43 CONFIG4L~1~45=0x7f,0x2c,Write Protect Program Flash Page 44 CONFIG4L~1~46=0x7f,0x2d,Write Protect Program Flash Page 45 CONFIG4L~1~47=0x7f,0x2e,Write Protect Program Flash Page 46 CONFIG4L~1~48=0x7f,0x2f,Write Protect Program Flash Page 47 CONFIG4L~1~49=0x7f,0x30,Write Protect Program Flash Page 48 CONFIG4L~1~50=0x7f,0x31,Write Protect Program Flash Page 49 CONFIG4L~1~51=0x7f,0x32,Write Protect Program Flash Page 50 CONFIG4L~1~52=0x7f,0x33,Write Protect Program Flash Page 51 CONFIG4L~1~53=0x7f,0x34,Write Protect Program Flash Page 52 CONFIG4L~1~54=0x7f,0x35,Write Protect Program Flash Page 53 CONFIG4L~1~55=0x7f,0x36,Write Protect Program Flash Page 54 CONFIG4L~1~56=0x7f,0x37,Write Protect Program Flash Page 55 CONFIG4L~1~57=0x7f,0x38,Write Protect Program Flash Page 56 CONFIG4L~1~58=0x7f,0x39,Write Protect Program Flash Page 57 CONFIG4L~1~59=0x7f,0x3a,Write Protect Program Flash Page 58 CONFIG4L~1~60=0x7f,0x3b,Write Protect Program Flash Page 59 CONFIG4L~1~61=0x7f,0x3c,Write Protect Program Flash Page 60 CONFIG4L~1~62=0x7f,0x3d,Write Protect Program Flash Page 61 CONFIG4L~1~63=0x7f,0x3e,Write Protect Program Flash Page 62 CONFIG4L~1~64=0x7f,0x3f,Write Protect Program Flash Page 63 CONFIG4L~1~65=0x7f,0x40,Write Protect Program Flash Page 64 CONFIG4L~1~66=0x7f,0x41,Write Protect Program Flash Page 65 CONFIG4L~1~67=0x7f,0x42,Write Protect Program Flash Page 66 CONFIG4L~1~68=0x7f,0x43,Write Protect Program Flash Page 67 CONFIG4L~1~69=0x7f,0x44,Write Protect Program Flash Page 68 CONFIG4L~1~70=0x7f,0x45,Write Protect Program Flash Page 69 CONFIG4L~1~71=0x7f,0x46,Write Protect Program Flash Page 70 CONFIG4L~1~72=0x7f,0x47,Write Protect Program Flash Page 71 CONFIG4L~1~73=0x7f,0x48,Write Protect Program Flash Page 72 CONFIG4L~1~74=0x7f,0x49,Write Protect Program Flash Page 73 CONFIG4L~1~75=0x7f,0x4a,Write Protect Program Flash Page 74 CONFIG4L~1~76=0x7f,0x4b,Write Protect Program Flash Page 75 CONFIG4L~1~77=0x7f,0x4c,Write Protect Program Flash Page 76 CONFIG4L~1~78=0x7f,0x4d,Write Protect Program Flash Page 77 CONFIG4L~1~79=0x7f,0x4e,Write Protect Program Flash Page 78 CONFIG4L~1~80=0x7f,0x4f,Write Protect Program Flash Page 79 CONFIG4L~1~81=0x7f,0x50,Write Protect Program Flash Page 80 CONFIG4L~1~82=0x7f,0x51,Write Protect Program Flash Page 81 CONFIG4L~1~83=0x7f,0x52,Write Protect Program Flash Page 82 CONFIG4L~1~84=0x7f,0x53,Write Protect Program Flash Page 83 CONFIG4L~1~85=0x7f,0x54,Write Protect Program Flash Page 84 CONFIG4L~1~86=0x7f,0x55,Write Protect Program Flash Page 85 CONFIG4L~1~87=0x7f,0x56,Write Protect Program Flash Page 86 CONFIG4L~1~88=0x7f,0x57,Write Protect Program Flash Page 87 CONFIG4L~1~89=0x7f,0x58,Write Protect Program Flash Page 88 CONFIG4L~1~90=0x7f,0x59,Write Protect Program Flash Page 89 CONFIG4L~1~91=0x7f,0x5a,Write Protect Program Flash Page 90 CONFIG4L~1~92=0x7f,0x5b,Write Protect Program Flash Page 91 CONFIG4L~1~93=0x7f,0x5c,Write Protect Program Flash Page 92 CONFIG4L~1~94=0x7f,0x5d,Write Protect Program Flash Page 93 CONFIG4L~1~95=0x7f,0x5e,Write Protect Program Flash Page 94 CONFIG4L~1~96=0x7f,0x5f,Write Protect Program Flash Page 95 CONFIG4L~1~97=0x7f,0x60,Write Protect Program Flash Page 96 CONFIG4L~1~98=0x7f,0x61,Write Protect Program Flash Page 97 CONFIG4L~1~99=0x7f,0x62,Write Protect Program Flash Page 98 CONFIG4L~1~100=0x7f,0x63,Write Protect Program Flash Page 99 CONFIG4L~1~101=0x7f,0x64,Write Protect Program Flash Page 100 CONFIG4L~1~102=0x7f,0x65,Write Protect Program Flash Page 101 CONFIG4L~1~103=0x7f,0x66,Write Protect Program Flash Page 102 CONFIG4L~1~104=0x7f,0x67,Write Protect Program Flash Page 103 CONFIG4L~1~105=0x7f,0x68,Write Protect Program Flash Page 104 CONFIG4L~1~106=0x7f,0x69,Write Protect Program Flash Page 105 CONFIG4L~1~107=0x7f,0x6a,Write Protect Program Flash Page 106 CONFIG4L~1~108=0x7f,0x6b,Write Protect Program Flash Page 107 CONFIG4L~1~109=0x7f,0x6c,Write Protect Program Flash Page 108 CONFIG4L~1~110=0x7f,0x6d,Write Protect Program Flash Page 109 CONFIG4L~1~111=0x7f,0x6e,Write Protect Program Flash Page 110 CONFIG4L~1~112=0x7f,0x6f,Write Protect Program Flash Page 111 CONFIG4L~1~113=0x7f,0x70,Write Protect Program Flash Page 112 CONFIG4L~1~114=0x7f,0x71,Write Protect Program Flash Page 113 CONFIG4L~1~115=0x7f,0x72,Write Protect Program Flash Page 114 CONFIG4L~1~116=0x7f,0x73,Write Protect Program Flash Page 115 CONFIG4L~1~117=0x7f,0x74,Write Protect Program Flash Page 116 CONFIG4L~1~118=0x7f,0x75,Write Protect Program Flash Page 117 CONFIG4L~1~119=0x7f,0x76,Write Protect Program Flash Page 118 CONFIG4L~1~120=0x7f,0x77,Write Protect Program Flash Page 119 CONFIG4L~1~121=0x7f,0x78,Write Protect Program Flash Page 120 CONFIG4L~1~122=0x7f,0x79,Write Protect Program Flash Page 121 CONFIG4L~1~123=0x7f,0x7a,Write Protect Program Flash Page 122 CONFIG4L~1~124=0x7f,0x7b,Write Protect Program Flash Page 123 CONFIG4L~1~125=0x7f,0x7c,Write Protect Program Flash Page 124 CONFIG4L~1~126=0x7f,0x7d,Write Protect Program Flash Page 125 CONFIG4L~1~127=0x7f,0x7e,Write Protect Program Flash Page 126 CONFIG4L~1~128=0x7f,0x7f,Write Protect Program Flash Page 127 CONFIG4L~2~1=0x80,0x80,Disabled CONFIG4L~2~2=0x80,0x0,Enabled CONFIG4H_unused=0x0 CONFIG4H~1=WPDIS,0x1,Write Protect Disable bit CONFIG4H~2=WPEND,0x2,Write/Erase Protect Region Select bit (valid when WPDIS = 0) CONFIG4H~3=RESERVED,0xf0,RESERVED CONFIG4H~1~1=0x1,0x1,Disabled CONFIG4H~1~2=0x1,0x0,Enabled CONFIG4H~2~1=0x2,0x2,Pages WPFP<6:0> to (Configuration Words page) write/erase protected CONFIG4H~2~2=0x2,0x0,Page 0 to WPFP<6:0> erase/write-protected CONFIG4H~3~1=0xf0,0xf0,RESERVED erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F47J53] pgmmem=0x0 ~pgmmem=0x1fff7 cfgmem=0x1fff8 ~cfgmem=0x1ffff userid= ~userid= eedata= ~eedata= devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0x58e0 configslots=8 0x1fff8=CONFIG1L 0x1fff9=CONFIG1H 0x1fffa=CONFIG2L 0x1fffb=CONFIG2H 0x1fffc=CONFIG3L 0x1fffd=CONFIG3H 0x1fffe=CONFIG4L 0x1ffff=CONFIG4H CONFIG1L_unused=0x0 CONFIG1L~1=WDTEN,0x1,Watchdog Timer CONFIG1L~2=PLLDIV,0xe,PLL Prescaler Selection bits (PLLSEL = 0) CONFIG1L~3=CFGPLLEN,0x10,PLL Configuration Enable Bit CONFIG1L~4=STVREN,0x20,Stack Overflow/Underflow Reset CONFIG1L~5=XINST,0x40,Extended Instruction Set CONFIG1L~6=DEBUG,0x80,Background Debug CONFIG1L~1~1=0x1,0x1,Enabled CONFIG1L~1~2=0x1,0x0,Disabled CONFIG1L~2~1=0xe,0xe,No prescale (4 MHz oscillator input drives PLL directly) CONFIG1L~2~2=0xe,0xc,Divide by 2 (8 MHz oscillator input) CONFIG1L~2~3=0xe,0xa,Divide by 3 (12 MHz oscillator input) CONFIG1L~2~4=0xe,0x8,Divide by 4 (16 MHz oscillator input) CONFIG1L~2~5=0xe,0x6,Divide by 5 (20 MHz oscillator input) CONFIG1L~2~6=0xe,0x4,Divide by 6 (24 MHz oscillator input) CONFIG1L~2~7=0xe,0x2,Divide by 10 (40 MHz oscillator input) CONFIG1L~2~8=0xe,0x0,Divide by 12 (48 MHz oscillator input) CONFIG1L~3~1=0x10,0x10,Enabled CONFIG1L~3~2=0x10,0x0,Disabled CONFIG1L~4~1=0x20,0x20,Enabled CONFIG1L~4~2=0x20,0x0,Disabled CONFIG1L~5~1=0x40,0x40,Enabled CONFIG1L~5~2=0x40,0x0,Disabled CONFIG1L~6~1=0x80,0x80,Disabled CONFIG1L~6~2=0x80,0x0,Enabled CONFIG1H_unused=0x0 CONFIG1H~1=CPUDIV,0x3,CPU System Clock Postscaler CONFIG1H~2=CP0,0x4,Code Protect CONFIG1H~3=SIGN,0x8,Config Word Signature Bit CONFIG1H~4=RESERVED,0xf0,RESERVED CONFIG1H~1~1=0x3,0x3,No CPU system clock divide CONFIG1H~1~2=0x3,0x2,CPU system clock divide by 2 CONFIG1H~1~3=0x3,0x1,CPU system clock divide by 3 CONFIG1H~1~4=0x3,0x0,CPU system clock divide by 6 CONFIG1H~2~1=0x4,0x4,Disabled CONFIG1H~2~2=0x4,0x0,Enabled CONFIG1H~3~1=0x8,0x8,Bulk erase of memory not conducated CONFIG1H~3~2=0x8,0x0,Bulk erase of memory area complete CONFIG1H~4~1=0xf0,0xf0,RESERVED CONFIG2L_unused=0x0 CONFIG2L~1=OSC,0x7,Oscillator CONFIG2L~2=SOSCSEL,0x18,T1OSC/SOSC Power Selection Bits CONFIG2L~3=CLKOEC,0x20,EC Clock Out Enable Bit CONFIG2L~4=FCMEN,0x40,Fail-Safe Clock Monitor CONFIG2L~5=IESO,0x80,Internal External Oscillator Switch Over Mode CONFIG2L~1~1=0x7,0x7,EC+PLL (CLKO-RA6), USB-EC+PLL CONFIG2L~1~2=0x7,0x6,EC (CLKO-RA6), USB-EC CONFIG2L~1~3=0x7,0x5,HS+PLL, USB-HS+PLL CONFIG2L~1~4=0x7,0x4,HS, USB-HS CONFIG2L~1~5=0x7,0x3,INTOSCPLLO (CLKO-RA6) CONFIG2L~1~6=0x7,0x2,INTOSCPLL CONFIG2L~1~7=0x7,0x1,INTOSCO (CLKO-RA6) CONFIG2L~1~8=0x7,0x0,INTOSC CONFIG2L~2~1=0x18,0x18,High Security Code Protection Enable CONFIG2L~2~2=0x18,0x10,Digital (SCLKI) mode selected CONFIG2L~2~3=0x18,0x8,Low Power T1OSC/SOSC circuit selected CONFIG2L~2~4=0x18,0x0,Reserved CONFIG2L~3~1=0x20,0x20,Enabled CONFIG2L~3~2=0x20,0x0,Disabled CONFIG2L~4~1=0x40,0x0,Disabled CONFIG2L~4~2=0x40,0x40,Enabled CONFIG2L~5~1=0x80,0x0,Disabled CONFIG2L~5~2=0x80,0x80,Enabled CONFIG2H_unused=0x0 CONFIG2H~1=WDTPS,0xf,Watchdog Postscaler CONFIG2H~2=RESERVED,0xf0,RESERVED CONFIG2H~1~1=0xf,0xf,1:32768 CONFIG2H~1~2=0xf,0xe,1:16384 CONFIG2H~1~3=0xf,0xd,1:8192 CONFIG2H~1~4=0xf,0xc,1:4096 CONFIG2H~1~5=0xf,0xb,1:2048 CONFIG2H~1~6=0xf,0xa,1:1024 CONFIG2H~1~7=0xf,0x9,1:512 CONFIG2H~1~8=0xf,0x8,1:256 CONFIG2H~1~9=0xf,0x7,1:128 CONFIG2H~1~10=0xf,0x6,1:64 CONFIG2H~1~11=0xf,0x5,1:32 CONFIG2H~1~12=0xf,0x4,1:16 CONFIG2H~1~13=0xf,0x3,1:8 CONFIG2H~1~14=0xf,0x2,1:4 CONFIG2H~1~15=0xf,0x1,1:2 CONFIG2H~1~16=0xf,0x0,1:1 CONFIG2H~2~1=0xf0,0xf0,RESERVED CONFIG3L_unused=0x0 CONFIG3L~1=DSWDTOSC,0x1,DSWDT Clock Select CONFIG3L~2=RTCOSC,0x2,RTCC Clock Select CONFIG3L~3=DSBOREN,0x4,Deep Sleep BOR CONFIG3L~4=DSWDTEN,0x8,Deep Sleep Watchdog Timer CONFIG3L~5=DSWDTPS,0xf0,Deep Sleep Watchdog Postscaler CONFIG3L~1~1=0x1,0x1,DSWDT uses INTRC CONFIG3L~1~2=0x1,0x0,DSWDT uses T1OSC/T1CKI CONFIG3L~2~1=0x2,0x2,RTCC uses T1OSC/T1CKI CONFIG3L~2~2=0x2,0x0,RTCC uses INTRC CONFIG3L~3~1=0x4,0x4,Enabled CONFIG3L~3~2=0x4,0x0,Disabled CONFIG3L~4~1=0x8,0x8,Enabled CONFIG3L~4~2=0x8,0x0,Disabled CONFIG3L~5~1=0xf0,0xf0,1:2,147,483,648 (25.7 days) CONFIG3L~5~2=0xf0,0xe0,1:536,870,912 (6.4 days) CONFIG3L~5~3=0xf0,0xd0,1:134,217,728 (38.5 hours) CONFIG3L~5~4=0xf0,0xc0,1:33,554,432 (9.6 hours) CONFIG3L~5~5=0xf0,0xb0,1:8,388,608 (2.4 hours) CONFIG3L~5~6=0xf0,0xa0,1:2,097,152 (36 minutes) CONFIG3L~5~7=0xf0,0x90,1:524,288 (9 minutes) CONFIG3L~5~8=0xf0,0x80,1:131,072 (135 seconds) CONFIG3L~5~9=0xf0,0x70,1:32,768 (34 seconds) CONFIG3L~5~10=0xf0,0x60,1:8,192 (8.5 seconds) CONFIG3L~5~11=0xf0,0x50,1:2,048 (2.1 seconds) CONFIG3L~5~12=0xf0,0x40,1:512 (528 ms) CONFIG3L~5~13=0xf0,0x30,1:128 (132 ms) CONFIG3L~5~14=0xf0,0x20,1:32 (33 ms) CONFIG3L~5~15=0xf0,0x10,1:8 (8.3 ms) CONFIG3L~5~16=0xf0,0x0,1:2 (2.1 ms) CONFIG3H_unused=0x0 CONFIG3H~1=IOL1WAY,0x1,IOLOCK One-Way Set Enable bit CONFIG3H~2=ADCSEL,0x2,ADC 10 or 12 Bit Select CONFIG3H~3=PLLSEL,0x4,PLL Selection Bit CONFIG3H~4=MSSP7B_EN,0x8,MSSP address masking CONFIG3H~5=RESERVED,0xf0,RESERVED CONFIG3H~1~1=0x1,0x1,Enabled CONFIG3H~1~2=0x1,0x0,Disabled CONFIG3H~2~1=0x2,0x2,10 - Bit ADC Enabled CONFIG3H~2~2=0x2,0x0,12 - Bit ADC Enabed CONFIG3H~3~1=0x4,0x0,Selects 96MHz PLL CONFIG3H~3~2=0x4,0x4,Selects 4x PLL CONFIG3H~4~1=0x8,0x8,7 Bit address masking mode CONFIG3H~4~2=0x8,0x0,5 Bit address masking mode CONFIG3H~5~1=0xf0,0xf0,RESERVED CONFIG4L_unused=0x0 CONFIG4L~1=WPFP,0x7f,Write/Erase Protect Page Start/End Location CONFIG4L~2=WPCFG,0x80,Write/Erase Protect Configuration Region CONFIG4L~1~1=0x7f,0x0,Write Protect Program Flash Page 0 CONFIG4L~1~2=0x7f,0x1,Write Protect Program Flash Page 1 CONFIG4L~1~3=0x7f,0x2,Write Protect Program Flash Page 2 CONFIG4L~1~4=0x7f,0x3,Write Protect Program Flash Page 3 CONFIG4L~1~5=0x7f,0x4,Write Protect Program Flash Page 4 CONFIG4L~1~6=0x7f,0x5,Write Protect Program Flash Page 5 CONFIG4L~1~7=0x7f,0x6,Write Protect Program Flash Page 6 CONFIG4L~1~8=0x7f,0x7,Write Protect Program Flash Page 7 CONFIG4L~1~9=0x7f,0x8,Write Protect Program Flash Page 8 CONFIG4L~1~10=0x7f,0x9,Write Protect Program Flash Page 9 CONFIG4L~1~11=0x7f,0xa,Write Protect Program Flash Page 10 CONFIG4L~1~12=0x7f,0xb,Write Protect Program Flash Page 11 CONFIG4L~1~13=0x7f,0xc,Write Protect Program Flash Page 12 CONFIG4L~1~14=0x7f,0xd,Write Protect Program Flash Page 13 CONFIG4L~1~15=0x7f,0xe,Write Protect Program Flash Page 14 CONFIG4L~1~16=0x7f,0xf,Write Protect Program Flash Page 15 CONFIG4L~1~17=0x7f,0x10,Write Protect Program Flash Page 16 CONFIG4L~1~18=0x7f,0x11,Write Protect Program Flash Page 17 CONFIG4L~1~19=0x7f,0x12,Write Protect Program Flash Page 18 CONFIG4L~1~20=0x7f,0x13,Write Protect Program Flash Page 19 CONFIG4L~1~21=0x7f,0x14,Write Protect Program Flash Page 20 CONFIG4L~1~22=0x7f,0x15,Write Protect Program Flash Page 21 CONFIG4L~1~23=0x7f,0x16,Write Protect Program Flash Page 22 CONFIG4L~1~24=0x7f,0x17,Write Protect Program Flash Page 23 CONFIG4L~1~25=0x7f,0x18,Write Protect Program Flash Page 24 CONFIG4L~1~26=0x7f,0x19,Write Protect Program Flash Page 25 CONFIG4L~1~27=0x7f,0x1a,Write Protect Program Flash Page 26 CONFIG4L~1~28=0x7f,0x1b,Write Protect Program Flash Page 27 CONFIG4L~1~29=0x7f,0x1c,Write Protect Program Flash Page 28 CONFIG4L~1~30=0x7f,0x1d,Write Protect Program Flash Page 29 CONFIG4L~1~31=0x7f,0x1e,Write Protect Program Flash Page 30 CONFIG4L~1~32=0x7f,0x1f,Write Protect Program Flash Page 31 CONFIG4L~1~33=0x7f,0x20,Write Protect Program Flash Page 32 CONFIG4L~1~34=0x7f,0x21,Write Protect Program Flash Page 33 CONFIG4L~1~35=0x7f,0x22,Write Protect Program Flash Page 34 CONFIG4L~1~36=0x7f,0x23,Write Protect Program Flash Page 35 CONFIG4L~1~37=0x7f,0x24,Write Protect Program Flash Page 36 CONFIG4L~1~38=0x7f,0x25,Write Protect Program Flash Page 37 CONFIG4L~1~39=0x7f,0x26,Write Protect Program Flash Page 38 CONFIG4L~1~40=0x7f,0x27,Write Protect Program Flash Page 39 CONFIG4L~1~41=0x7f,0x28,Write Protect Program Flash Page 40 CONFIG4L~1~42=0x7f,0x29,Write Protect Program Flash Page 41 CONFIG4L~1~43=0x7f,0x2a,Write Protect Program Flash Page 42 CONFIG4L~1~44=0x7f,0x2b,Write Protect Program Flash Page 43 CONFIG4L~1~45=0x7f,0x2c,Write Protect Program Flash Page 44 CONFIG4L~1~46=0x7f,0x2d,Write Protect Program Flash Page 45 CONFIG4L~1~47=0x7f,0x2e,Write Protect Program Flash Page 46 CONFIG4L~1~48=0x7f,0x2f,Write Protect Program Flash Page 47 CONFIG4L~1~49=0x7f,0x30,Write Protect Program Flash Page 48 CONFIG4L~1~50=0x7f,0x31,Write Protect Program Flash Page 49 CONFIG4L~1~51=0x7f,0x32,Write Protect Program Flash Page 50 CONFIG4L~1~52=0x7f,0x33,Write Protect Program Flash Page 51 CONFIG4L~1~53=0x7f,0x34,Write Protect Program Flash Page 52 CONFIG4L~1~54=0x7f,0x35,Write Protect Program Flash Page 53 CONFIG4L~1~55=0x7f,0x36,Write Protect Program Flash Page 54 CONFIG4L~1~56=0x7f,0x37,Write Protect Program Flash Page 55 CONFIG4L~1~57=0x7f,0x38,Write Protect Program Flash Page 56 CONFIG4L~1~58=0x7f,0x39,Write Protect Program Flash Page 57 CONFIG4L~1~59=0x7f,0x3a,Write Protect Program Flash Page 58 CONFIG4L~1~60=0x7f,0x3b,Write Protect Program Flash Page 59 CONFIG4L~1~61=0x7f,0x3c,Write Protect Program Flash Page 60 CONFIG4L~1~62=0x7f,0x3d,Write Protect Program Flash Page 61 CONFIG4L~1~63=0x7f,0x3e,Write Protect Program Flash Page 62 CONFIG4L~1~64=0x7f,0x3f,Write Protect Program Flash Page 63 CONFIG4L~1~65=0x7f,0x40,Write Protect Program Flash Page 64 CONFIG4L~1~66=0x7f,0x41,Write Protect Program Flash Page 65 CONFIG4L~1~67=0x7f,0x42,Write Protect Program Flash Page 66 CONFIG4L~1~68=0x7f,0x43,Write Protect Program Flash Page 67 CONFIG4L~1~69=0x7f,0x44,Write Protect Program Flash Page 68 CONFIG4L~1~70=0x7f,0x45,Write Protect Program Flash Page 69 CONFIG4L~1~71=0x7f,0x46,Write Protect Program Flash Page 70 CONFIG4L~1~72=0x7f,0x47,Write Protect Program Flash Page 71 CONFIG4L~1~73=0x7f,0x48,Write Protect Program Flash Page 72 CONFIG4L~1~74=0x7f,0x49,Write Protect Program Flash Page 73 CONFIG4L~1~75=0x7f,0x4a,Write Protect Program Flash Page 74 CONFIG4L~1~76=0x7f,0x4b,Write Protect Program Flash Page 75 CONFIG4L~1~77=0x7f,0x4c,Write Protect Program Flash Page 76 CONFIG4L~1~78=0x7f,0x4d,Write Protect Program Flash Page 77 CONFIG4L~1~79=0x7f,0x4e,Write Protect Program Flash Page 78 CONFIG4L~1~80=0x7f,0x4f,Write Protect Program Flash Page 79 CONFIG4L~1~81=0x7f,0x50,Write Protect Program Flash Page 80 CONFIG4L~1~82=0x7f,0x51,Write Protect Program Flash Page 81 CONFIG4L~1~83=0x7f,0x52,Write Protect Program Flash Page 82 CONFIG4L~1~84=0x7f,0x53,Write Protect Program Flash Page 83 CONFIG4L~1~85=0x7f,0x54,Write Protect Program Flash Page 84 CONFIG4L~1~86=0x7f,0x55,Write Protect Program Flash Page 85 CONFIG4L~1~87=0x7f,0x56,Write Protect Program Flash Page 86 CONFIG4L~1~88=0x7f,0x57,Write Protect Program Flash Page 87 CONFIG4L~1~89=0x7f,0x58,Write Protect Program Flash Page 88 CONFIG4L~1~90=0x7f,0x59,Write Protect Program Flash Page 89 CONFIG4L~1~91=0x7f,0x5a,Write Protect Program Flash Page 90 CONFIG4L~1~92=0x7f,0x5b,Write Protect Program Flash Page 91 CONFIG4L~1~93=0x7f,0x5c,Write Protect Program Flash Page 92 CONFIG4L~1~94=0x7f,0x5d,Write Protect Program Flash Page 93 CONFIG4L~1~95=0x7f,0x5e,Write Protect Program Flash Page 94 CONFIG4L~1~96=0x7f,0x5f,Write Protect Program Flash Page 95 CONFIG4L~1~97=0x7f,0x60,Write Protect Program Flash Page 96 CONFIG4L~1~98=0x7f,0x61,Write Protect Program Flash Page 97 CONFIG4L~1~99=0x7f,0x62,Write Protect Program Flash Page 98 CONFIG4L~1~100=0x7f,0x63,Write Protect Program Flash Page 99 CONFIG4L~1~101=0x7f,0x64,Write Protect Program Flash Page 100 CONFIG4L~1~102=0x7f,0x65,Write Protect Program Flash Page 101 CONFIG4L~1~103=0x7f,0x66,Write Protect Program Flash Page 102 CONFIG4L~1~104=0x7f,0x67,Write Protect Program Flash Page 103 CONFIG4L~1~105=0x7f,0x68,Write Protect Program Flash Page 104 CONFIG4L~1~106=0x7f,0x69,Write Protect Program Flash Page 105 CONFIG4L~1~107=0x7f,0x6a,Write Protect Program Flash Page 106 CONFIG4L~1~108=0x7f,0x6b,Write Protect Program Flash Page 107 CONFIG4L~1~109=0x7f,0x6c,Write Protect Program Flash Page 108 CONFIG4L~1~110=0x7f,0x6d,Write Protect Program Flash Page 109 CONFIG4L~1~111=0x7f,0x6e,Write Protect Program Flash Page 110 CONFIG4L~1~112=0x7f,0x6f,Write Protect Program Flash Page 111 CONFIG4L~1~113=0x7f,0x70,Write Protect Program Flash Page 112 CONFIG4L~1~114=0x7f,0x71,Write Protect Program Flash Page 113 CONFIG4L~1~115=0x7f,0x72,Write Protect Program Flash Page 114 CONFIG4L~1~116=0x7f,0x73,Write Protect Program Flash Page 115 CONFIG4L~1~117=0x7f,0x74,Write Protect Program Flash Page 116 CONFIG4L~1~118=0x7f,0x75,Write Protect Program Flash Page 117 CONFIG4L~1~119=0x7f,0x76,Write Protect Program Flash Page 118 CONFIG4L~1~120=0x7f,0x77,Write Protect Program Flash Page 119 CONFIG4L~1~121=0x7f,0x78,Write Protect Program Flash Page 120 CONFIG4L~1~122=0x7f,0x79,Write Protect Program Flash Page 121 CONFIG4L~1~123=0x7f,0x7a,Write Protect Program Flash Page 122 CONFIG4L~1~124=0x7f,0x7b,Write Protect Program Flash Page 123 CONFIG4L~1~125=0x7f,0x7c,Write Protect Program Flash Page 124 CONFIG4L~1~126=0x7f,0x7d,Write Protect Program Flash Page 125 CONFIG4L~1~127=0x7f,0x7e,Write Protect Program Flash Page 126 CONFIG4L~1~128=0x7f,0x7f,Write Protect Program Flash Page 127 CONFIG4L~2~1=0x80,0x80,Disabled CONFIG4L~2~2=0x80,0x0,Enabled CONFIG4H_unused=0x0 CONFIG4H~1=WPDIS,0x1,Write Protect Disable bit CONFIG4H~2=WPEND,0x2,Write/Erase Protect Region Select bit (valid when WPDIS = 0) CONFIG4H~3=LS48MHZ,0x8,Low Speed USB mode with 48 MHz system clock bit CONFIG4H~4=RESERVED,0xf0,RESERVED CONFIG4H~1~1=0x1,0x1,Disabled CONFIG4H~1~2=0x1,0x0,Enabled CONFIG4H~2~1=0x2,0x2,Pages WPFP<6:0> to (Configuration Words page) write/erase protected CONFIG4H~2~2=0x2,0x0,Page 0 to WPFP<6:0> erase/write-protected CONFIG4H~3~1=0x8,0x0,System clock at 24 MHz USB CLKEN divide-by is set to 4 CONFIG4H~3~2=0x8,0x8,System clock at 48 MHz USB CLKEN divide-by is set to 8 CONFIG4H~4~1=0xf0,0xf0,RESERVED erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F6313] pgmmem=0x0 ~pgmmem=0x1fff cfgmem=0x300000 ~cfgmem=0x30000d userid=0x200000 ~userid=0x200007 eedata= ~eedata= devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0x1a40 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004=CONFIG3L 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009= 0x30000a= 0x30000b= 0x30000c=CONFIG7L 0x30000d= CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xf,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xc,0xc,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xe,0xa,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xf,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xf,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xf,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xf,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xf,0x5,EC-Port on RA6 CONFIG1H~1~8=0xf,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xf,0x3,0011 EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xf,0x2,HS CONFIG1H~1~11=0xf,0x1,XT CONFIG1H~1~12=0xf,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x8,4.2V CONFIG2L~3~4=0x18,0x0,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1e,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1e,0x1e,1:32768 CONFIG2H~2~2=0x1e,0x1c,1:16384 CONFIG2H~2~3=0x1e,0x1a,1:8192 CONFIG2H~2~4=0x1e,0x18,1:4096 CONFIG2H~2~5=0x1e,0x16,1:2048 CONFIG2H~2~6=0x1e,0x14,1:1024 CONFIG2H~2~7=0x1e,0x12,1:512 CONFIG2H~2~8=0x1e,0x10,1:256 CONFIG2H~2~9=0x1e,0xe,1:128 CONFIG2H~2~10=0x1e,0xc,1:64 CONFIG2H~2~11=0x1e,0xa,1:32 CONFIG2H~2~12=0x1e,0x8,1:16 CONFIG2H~2~13=0x1e,0x6,1:8 CONFIG2H~2~14=0x1e,0x4,1:4 CONFIG2H~2~15=0x1e,0x2,1:2 CONFIG2H~2~16=0x1e,0x0,1:1 CONFIG3L_unused=0x0 CONFIG3L~1=PMODE,0x3,Processor Mode CONFIG3L~2=BW,0x40,Bus Width CONFIG3L~3=WAIT,0x80,External Bus Wait CONFIG3L~1~1=0x3,0x3,Microcontroller CONFIG3L~2~1=0x40,0x40,16-bit external CONFIG3L~2~2=0x40,0x0,8-bit external CONFIG3L~3~1=0x80,0x80,Disabled CONFIG3L~3~2=0x80,0x0,Enabled CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=LPT1OSC,0x4,Low Power Timer1 Osc enable CONFIG3H~3=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RE7 in microcontroller mode CONFIG3H~2~1=0x4,0x4,Enabled CONFIG3H~2~2=0x4,0x0,Disabled CONFIG3H~3~1=0x80,0x80,MCLR Enabled, RG5 Disabled CONFIG3H~3~2=0x80,0x0,MCLR Disabled, RG5 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=ENHCPU,0x40,Extended CPU Enable CONFIG4L~3=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x40,0x40,Enabled CONFIG4L~2~2=0x40,0x0,Disabled CONFIG4L~3~1=0x80,0x80,Disabled CONFIG4L~3~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00000-01FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00000-01FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F6393] pgmmem=0x2000 ~pgmmem=0x1fffff cfgmem=0x300000 ~cfgmem=0x30000d userid=0x200000 ~userid=0x200007 eedata= ~eedata= devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0x1a00 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004=CONFIG3L 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009= 0x30000a= 0x30000b= 0x30000c=CONFIG7L 0x30000d= CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xf,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xc,0xc,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xe,0xa,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xf,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xf,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xf,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xf,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xf,0x5,EC-Port on RA6 CONFIG1H~1~8=0xf,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xf,0x3,0011 EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xf,0x2,HS CONFIG1H~1~11=0xf,0x1,XT CONFIG1H~1~12=0xf,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x8,4.2V CONFIG2L~3~4=0x18,0x0,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1e,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1e,0x1e,1:32768 CONFIG2H~2~2=0x1e,0x1c,1:16384 CONFIG2H~2~3=0x1e,0x1a,1:8192 CONFIG2H~2~4=0x1e,0x18,1:4096 CONFIG2H~2~5=0x1e,0x16,1:2048 CONFIG2H~2~6=0x1e,0x14,1:1024 CONFIG2H~2~7=0x1e,0x12,1:512 CONFIG2H~2~8=0x1e,0x10,1:256 CONFIG2H~2~9=0x1e,0xe,1:128 CONFIG2H~2~10=0x1e,0xc,1:64 CONFIG2H~2~11=0x1e,0xa,1:32 CONFIG2H~2~12=0x1e,0x8,1:16 CONFIG2H~2~13=0x1e,0x6,1:8 CONFIG2H~2~14=0x1e,0x4,1:4 CONFIG2H~2~15=0x1e,0x2,1:2 CONFIG2H~2~16=0x1e,0x0,1:1 CONFIG3L_unused=0x0 CONFIG3L~1=PMODE,0x3,Processor Mode CONFIG3L~2=BW,0x40,Bus Width CONFIG3L~3=WAIT,0x80,External Bus Wait CONFIG3L~1~1=0x3,0x3,Microcontroller CONFIG3L~1~2=0x3,0x2,Microprocessor CONFIG3L~1~3=0x3,0x1,Microprocessor w/Boot CONFIG3L~1~4=0x3,0x0,Ext Microcontroller CONFIG3L~2~1=0x40,0x40,16-bit external CONFIG3L~2~2=0x40,0x0,8-bit external CONFIG3L~3~1=0x80,0x80,Disabled CONFIG3L~3~2=0x80,0x0,Enabled CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=LPT1OSC,0x4,Low Power Timer1 Osc enable CONFIG3H~3=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RE7 CONFIG3H~2~1=0x4,0x4,Enabled CONFIG3H~2~2=0x4,0x0,Disabled CONFIG3H~3~1=0x80,0x80,MCLR Enabled, RG5 Disabled CONFIG3H~3~2=0x80,0x0,MCLR Disabled, RG5 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=XINST,0x40,Extended Instruction Set Enable bit CONFIG4L~3=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x40,0x40,Enabled CONFIG4L~2~2=0x40,0x0,Disabled CONFIG4L~3~1=0x80,0x80,Disabled CONFIG4L~3~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00000-01FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00000-01FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F6413] pgmmem=0x0 ~pgmmem=0x3fff cfgmem=0x300000 ~cfgmem=0x30000d userid=0x200000 ~userid=0x200007 eedata= ~eedata= devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0xe40 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004=CONFIG3L 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009= 0x30000a= 0x30000b= 0x30000c=CONFIG7L 0x30000d= CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xf,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xc,0xc,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xe,0xa,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xf,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xf,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xf,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xf,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xf,0x5,EC-Port on RA6 CONFIG1H~1~8=0xf,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xf,0x3,0011 EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xf,0x2,HS CONFIG1H~1~11=0xf,0x1,XT CONFIG1H~1~12=0xf,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x8,4.2V CONFIG2L~3~4=0x18,0x0,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1e,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1e,0x1e,1:32768 CONFIG2H~2~2=0x1e,0x1c,1:16384 CONFIG2H~2~3=0x1e,0x1a,1:8192 CONFIG2H~2~4=0x1e,0x18,1:4096 CONFIG2H~2~5=0x1e,0x16,1:2048 CONFIG2H~2~6=0x1e,0x14,1:1024 CONFIG2H~2~7=0x1e,0x12,1:512 CONFIG2H~2~8=0x1e,0x10,1:256 CONFIG2H~2~9=0x1e,0xe,1:128 CONFIG2H~2~10=0x1e,0xc,1:64 CONFIG2H~2~11=0x1e,0xa,1:32 CONFIG2H~2~12=0x1e,0x8,1:16 CONFIG2H~2~13=0x1e,0x6,1:8 CONFIG2H~2~14=0x1e,0x4,1:4 CONFIG2H~2~15=0x1e,0x2,1:2 CONFIG2H~2~16=0x1e,0x0,1:1 CONFIG3L_unused=0x0 CONFIG3L~1=PMODE,0x3,Processor Mode CONFIG3L~2=BW,0x40,Bus Width CONFIG3L~3=WAIT,0x80,External Bus Wait CONFIG3L~1~1=0x3,0x3,Microcontroller CONFIG3L~2~1=0x40,0x40,16-bit external CONFIG3L~2~2=0x40,0x0,8-bit external CONFIG3L~3~1=0x80,0x80,Disabled CONFIG3L~3~2=0x80,0x0,Enabled CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=LPT1OSC,0x4,Low Power Timer1 Osc enable CONFIG3H~3=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RE7 in microcontroller mode CONFIG3H~2~1=0x4,0x4,Enabled CONFIG3H~2~2=0x4,0x0,Disabled CONFIG3H~3~1=0x80,0x80,MCLR Enabled, RG5 Disabled CONFIG3H~3~2=0x80,0x0,MCLR Disabled, RG5 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=ENHCPU,0x40,Extended CPU Enable CONFIG4L~3=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x40,0x40,Enabled CONFIG4L~2~2=0x40,0x0,Disabled CONFIG4L~3~1=0x80,0x80,Disabled CONFIG4L~3~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00000-03FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00000-03FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F6493] pgmmem=0x2000 ~pgmmem=0x1fffff cfgmem=0x300000 ~cfgmem=0x30000d userid=0x200000 ~userid=0x200007 eedata= ~eedata= devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0xe00 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004=CONFIG3L 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009= 0x30000a= 0x30000b= 0x30000c=CONFIG7L 0x30000d= CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xf,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xc,0xc,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xe,0xa,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xf,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xf,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xf,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xf,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xf,0x5,EC-Port on RA6 CONFIG1H~1~8=0xf,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xf,0x3,0011 EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xf,0x2,HS CONFIG1H~1~11=0xf,0x1,XT CONFIG1H~1~12=0xf,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x8,4.2V CONFIG2L~3~4=0x18,0x0,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1e,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1e,0x1e,1:32768 CONFIG2H~2~2=0x1e,0x1c,1:16384 CONFIG2H~2~3=0x1e,0x1a,1:8192 CONFIG2H~2~4=0x1e,0x18,1:4096 CONFIG2H~2~5=0x1e,0x16,1:2048 CONFIG2H~2~6=0x1e,0x14,1:1024 CONFIG2H~2~7=0x1e,0x12,1:512 CONFIG2H~2~8=0x1e,0x10,1:256 CONFIG2H~2~9=0x1e,0xe,1:128 CONFIG2H~2~10=0x1e,0xc,1:64 CONFIG2H~2~11=0x1e,0xa,1:32 CONFIG2H~2~12=0x1e,0x8,1:16 CONFIG2H~2~13=0x1e,0x6,1:8 CONFIG2H~2~14=0x1e,0x4,1:4 CONFIG2H~2~15=0x1e,0x2,1:2 CONFIG2H~2~16=0x1e,0x0,1:1 CONFIG3L_unused=0x0 CONFIG3L~1=PMODE,0x3,Processor Mode CONFIG3L~2=BW,0x40,Bus Width CONFIG3L~3=WAIT,0x80,External Bus Wait CONFIG3L~1~1=0x3,0x3,Microcontroller CONFIG3L~1~2=0x3,0x2,Microprocessor CONFIG3L~1~3=0x3,0x1,Microprocessor w/Boot CONFIG3L~1~4=0x3,0x0,Ext Microcontroller CONFIG3L~2~1=0x40,0x40,16-bit external CONFIG3L~2~2=0x40,0x0,8-bit external CONFIG3L~3~1=0x80,0x80,Disabled CONFIG3L~3~2=0x80,0x0,Enabled CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=LPT1OSC,0x4,Low Power Timer1 Osc enable CONFIG3H~3=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RE7 CONFIG3H~2~1=0x4,0x4,Enabled CONFIG3H~2~2=0x4,0x0,Disabled CONFIG3H~3~1=0x80,0x80,MCLR Enabled, RG5 Disabled CONFIG3H~3~2=0x80,0x0,MCLR Disabled, RG5 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=XINST,0x40,Extended Instruction Set Enable bit CONFIG4L~3=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x40,0x40,Enabled CONFIG4L~2~2=0x40,0x0,Disabled CONFIG4L~3~1=0x80,0x80,Disabled CONFIG4L~3~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00000-03FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00000-03FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F65K22] pgmmem=0x0 ~pgmmem=0x7fff cfgmem=0x300000 ~cfgmem=0x30000d userid=0x200000 ~userid=0x200007 eedata=0x0 ~eedata=0x3ff devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0x5300 configslots=14 0x300000=CONFIG1L 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004=CONFIG3L 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000a=CONFIG6L 0x30000b=CONFIG6H 0x30000c=CONFIG7L 0x30000d=CONFIG7H CONFIG1L_unused=0x0 CONFIG1L~1=RETEN,0x1,VREG Sleep Enable bit CONFIG1L~2=SOSCEL,0x18,SOSC Power Selection and mode Configuration bits CONFIG1L~3=XINST,0x40,Extended Instruction Set CONFIG1L~1~1=0x1,0x1,Enabled CONFIG1L~1~2=0x1,0x0,Disabled CONFIG1L~2~1=0x18,0x18,High Power SOSC circuit selected CONFIG1L~2~2=0x18,0x8,Low Power SOSC circuit selected CONFIG1L~2~3=0x18,0x10,Digital (SCLKI) mode CONFIG1L~3~1=0x40,0x40,Enabled CONFIG1L~3~2=0x40,0x0,Disabled CONFIG1H_unused=0x0 CONFIG1H~1=FOSC,0xf,Oscillator CONFIG1H~2=PLLCFG,0x10,PLL x4 Enable bit CONFIG1H~3=PRCKEN,0x20,Primary Clock Enable bit CONFIG1H~4=FCMEN,0x40,Fail-Safe Clock Monitor CONFIG1H~5=IESO,0x80,Internal External Oscillator Switch Over Mode CONFIG1H~1~1=0xf,0xd,EC oscillator (Low power, DC - 160 kHz) CONFIG1H~1~2=0xf,0xc,EC oscillator, CLKOUT function on OSC2 (Low power, DC - 160 kHz) CONFIG1H~1~3=0xf,0xb,EC oscillator (Medium power, 160 kHz - 4 MHz) CONFIG1H~1~4=0xf,0xa,EC oscillator, CLKOUT function on OSC2 (Medium power, 160 kHz - 4 MHz) CONFIG1H~1~5=0xf,0x9,Internal RC oscillator, CLKOUT function on OSC2 CONFIG1H~1~6=0xf,0x8,Internal RC oscillator CONFIG1H~1~7=0xf,0x5,EC oscillator (High power, 16 MHz - 25 MHz) CONFIG1H~1~8=0xf,0x4,EC oscillator, CLKOUT function on OSC2 (High power, 16 MHz - 25 MHz) CONFIG1H~1~9=0xf,0x3,HS oscillator (Medium power, 4 MHz - 16 MHz) CONFIG1H~1~10=0xf,0x2,HS oscillator (High power, 16 MHz - 25 MHz) CONFIG1H~1~11=0xf,0x1,XT oscillator CONFIG1H~1~12=0xf,0x0,LP oscillator CONFIG1H~1~13=0x7,0x7,External RC oscillator CONFIG1H~1~14=0x7,0x6,External RC oscillator, CLKOUT function on OSC2 CONFIG1H~2~1=0x10,0x10,Enabled CONFIG1H~2~2=0x10,0x0,Disabled CONFIG1H~3~1=0x20,0x0,Disabled CONFIG1H~3~2=0x20,0x20,Enabled CONFIG1H~4~1=0x40,0x0,Disabled CONFIG1H~4~2=0x40,0x40,Enabled CONFIG1H~5~1=0x80,0x0,Disabled CONFIG1H~5~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PWRTEN,0x1,Power Up Timer CONFIG2L~2=BOREN,0x6,Brown Out Detect CONFIG2L~3=BORV,0x18,Brown-out Reset Voltage bits CONFIG2L~4=BORPWR,0x60,BORMV Power level CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active, disabled in SLEEP, SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,1.8V CONFIG2L~3~2=0x18,0x10,2.0V CONFIG2L~3~3=0x18,0x8,2.7V CONFIG2L~3~4=0x18,0x0,3.0V CONFIG2L~4~1=0x60,0x60,ZPBORMV instead of BORMV is selected CONFIG2L~4~2=0x60,0x40,BORMV set to high power level CONFIG2L~4~3=0x60,0x20,BORMV set to medium power level CONFIG2L~4~4=0x60,0x0,BORMV set to low power level CONFIG2H_unused=0x0 CONFIG2H~1=WDTEN,0x3,Watchdog Timer CONFIG2H~2=WDTPS,0x7c,Watchdog Postscaler CONFIG2H~1~1=0x3,0x3,Enabled in hardware, SWDTEN disabled CONFIG2H~1~2=0x3,0x2,Enabled while active, disabled in SLEEP, SWDTEN disabled CONFIG2H~1~3=0x3,0x1,Controlled with SWDTEN bit CONFIG2H~1~4=0x3,0x0,Disabled in hardware, SWDTEN disabled CONFIG2H~2~1=0x7c,0x7c,1:1048576 CONFIG2H~2~2=0x7c,0x4c,1:524288 CONFIG2H~2~3=0x7c,0x48,1:262144 CONFIG2H~2~4=0x7c,0x44,1:131072 CONFIG2H~2~5=0x7c,0x40,1:65536 CONFIG2H~2~6=0x7c,0x3c,1:32768 CONFIG2H~2~7=0x7c,0x38,1:16384 CONFIG2H~2~8=0x7c,0x34,1:8192 CONFIG2H~2~9=0x7c,0x30,1:4096 CONFIG2H~2~10=0x7c,0x2c,1:2048 CONFIG2H~2~11=0x7c,0x28,1:1024 CONFIG2H~2~12=0x7c,0x24,1:512 CONFIG2H~2~13=0x7c,0x20,1:256 CONFIG2H~2~14=0x7c,0x1c,1:128 CONFIG2H~2~15=0x7c,0x18,1:64 CONFIG2H~2~16=0x7c,0x14,1:32 CONFIG2H~2~17=0x7c,0x10,1:16 CONFIG2H~2~18=0x7c,0xc,1:8 CONFIG2H~2~19=0x7c,0x8,1:4 CONFIG2H~2~20=0x7c,0x4,1:2 CONFIG2H~2~21=0x7c,0x0,1:1 CONFIG3L_unused=0x0 CONFIG3L~1=RTCOSC,0x1,RTCC Clock Select CONFIG3L~1~1=0x1,0x1,RTCC uses T1OSC/T1CKI CONFIG3L~1~2=0x1,0x0,RTCC uses INTRC CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MX,0x1,CCP2 Mux CONFIG3H~2=MSSPMSK,0x8,MSSP address masking CONFIG3H~3=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RE7-Microcontroller Mode/RB3-All other modes CONFIG3H~2~1=0x8,0x8,7 Bit address masking mode CONFIG3H~2~2=0x8,0x0,5 bit address masking mode CONFIG3H~3~1=0x80,0x80,MCLR Enabled, RG5 Disabled CONFIG3H~3~2=0x80,0x0,MCLR Disabled, RG5 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVREN,0x1,Stack Overflow Reset CONFIG4L~2=BBSIZ0,0x10,Boot Block Size CONFIG4L~3=DEBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x10,0x10,2K word Boot Block size CONFIG4L~2~2=0x10,0x0,1K word Boot Block size CONFIG4L~3~1=0x80,0x80,Disabled CONFIG4L~3~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP0,0x1,Code Protect 00800-017FF CONFIG5L~2=CP1,0x2,Code Protect 01800-03FFF CONFIG5L~3=CP2,0x4,Code Protect 04000-05FFF CONFIG5L~4=CP3,0x8,Code Protect 06000-07FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x0,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x0,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x0,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x0,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPB,0x40,Code Protect Boot CONFIG5H~2=CPD,0x80,Data EE Read Protect CONFIG5H~1~1=0x40,0x40,Disabled CONFIG5H~1~2=0x40,0x0,Enabled CONFIG5H~2~1=0x80,0x80,Disabled CONFIG5H~2~2=0x80,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT0,0x1,Table Write Protect 00800-017FF CONFIG6L~2=WRT1,0x2,Table Write Protect 01800-03FFF CONFIG6L~3=WRT2,0x4,Table Write Protect 04000-05FFF CONFIG6L~4=WRT3,0x8,Table Write Protect 06000-07FFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x0,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x0,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x0,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x0,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTC,0x20,Config. Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTD,0x80,Data EE Write Protect CONFIG6H~1~1=0x20,0x20,Disabled CONFIG6H~1~2=0x20,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x80,0x80,Disabled CONFIG6H~3~2=0x80,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBRT0,0x1,Table Read Protect 00800-017FF CONFIG7L~2=EBRT1,0x2,Table Read Protect 01800-03FFF CONFIG7L~3=EBRT2,0x4,Table Read Protect 04000-05FFF CONFIG7L~4=EBRT3,0x8,Table Read Protect 06000-07FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x0,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x0,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x0,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x0,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBRTB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F65K90] pgmmem=0x0 ~pgmmem=0x7fff cfgmem=0x300000 ~cfgmem=0x30000d userid=0x200000 ~userid=0x200007 eedata=0x0 ~eedata=0x3ff devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0x5240 configslots=14 0x300000=CONFIG1L 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004=CONFIG3L 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000a=CONFIG6L 0x30000b=CONFIG6H 0x30000c=CONFIG7L 0x30000d=CONFIG7H CONFIG1L_unused=0x0 CONFIG1L~1=RETEN,0x1,VREG Sleep Enable bit CONFIG1L~2=SOSCEL,0x18,SOSC Power Selection and mode Configuration bits CONFIG1L~3=XINST,0x40,Extended Instruction Set CONFIG1L~1~1=0x1,0x1,Enabled CONFIG1L~1~2=0x1,0x0,Disabled CONFIG1L~2~1=0x18,0x18,High Power SOSC circuit selected CONFIG1L~2~2=0x18,0x8,Low Power SOSC circuit selected CONFIG1L~2~3=0x18,0x10,Digital (SCLKI) mode CONFIG1L~3~1=0x40,0x40,Enabled CONFIG1L~3~2=0x40,0x0,Disabled CONFIG1H_unused=0x0 CONFIG1H~1=FOSC,0xf,Oscillator CONFIG1H~2=PLLCFG,0x10,PLL x4 Enable bit CONFIG1H~3=PRCKEN,0x20,Primary Clock Enable bit CONFIG1H~4=FCMEN,0x40,Fail-Safe Clock Monitor CONFIG1H~5=IESO,0x80,Internal External Oscillator Switch Over Mode CONFIG1H~1~1=0x7,0x7,External RC oscillator CONFIG1H~1~2=0x7,0x6,External RC oscillator, CLKOUT function on OSC2 CONFIG1H~1~3=0xf,0xd,EC oscillator (Low power, DC - 160 kHz) CONFIG1H~1~4=0xf,0xc,EC oscillator, CLKOUT function on OSC2 (Low power, DC - 160 kHz) CONFIG1H~1~5=0xf,0xb,EC oscillator (Medium power, 160 kHz - 4 MHz) CONFIG1H~1~6=0xf,0xa,EC oscillator, CLKOUT function on OSC2 (Medium power, 160 kHz - 4 MHz) CONFIG1H~1~7=0xf,0x9,Internal RC oscillator, CLKOUT function on OSC2 CONFIG1H~1~8=0xf,0x8,Internal RC oscillator CONFIG1H~1~9=0xf,0x5,EC oscillator (High power, 16 MHz - 25 MHz) CONFIG1H~1~10=0xf,0x4,EC oscillator, CLKOUT function on OSC2 (High power, 16 MHz - 25 MHz) CONFIG1H~1~11=0xf,0x3,HS oscillator (Medium power, 4 MHz - 16 MHz) CONFIG1H~1~12=0xf,0x2,HS oscillator (High power, 16 MHz - 25 MHz) CONFIG1H~1~13=0xf,0x1,XT oscillator CONFIG1H~1~14=0xf,0x0,LP oscillator CONFIG1H~2~1=0x10,0x10,Enabled CONFIG1H~2~2=0x10,0x0,Disabled CONFIG1H~3~1=0x20,0x0,Disabled CONFIG1H~3~2=0x20,0x20,Enabled CONFIG1H~4~1=0x40,0x0,Disabled CONFIG1H~4~2=0x40,0x40,Enabled CONFIG1H~5~1=0x80,0x0,Disabled CONFIG1H~5~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PWRTEN,0x1,Power Up Timer CONFIG2L~2=BOREN,0x6,Brown Out Detect CONFIG2L~3=BORV,0x18,Brown-out Reset Voltage bits CONFIG2L~4=BORPWR,0x60,BORMV Power level CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active, disabled in SLEEP, SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,1.8V CONFIG2L~3~2=0x18,0x10,2.0V CONFIG2L~3~3=0x18,0x8,2.7V CONFIG2L~3~4=0x18,0x0,3.0V CONFIG2L~4~1=0x60,0x60,ZPBORMV instead of BORMV is selected CONFIG2L~4~2=0x60,0x40,BORMV set to high power level CONFIG2L~4~3=0x60,0x20,BORMV set to medium power level CONFIG2L~4~4=0x60,0x0,BORMV set to low power level CONFIG2H_unused=0x0 CONFIG2H~1=WDTEN,0x3,Watchdog Timer CONFIG2H~2=WDTPS,0x7c,Watchdog Postscaler CONFIG2H~1~1=0x3,0x3,Enabled in hardware, SWDTEN disabled CONFIG2H~1~2=0x3,0x2,Enabled while active, disabled in SLEEP, SWDTEN disabled CONFIG2H~1~3=0x3,0x1,Controlled with SWDTEN bit CONFIG2H~1~4=0x3,0x0,Disabled in hardware, SWDTEN disabled CONFIG2H~2~1=0x7c,0x7c,1:1048576 CONFIG2H~2~2=0x7c,0x4c,1:524288 CONFIG2H~2~3=0x7c,0x48,1:262144 CONFIG2H~2~4=0x7c,0x44,1:131072 CONFIG2H~2~5=0x7c,0x40,1:65536 CONFIG2H~2~6=0x7c,0x3c,1:32768 CONFIG2H~2~7=0x7c,0x38,1:16384 CONFIG2H~2~8=0x7c,0x34,1:8192 CONFIG2H~2~9=0x7c,0x30,1:4096 CONFIG2H~2~10=0x7c,0x2c,1:2048 CONFIG2H~2~11=0x7c,0x28,1:1024 CONFIG2H~2~12=0x7c,0x24,1:512 CONFIG2H~2~13=0x7c,0x20,1:256 CONFIG2H~2~14=0x7c,0x1c,1:128 CONFIG2H~2~15=0x7c,0x18,1:64 CONFIG2H~2~16=0x7c,0x14,1:32 CONFIG2H~2~17=0x7c,0x10,1:16 CONFIG2H~2~18=0x7c,0xc,1:8 CONFIG2H~2~19=0x7c,0x8,1:4 CONFIG2H~2~20=0x7c,0x4,1:2 CONFIG2H~2~21=0x7c,0x0,1:1 CONFIG3L_unused=0x0 CONFIG3L~1=RTCOSC,0x1,RTCC Clock Select CONFIG3L~1~1=0x1,0x1,RTCC uses T1OSC/T1CKI CONFIG3L~1~2=0x1,0x0,RTCC uses INTRC CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MX,0x1,CCP2 Mux CONFIG3H~2=MSSPMSK,0x8,MSSP address masking CONFIG3H~3=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RE7-Microcontroller Mode/RB3-All other modes CONFIG3H~2~1=0x8,0x8,7 Bit address masking mode CONFIG3H~2~2=0x8,0x0,5 bit address masking mode CONFIG3H~3~1=0x80,0x80,MCLR Enabled, RG5 Disabled CONFIG3H~3~2=0x80,0x0,MCLR Disabled, RG5 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVREN,0x1,Stack Overflow Reset CONFIG4L~2=BBSIZ0,0x10,Boot Block Size CONFIG4L~3=DEBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x10,0x10,2K word Boot Block size CONFIG4L~2~2=0x10,0x0,1K word Boot Block size CONFIG4L~3~1=0x80,0x80,Disabled CONFIG4L~3~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP0,0x1,Code Protect 00800-017FF CONFIG5L~2=CP1,0x2,Code Protect 01800-03FFF CONFIG5L~3=CP2,0x4,Code Protect 04000-05FFF CONFIG5L~4=CP3,0x8,Code Protect 06000-07FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x0,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x0,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x0,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x0,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPB,0x40,Code Protect Boot CONFIG5H~2=CPD,0x80,Data EE Read Protect CONFIG5H~1~1=0x40,0x40,Disabled CONFIG5H~1~2=0x40,0x0,Enabled CONFIG5H~2~1=0x80,0x80,Disabled CONFIG5H~2~2=0x80,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT0,0x1,Table Write Protect 00800-017FF CONFIG6L~2=WRT1,0x2,Table Write Protect 01800-03FFF CONFIG6L~3=WRT2,0x4,Table Write Protect 04000-05FFF CONFIG6L~4=WRT3,0x8,Table Write Protect 06000-07FFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x0,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x0,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x0,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x0,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTC,0x20,Config. Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTD,0x80,Data EE Write Protect CONFIG6H~1~1=0x20,0x20,Disabled CONFIG6H~1~2=0x20,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x80,0x80,Disabled CONFIG6H~3~2=0x80,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBRT0,0x1,Table Read Protect 00800-017FF CONFIG7L~2=EBRT1,0x2,Table Read Protect 01800-03FFF CONFIG7L~3=EBRT2,0x4,Table Read Protect 04000-05FFF CONFIG7L~4=EBRT3,0x8,Table Read Protect 06000-07FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x0,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x0,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x0,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x0,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBRTB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F6628] pgmmem=0x0 ~pgmmem=0x17fff cfgmem=0x300000 ~cfgmem=0x30000d userid=0x200000 ~userid=0x200007 eedata=0x0 ~eedata=0x3ff devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0x49c0 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000a=CONFIG6L 0x30000b=CONFIG6H 0x30000c=CONFIG7L 0x30000d=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xf,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xc,0xc,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xe,0xa,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xf,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xf,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xf,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xf,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xf,0x5,EC-Port on RA6 CONFIG1H~1~8=0xf,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xf,0x3,0011 EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xf,0x2,HS CONFIG1H~1~11=0xf,0x1,XT CONFIG1H~1~12=0xf,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x8,4.2V CONFIG2L~3~4=0x18,0x0,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1e,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1e,0x1e,1:32768 CONFIG2H~2~2=0x1e,0x1c,1:16384 CONFIG2H~2~3=0x1e,0x1a,1:8192 CONFIG2H~2~4=0x1e,0x18,1:4096 CONFIG2H~2~5=0x1e,0x16,1:2048 CONFIG2H~2~6=0x1e,0x14,1:1024 CONFIG2H~2~7=0x1e,0x12,1:512 CONFIG2H~2~8=0x1e,0x10,1:256 CONFIG2H~2~9=0x1e,0xe,1:128 CONFIG2H~2~10=0x1e,0xc,1:64 CONFIG2H~2~11=0x1e,0xa,1:32 CONFIG2H~2~12=0x1e,0x8,1:16 CONFIG2H~2~13=0x1e,0x6,1:8 CONFIG2H~2~14=0x1e,0x4,1:4 CONFIG2H~2~15=0x1e,0x2,1:2 CONFIG2H~2~16=0x1e,0x0,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=LPT1OSC,0x4,Low Power Timer1 Osc enable CONFIG3H~3=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,CCP2 muxed with RC1 CONFIG3H~1~2=0x1,0x0,CCP2 muxed with RE7 CONFIG3H~2~1=0x4,0x4,Enabled CONFIG3H~2~2=0x4,0x0,Disabled CONFIG3H~3~1=0x80,0x80,MCLR Enabled,RG5 Disabled CONFIG3H~3~2=0x80,0x0,MCLR Disabled, RG5 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=BBSIZ,0x30,Boot Block Size CONFIG4L~4=XINST,0x40,Extended Instruction Set Enable bit CONFIG4L~5=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x20,0x20,4K Words (8 Kbytes) CONFIG4L~3~2=0x30,0x10,2K Words (4 Kbytes) CONFIG4L~3~3=0x30,0x0,1K Words (2 Kbytes) CONFIG4L~4~1=0x40,0x40,Enabled CONFIG4L~4~2=0x40,0x0,Disabled CONFIG4L~5~1=0x80,0x80,Disabled CONFIG4L~5~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-03FFF CONFIG5L~2=CP_1,0x2,Code Protect 04000-07FFF CONFIG5L~3=CP_2,0x4,Code Protect 08000-0BFFF CONFIG5L~4=CP_3,0x8,Code Protect 0C000-0FFFF CONFIG5L~5=CP_4,0x10,Code Protect 10000-13FFF CONFIG5L~6=CP_5,0x20,Code Protect 14000-17FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x0,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x0,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x0,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x0,Enabled CONFIG5L~5~1=0x10,0x10,Disabled CONFIG5L~5~2=0x10,0x0,Enabled CONFIG5L~6~1=0x20,0x20,Disabled CONFIG5L~6~2=0x20,0x0,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPB,0x40,Code Protect Boot CONFIG5H~2=CPD,0x80,Data EE Read Protect CONFIG5H~1~1=0x40,0x40,Disabled CONFIG5H~1~2=0x40,0x0,Enabled CONFIG5H~2~1=0x80,0x80,Disabled CONFIG5H~2~2=0x80,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-03FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 04000-07FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 08000-0BFFF CONFIG6L~4=WRT_3,0x8,Table Write Protect 0C000-0FFFF CONFIG6L~5=WRT_4,0x10,Table Write Protect 10000-13FFF CONFIG6L~6=WRT_5,0x20,Table Write Protect 14000-17FFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x0,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x0,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x0,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x0,Enabled CONFIG6L~5~1=0x10,0x10,Disabled CONFIG6L~5~2=0x10,0x0,Enabled CONFIG6L~6~1=0x20,0x20,Disabled CONFIG6L~6~2=0x20,0x0,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTC,0x20,Config. Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTD,0x80,Data EE Write Protect CONFIG6H~1~1=0x20,0x20,Disabled CONFIG6H~1~2=0x20,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x80,0x80,Disabled CONFIG6H~3~2=0x80,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-03FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 04000-07FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 08000-0BFFF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 0C000-0FFFF CONFIG7L~5=EBTR_4,0x10,Table Read Protect 10000-13FFF CONFIG7L~6=EBTR_5,0x20,Table Read Protect 14000-17FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x0,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x0,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x0,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x0,Enabled CONFIG7L~5~1=0x10,0x10,Disabled CONFIG7L~5~2=0x10,0x0,Enabled CONFIG7L~6~1=0x20,0x20,Disabled CONFIG7L~6~2=0x20,0x0,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F66J90] pgmmem=0x20000 ~pgmmem=0x1fffff cfgmem=0xfff8 ~cfgmem=0xffff userid= ~userid= eedata= ~eedata= devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0x5000 configslots=8 0xfff8=CONFIG1L 0xfff9=CONFIG1H 0xfffa=CONFIG2L 0xfffb=CONFIG2H 0xfffc=CONFIG3L 0xfffd=CONFIG3H 0xfffe= 0xffff= CONFIG1L_unused=0x0 CONFIG1L~1=WDTEN,0x1,Watchdog Timer CONFIG1L~2=STVREN,0x20,Stack Overflow Reset CONFIG1L~3=XINST,0x40,Extended Instruction Set Enable bit CONFIG1L~4=DEBUG,0x80,Background Debugger Enable bit CONFIG1L~1~1=0x1,0x1,Enabled CONFIG1L~1~2=0x1,0x0,Disabled CONFIG1L~2~1=0x20,0x20,Enabled CONFIG1L~2~2=0x20,0x0,Disabled CONFIG1L~3~1=0x40,0x40,Enabled CONFIG1L~3~2=0x40,0x0,Disabled CONFIG1L~4~1=0x80,0x80,Disabled CONFIG1L~4~2=0x80,0x0,Enabled CONFIG1H_unused=0x0 CONFIG1H~1=CP0,0x4,Code Protect CONFIG1H~2=SIGN,0x8,Config Word Signature Bit CONFIG1H~3=RESERVED,0xf0,RESERVED CONFIG1H~1~1=0x4,0x4,Disabled CONFIG1H~1~2=0x4,0x0,Enabled CONFIG1H~2~1=0x8,0x8,Bulk erase of memory not conducated CONFIG1H~2~2=0x8,0x0,Bulk erase of memory area complete CONFIG1H~3~1=0xf0,0xf0,RESERVED CONFIG2L_unused=0x0 CONFIG2L~1=OSC,0x7,Oscillator Selection bits CONFIG2L~2=T1DIG,0x8,Secondary Clock Source T1OSCEN Enforcement CONFIG2L~3=LPT1OSC,0x10,Low-Power Timer1 Oscillator Enable bit CONFIG2L~4=FCMEN,0x40,Fail-Safe Clock Monitor Enable bit CONFIG2L~5=IESO,0x80,Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit CONFIG2L~1~1=0x7,0x7,EC Oscillator with PLL CONFIG2L~1~2=0x7,0x6,EC Oscillator with clock out on RA6 CONFIG2L~1~3=0x7,0x5,HS oscillator, PLL enabled CONFIG2L~1~4=0x7,0x4,HS oscillator CONFIG2L~1~5=0x7,0x3,INTOSC with PLL enabled, CLKOUT on RA6 and port function on RA7 CONFIG2L~1~6=0x7,0x2,Internal oscillator, CLKOUT on RA6 and port function on RA7 CONFIG2L~1~7=0x7,0x1,INTOSC with PLL enabled, port function on RA6 and RA7 CONFIG2L~1~8=0x7,0x0,Internal oscillator, port function on RA6 and RA7 CONFIG2L~2~1=0x8,0x8,Enabled CONFIG2L~2~2=0x8,0x0,Disabled CONFIG2L~3~1=0x10,0x0,Enabled CONFIG2L~3~2=0x10,0x10,Disabled CONFIG2L~4~1=0x40,0x0,Disabled CONFIG2L~4~2=0x40,0x40,Enabled CONFIG2L~5~1=0x80,0x0,Disabled CONFIG2L~5~2=0x80,0x80,Enabled CONFIG2H_unused=0x0 CONFIG2H~1=WDTPS,0xf,Watchdog Timer Postscaler Select bits CONFIG2H~2=RESERVED,0xf0,RESERVED CONFIG2H~1~1=0xf,0xf,1:32768 CONFIG2H~1~2=0xf,0xe,1:16384 CONFIG2H~1~3=0xf,0xd,1:8192 CONFIG2H~1~4=0xf,0xc,1:4096 CONFIG2H~1~5=0xf,0xb,1:2048 CONFIG2H~1~6=0xf,0xa,1:1024 CONFIG2H~1~7=0xf,0x9,1:512 CONFIG2H~1~8=0xf,0x8,1:256 CONFIG2H~1~9=0xf,0x7,1:128 CONFIG2H~1~10=0xf,0x6,1:64 CONFIG2H~1~11=0xf,0x5,1:32 CONFIG2H~1~12=0xf,0x4,1:16 CONFIG2H~1~13=0xf,0x3,1:8 CONFIG2H~1~14=0xf,0x2,1:4 CONFIG2H~1~15=0xf,0x1,1:2 CONFIG2H~1~16=0xf,0x0,1:1 CONFIG2H~2~1=0xf0,0xf0,RESERVED CONFIG3L_unused=0x0 CONFIG3L~1=RTCSOSC,0x2,RTCC Reference Clock Select bit CONFIG3L~1~1=0x2,0x2,RTCC uses T1OSC/T1CKI as reference clock CONFIG3L~1~2=0x2,0x0,RTCC uses INTOSC/INTRC as reference clock CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MX,0x1,CCP2 MUX CONFIG3H~2=RESERVED,0xf0,RESERVED CONFIG3H~1~1=0x1,0x0,RE7 / RB3 CONFIG3H~1~2=0x1,0x1,RC1 CONFIG3H~2~1=0xf0,0xf0,RESERVED erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F66J93] pgmmem=0x20000 ~pgmmem=0x1fffff cfgmem=0xfff8 ~cfgmem=0xffff userid= ~userid= eedata= ~eedata= devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0x5040 configslots=8 0xfff8=CONFIG1L 0xfff9=CONFIG1H 0xfffa=CONFIG2L 0xfffb=CONFIG2H 0xfffc=CONFIG3L 0xfffd=CONFIG3H 0xfffe= 0xffff= CONFIG1L_unused=0x0 CONFIG1L~1=WDTEN,0x1,Watchdog Timer CONFIG1L~2=STVREN,0x20,Stack Overflow Reset CONFIG1L~3=XINST,0x40,Extended Instruction Set Enable bit CONFIG1L~4=DEBUG,0x80,Background Debugger Enable bit CONFIG1L~1~1=0x1,0x1,Enabled CONFIG1L~1~2=0x1,0x0,Disabled CONFIG1L~2~1=0x20,0x20,Enabled CONFIG1L~2~2=0x20,0x0,Disabled CONFIG1L~3~1=0x40,0x40,Enabled CONFIG1L~3~2=0x40,0x0,Disabled CONFIG1L~4~1=0x80,0x80,Disabled CONFIG1L~4~2=0x80,0x0,Enabled CONFIG1H_unused=0x0 CONFIG1H~1=CP0,0x4,Code Protect CONFIG1H~2=SIGN,0x8,Config Word Signature Bit CONFIG1H~3=RESERVED,0xf0,RESERVED CONFIG1H~1~1=0x4,0x4,Disabled CONFIG1H~1~2=0x4,0x0,Enabled CONFIG1H~2~1=0x8,0x8,Bulk erase of memory not conducated CONFIG1H~2~2=0x8,0x0,Bulk erase of memory area complete CONFIG1H~3~1=0xf0,0xf0,RESERVED CONFIG2L_unused=0x0 CONFIG2L~1=OSC,0x7,Oscillator Selection bits CONFIG2L~2=T1DIG,0x8,Secondary Clock Source T1OSCEN Enforcement CONFIG2L~3=LPT1OSC,0x10,Low-Power Timer1 Oscillator Enable bit CONFIG2L~4=FCMEN,0x40,Fail-Safe Clock Monitor Enable bit CONFIG2L~5=IESO,0x80,Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit CONFIG2L~1~1=0x7,0x7,EC Oscillator with PLL CONFIG2L~1~2=0x7,0x6,EC Oscillator with clock out on RA6 CONFIG2L~1~3=0x7,0x5,HS oscillator, PLL enabled CONFIG2L~1~4=0x7,0x4,HS oscillator CONFIG2L~1~5=0x7,0x3,INTOSC with PLL enabled, CLKOUT on RA6 and port function on RA7 CONFIG2L~1~6=0x7,0x2,Internal oscillator, CLKOUT on RA6 and port function on RA7 CONFIG2L~1~7=0x7,0x1,INTOSC with PLL enabled, port function on RA6 and RA7 CONFIG2L~1~8=0x7,0x0,Internal oscillator, port function on RA6 and RA7 CONFIG2L~2~1=0x8,0x8,Enabled CONFIG2L~2~2=0x8,0x0,Disabled CONFIG2L~3~1=0x10,0x0,Enabled CONFIG2L~3~2=0x10,0x10,Disabled CONFIG2L~4~1=0x40,0x0,Disabled CONFIG2L~4~2=0x40,0x40,Enabled CONFIG2L~5~1=0x80,0x0,Disabled CONFIG2L~5~2=0x80,0x80,Enabled CONFIG2H_unused=0x0 CONFIG2H~1=WDTPS,0xf,Watchdog Timer Postscaler Select bits CONFIG2H~2=RESERVED,0xf0,RESERVED CONFIG2H~1~1=0xf,0xf,1:32768 CONFIG2H~1~2=0xf,0xe,1:16384 CONFIG2H~1~3=0xf,0xd,1:8192 CONFIG2H~1~4=0xf,0xc,1:4096 CONFIG2H~1~5=0xf,0xb,1:2048 CONFIG2H~1~6=0xf,0xa,1:1024 CONFIG2H~1~7=0xf,0x9,1:512 CONFIG2H~1~8=0xf,0x8,1:256 CONFIG2H~1~9=0xf,0x7,1:128 CONFIG2H~1~10=0xf,0x6,1:64 CONFIG2H~1~11=0xf,0x5,1:32 CONFIG2H~1~12=0xf,0x4,1:16 CONFIG2H~1~13=0xf,0x3,1:8 CONFIG2H~1~14=0xf,0x2,1:4 CONFIG2H~1~15=0xf,0x1,1:2 CONFIG2H~1~16=0xf,0x0,1:1 CONFIG2H~2~1=0xf0,0xf0,RESERVED CONFIG3L_unused=0x0 CONFIG3L~1=RTCSOSC,0x2,RTCC Reference Clock Select bit CONFIG3L~1~1=0x2,0x2,RTCC uses T1OSC/T1CKI as reference clock CONFIG3L~1~2=0x2,0x0,RTCC uses INTOSC/INTRC as reference clock CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MX,0x1,CCP2 MUX CONFIG3H~2=RESERVED,0xf0,RESERVED CONFIG3H~1~1=0x1,0x0,RE7 / RB3 CONFIG3H~1~2=0x1,0x1,RC1 CONFIG3H~2~1=0xf0,0xf0,RESERVED erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F66K22] pgmmem=0x0 ~pgmmem=0xffff cfgmem=0x300000 ~cfgmem=0x30000d userid=0x200000 ~userid=0x200007 eedata=0x0 ~eedata=0x3ff devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0x52c0 configslots=14 0x300000=CONFIG1L 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004=CONFIG3L 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000a=CONFIG6L 0x30000b=CONFIG6H 0x30000c=CONFIG7L 0x30000d=CONFIG7H CONFIG1L_unused=0x0 CONFIG1L~1=RETEN,0x1,VREG Sleep Enable bit CONFIG1L~2=SOSCEL,0x18,SOSC Power Selection and mode Configuration bits CONFIG1L~3=XINST,0x40,Extended Instruction Set CONFIG1L~1~1=0x1,0x1,Enabled CONFIG1L~1~2=0x1,0x0,Disabled CONFIG1L~2~1=0x18,0x18,High Power SOSC circuit selected CONFIG1L~2~2=0x18,0x8,Low Power SOSC circuit selected CONFIG1L~2~3=0x18,0x10,Digital (SCLKI) mode CONFIG1L~3~1=0x40,0x40,Enabled CONFIG1L~3~2=0x40,0x0,Disabled CONFIG1H_unused=0x0 CONFIG1H~1=FOSC,0xf,Oscillator CONFIG1H~2=PLLCFG,0x10,PLL x4 Enable bit CONFIG1H~3=PRCKEN,0x20,Primary Clock Enable bit CONFIG1H~4=FCMEN,0x40,Fail-Safe Clock Monitor CONFIG1H~5=IESO,0x80,Internal External Oscillator Switch Over Mode CONFIG1H~1~1=0xf,0xd,EC oscillator (Low power, DC - 160 kHz) CONFIG1H~1~2=0xf,0xc,EC oscillator, CLKOUT function on OSC2 (Low power, DC - 160 kHz) CONFIG1H~1~3=0xf,0xb,EC oscillator (Medium power, 160 kHz - 4 MHz) CONFIG1H~1~4=0xf,0xa,EC oscillator, CLKOUT function on OSC2 (Medium power, 160 kHz - 4 MHz) CONFIG1H~1~5=0xf,0x9,Internal RC oscillator, CLKOUT function on OSC2 CONFIG1H~1~6=0xf,0x8,Internal RC oscillator CONFIG1H~1~7=0xf,0x5,EC oscillator (High power, 16 MHz - 25 MHz) CONFIG1H~1~8=0xf,0x4,EC oscillator, CLKOUT function on OSC2 (High power, 16 MHz - 25 MHz) CONFIG1H~1~9=0xf,0x3,HS oscillator (Medium power, 4 MHz - 16 MHz) CONFIG1H~1~10=0xf,0x2,HS oscillator (High power, 16 MHz - 25 MHz) CONFIG1H~1~11=0xf,0x1,XT oscillator CONFIG1H~1~12=0xf,0x0,LP oscillator CONFIG1H~1~13=0x7,0x7,External RC oscillator CONFIG1H~1~14=0x7,0x6,External RC oscillator, CLKOUT function on OSC2 CONFIG1H~2~1=0x10,0x10,Enabled CONFIG1H~2~2=0x10,0x0,Disabled CONFIG1H~3~1=0x20,0x0,Disabled CONFIG1H~3~2=0x20,0x20,Enabled CONFIG1H~4~1=0x40,0x0,Disabled CONFIG1H~4~2=0x40,0x40,Enabled CONFIG1H~5~1=0x80,0x0,Disabled CONFIG1H~5~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PWRTEN,0x1,Power Up Timer CONFIG2L~2=BOREN,0x6,Brown Out Detect CONFIG2L~3=BORV,0x18,Brown-out Reset Voltage bits CONFIG2L~4=BORPWR,0x60,BORMV Power level CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active, disabled in SLEEP, SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,1.8V CONFIG2L~3~2=0x18,0x10,2.0V CONFIG2L~3~3=0x18,0x8,2.7V CONFIG2L~3~4=0x18,0x0,3.0V CONFIG2L~4~1=0x60,0x60,ZPBORMV instead of BORMV is selected CONFIG2L~4~2=0x60,0x40,BORMV set to high power level CONFIG2L~4~3=0x60,0x20,BORMV set to medium power level CONFIG2L~4~4=0x60,0x0,BORMV set to low power level CONFIG2H_unused=0x0 CONFIG2H~1=WDTEN,0x3,Watchdog Timer CONFIG2H~2=WDTPS,0x7c,Watchdog Postscaler CONFIG2H~1~1=0x3,0x3,Enabled in hardware, SWDTEN disabled CONFIG2H~1~2=0x3,0x2,Enabled while active, disabled in SLEEP, SWDTEN disabled CONFIG2H~1~3=0x3,0x1,Controlled with SWDTEN bit CONFIG2H~1~4=0x3,0x0,Disabled in hardware, SWDTEN disabled CONFIG2H~2~1=0x7c,0x7c,1:1048576 CONFIG2H~2~2=0x7c,0x4c,1:524288 CONFIG2H~2~3=0x7c,0x48,1:262144 CONFIG2H~2~4=0x7c,0x44,1:131072 CONFIG2H~2~5=0x7c,0x40,1:65536 CONFIG2H~2~6=0x7c,0x3c,1:32768 CONFIG2H~2~7=0x7c,0x38,1:16384 CONFIG2H~2~8=0x7c,0x34,1:8192 CONFIG2H~2~9=0x7c,0x30,1:4096 CONFIG2H~2~10=0x7c,0x2c,1:2048 CONFIG2H~2~11=0x7c,0x28,1:1024 CONFIG2H~2~12=0x7c,0x24,1:512 CONFIG2H~2~13=0x7c,0x20,1:256 CONFIG2H~2~14=0x7c,0x1c,1:128 CONFIG2H~2~15=0x7c,0x18,1:64 CONFIG2H~2~16=0x7c,0x14,1:32 CONFIG2H~2~17=0x7c,0x10,1:16 CONFIG2H~2~18=0x7c,0xc,1:8 CONFIG2H~2~19=0x7c,0x8,1:4 CONFIG2H~2~20=0x7c,0x4,1:2 CONFIG2H~2~21=0x7c,0x0,1:1 CONFIG3L_unused=0x0 CONFIG3L~1=RTCOSC,0x1,RTCC Clock Select CONFIG3L~1~1=0x1,0x1,RTCC uses T1OSC/T1CKI CONFIG3L~1~2=0x1,0x0,RTCC uses INTRC CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MX,0x1,CCP2 Mux CONFIG3H~2=MSSPMSK,0x8,MSSP address masking CONFIG3H~3=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RE7-Microcontroller Mode/RB3-All other modes CONFIG3H~2~1=0x8,0x8,7 Bit address masking mode CONFIG3H~2~2=0x8,0x0,5 bit address masking mode CONFIG3H~3~1=0x80,0x80,MCLR Enabled, RG5 Disabled CONFIG3H~3~2=0x80,0x0,MCLR Disabled, RG5 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVREN,0x1,Stack Overflow Reset CONFIG4L~2=BBSIZ0,0x10,Boot Block Size CONFIG4L~3=DEBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x10,0x10,2K word Boot Block size CONFIG4L~2~2=0x10,0x0,1K word Boot Block size CONFIG4L~3~1=0x80,0x80,Disabled CONFIG4L~3~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP0,0x1,Code Protect 00800-03FFF CONFIG5L~2=CP1,0x2,Code Protect 04000-07FFF CONFIG5L~3=CP2,0x4,Code Protect 08000-0BFFF CONFIG5L~4=CP3,0x8,Code Protect 0C000-0FFFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x0,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x0,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x0,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x0,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPB,0x40,Code Protect Boot CONFIG5H~2=CPD,0x80,Data EE Read Protect CONFIG5H~1~1=0x40,0x40,Disabled CONFIG5H~1~2=0x40,0x0,Enabled CONFIG5H~2~1=0x80,0x80,Disabled CONFIG5H~2~2=0x80,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT0,0x1,Table Write Protect 00800-03FFF CONFIG6L~2=WRT1,0x2,Table Write Protect 04000-07FFF CONFIG6L~3=WRT2,0x4,Table Write Protect 08000-0BFFF CONFIG6L~4=WRT3,0x8,Table Write Protect 0C000-0FFFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x0,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x0,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x0,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x0,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTC,0x20,Config. Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTD,0x80,Data EE Write Protect CONFIG6H~1~1=0x20,0x20,Disabled CONFIG6H~1~2=0x20,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x80,0x80,Disabled CONFIG6H~3~2=0x80,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBRT0,0x1,Table Read Protect 00800-03FFF CONFIG7L~2=EBRT1,0x2,Table Read Protect 04000-07FFF CONFIG7L~3=EBRT2,0x4,Table Read Protect 08000-0BFFF CONFIG7L~4=EBRT3,0x8,Table Read Protect 0C000-0FFFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x0,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x0,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x0,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x0,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBRTB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F66K27] pgmmem=0x0 ~pgmmem=0x17fff cfgmem=0x300000 ~cfgmem=0x30000d userid=0x200000 ~userid=0x200007 eedata=0x0 ~eedata=0x3ff devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0x51a0 configslots=14 0x300000=CONFIG1L 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004=CONFIG3L 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000a=CONFIG6L 0x30000b=CONFIG6H 0x30000c=CONFIG7L 0x30000d=CONFIG7H CONFIG1L_unused=0x0 CONFIG1L~1=RETEN,0x1,VREG Sleep Enable bit CONFIG1L~2=SOSCEL,0x18,SOSC Power Selection and mode Configuration bits CONFIG1L~3=XINST,0x40,Extended Instruction Set CONFIG1L~1~1=0x1,0x1,Enabled CONFIG1L~1~2=0x1,0x0,Disabled CONFIG1L~2~1=0x18,0x18,High Power SOSC circuit selected CONFIG1L~2~2=0x18,0x8,Low Power SOSC circuit selected CONFIG1L~2~3=0x18,0x10,Digital (SCLKI) mode CONFIG1L~3~1=0x40,0x40,Enabled CONFIG1L~3~2=0x40,0x0,Disabled CONFIG1H_unused=0x0 CONFIG1H~1=FOSC,0xf,Oscillator CONFIG1H~2=PLLCFG,0x10,PLL x4 Enable bit CONFIG1H~3=PRCKEN,0x20,Primary Clock Enable bit CONFIG1H~4=FCMEN,0x40,Fail-Safe Clock Monitor CONFIG1H~5=IESO,0x80,Internal External Oscillator Switch Over Mode CONFIG1H~1~1=0xf,0xd,EC oscillator (Low power, DC - 160 kHz) CONFIG1H~1~2=0xf,0xc,EC oscillator, CLKOUT function on OSC2 (Low power, DC - 160 kHz) CONFIG1H~1~3=0xf,0xb,EC oscillator (Medium power, 160 kHz - 4 MHz) CONFIG1H~1~4=0xf,0xa,EC oscillator, CLKOUT function on OSC2 (Medium power, 160 kHz - 4 MHz) CONFIG1H~1~5=0xf,0x9,Internal RC oscillator, CLKOUT function on OSC2 CONFIG1H~1~6=0xf,0x8,Internal RC oscillator CONFIG1H~1~7=0xf,0x5,EC oscillator (High power, 16 MHz - 25 MHz) CONFIG1H~1~8=0xf,0x4,EC oscillator, CLKOUT function on OSC2 (High power, 16 MHz - 25 MHz) CONFIG1H~1~9=0xf,0x3,HS oscillator (Medium power, 4 MHz - 16 MHz) CONFIG1H~1~10=0xf,0x2,HS oscillator (High power, 16 MHz - 25 MHz) CONFIG1H~1~11=0xf,0x1,XT oscillator CONFIG1H~1~12=0xf,0x0,LP oscillator CONFIG1H~1~13=0x7,0x7,External RC oscillator CONFIG1H~1~14=0x7,0x6,External RC oscillator, CLKOUT function on OSC2 CONFIG1H~2~1=0x10,0x10,Enabled CONFIG1H~2~2=0x10,0x0,Disabled CONFIG1H~3~1=0x20,0x0,Disabled CONFIG1H~3~2=0x20,0x20,Enabled CONFIG1H~4~1=0x40,0x0,Disabled CONFIG1H~4~2=0x40,0x40,Enabled CONFIG1H~5~1=0x80,0x0,Disabled CONFIG1H~5~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PWRTEN,0x1,Power Up Timer CONFIG2L~2=BOREN,0x6,Brown Out Detect CONFIG2L~3=BORV,0x18,Brown-out Reset Voltage bits CONFIG2L~4=BORPWR,0x60,BORMV Power level CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active, disabled in SLEEP, SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,1.8V CONFIG2L~3~2=0x18,0x10,2.0V CONFIG2L~3~3=0x18,0x8,2.7V CONFIG2L~3~4=0x18,0x0,3.0V CONFIG2L~4~1=0x60,0x60,ZPBORMV instead of BORMV is selected CONFIG2L~4~2=0x60,0x40,BORMV set to high power level CONFIG2L~4~3=0x60,0x20,BORMV set to medium power level CONFIG2L~4~4=0x60,0x0,BORMV set to low power level CONFIG2H_unused=0x0 CONFIG2H~1=WDTEN,0x3,Watchdog Timer CONFIG2H~2=WDTPS,0x7c,Watchdog Postscaler CONFIG2H~1~1=0x3,0x3,Enabled in hardware, SWDTEN disabled CONFIG2H~1~2=0x3,0x2,Enabled while active, disabled in SLEEP, SWDTEN disabled CONFIG2H~1~3=0x3,0x1,Controlled with SWDTEN bit CONFIG2H~1~4=0x3,0x0,Disabled in hardware, SWDTEN disabled CONFIG2H~2~1=0x7c,0x7c,1:1048576 CONFIG2H~2~2=0x7c,0x4c,1:524288 CONFIG2H~2~3=0x7c,0x48,1:262144 CONFIG2H~2~4=0x7c,0x44,1:131072 CONFIG2H~2~5=0x7c,0x40,1:65536 CONFIG2H~2~6=0x7c,0x3c,1:32768 CONFIG2H~2~7=0x7c,0x38,1:16384 CONFIG2H~2~8=0x7c,0x34,1:8192 CONFIG2H~2~9=0x7c,0x30,1:4096 CONFIG2H~2~10=0x7c,0x2c,1:2048 CONFIG2H~2~11=0x7c,0x28,1:1024 CONFIG2H~2~12=0x7c,0x24,1:512 CONFIG2H~2~13=0x7c,0x20,1:256 CONFIG2H~2~14=0x7c,0x1c,1:128 CONFIG2H~2~15=0x7c,0x18,1:64 CONFIG2H~2~16=0x7c,0x14,1:32 CONFIG2H~2~17=0x7c,0x10,1:16 CONFIG2H~2~18=0x7c,0xc,1:8 CONFIG2H~2~19=0x7c,0x8,1:4 CONFIG2H~2~20=0x7c,0x4,1:2 CONFIG2H~2~21=0x7c,0x0,1:1 CONFIG3L_unused=0x0 CONFIG3L~1=RTCOSC,0x1,RTCC Clock Select CONFIG3L~1~1=0x1,0x1,RTCC uses T1OSC/T1CKI CONFIG3L~1~2=0x1,0x0,RTCC uses INTRC CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MX,0x1,CCP2 Mux CONFIG3H~2=MSSPMSK,0x8,MSSP address masking CONFIG3H~3=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RE7-Microcontroller Mode/RB3-All other modes CONFIG3H~2~1=0x8,0x8,7 Bit address masking mode CONFIG3H~2~2=0x8,0x0,5 bit address masking mode CONFIG3H~3~1=0x80,0x80,MCLR Enabled, RG5 Disabled CONFIG3H~3~2=0x80,0x0,MCLR Disabled, RG5 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVREN,0x1,Stack Overflow Reset CONFIG4L~2=BBSIZ0,0x10,Boot Block Size CONFIG4L~3=DEBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x10,0x10,2K word Boot Block size CONFIG4L~2~2=0x10,0x0,1K word Boot Block size CONFIG4L~3~1=0x80,0x80,Disabled CONFIG4L~3~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP0,0x1,Code Protect 00800-03FFF CONFIG5L~2=CP1,0x2,Code Protect 04000-07FFF CONFIG5L~3=CP2,0x4,Code Protect 08000-0BFFF CONFIG5L~4=CP3,0x8,Code Protect 0C000-0FFFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x0,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x0,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x0,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x0,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPB,0x40,Code Protect Boot CONFIG5H~2=CPD,0x80,Data EE Read Protect CONFIG5H~1~1=0x40,0x40,Disabled CONFIG5H~1~2=0x40,0x0,Enabled CONFIG5H~2~1=0x80,0x80,Disabled CONFIG5H~2~2=0x80,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT0,0x1,Table Write Protect 00800-03FFF CONFIG6L~2=WRT1,0x2,Table Write Protect 04000-07FFF CONFIG6L~3=WRT2,0x4,Table Write Protect 08000-0BFFF CONFIG6L~4=WRT3,0x8,Table Write Protect 0C000-0FFFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x0,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x0,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x0,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x0,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTC,0x20,Config. Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTD,0x80,Data EE Write Protect CONFIG6H~1~1=0x20,0x20,Disabled CONFIG6H~1~2=0x20,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x80,0x80,Disabled CONFIG6H~3~2=0x80,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBRT0,0x1,Table Read Protect 00800-03FFF CONFIG7L~2=EBRT1,0x2,Table Read Protect 04000-07FFF CONFIG7L~3=EBRT2,0x4,Table Read Protect 08000-0BFFF CONFIG7L~4=EBRT3,0x8,Table Read Protect 0C000-0FFFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x0,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x0,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x0,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x0,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBRTB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F66K90] pgmmem=0x0 ~pgmmem=0xffff cfgmem=0x300000 ~cfgmem=0x30000d userid=0x200000 ~userid=0x200007 eedata=0x0 ~eedata=0x3ff devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0x5200 configslots=14 0x300000=CONFIG1L 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004=CONFIG3L 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000a=CONFIG6L 0x30000b=CONFIG6H 0x30000c=CONFIG7L 0x30000d=CONFIG7H CONFIG1L_unused=0x0 CONFIG1L~1=RETEN,0x1,VREG Sleep Enable bit CONFIG1L~2=SOSCEL,0x18,SOSC Power Selection and mode Configuration bits CONFIG1L~3=XINST,0x40,Extended Instruction Set CONFIG1L~1~1=0x1,0x1,Enabled CONFIG1L~1~2=0x1,0x0,Disabled CONFIG1L~2~1=0x18,0x18,High Power SOSC circuit selected CONFIG1L~2~2=0x18,0x8,Low Power SOSC circuit selected CONFIG1L~2~3=0x18,0x10,Digital (SCLKI) mode CONFIG1L~3~1=0x40,0x40,Enabled CONFIG1L~3~2=0x40,0x0,Disabled CONFIG1H_unused=0x0 CONFIG1H~1=FOSC,0xf,Oscillator CONFIG1H~2=PLLCFG,0x10,PLL x4 Enable bit CONFIG1H~3=PRCKEN,0x20,Primary Clock Enable bit CONFIG1H~4=FCMEN,0x40,Fail-Safe Clock Monitor CONFIG1H~5=IESO,0x80,Internal External Oscillator Switch Over Mode CONFIG1H~1~1=0x7,0x7,External RC oscillator CONFIG1H~1~2=0x7,0x6,External RC oscillator, CLKOUT function on OSC2 CONFIG1H~1~3=0xf,0xd,EC oscillator (Low power, DC - 160 kHz) CONFIG1H~1~4=0xf,0xc,EC oscillator, CLKOUT function on OSC2 (Low power, DC - 160 kHz) CONFIG1H~1~5=0xf,0xb,EC oscillator (Medium power, 160 kHz - 4 MHz) CONFIG1H~1~6=0xf,0xa,EC oscillator, CLKOUT function on OSC2 (Medium power, 160 kHz - 4 MHz) CONFIG1H~1~7=0xf,0x9,Internal RC oscillator, CLKOUT function on OSC2 CONFIG1H~1~8=0xf,0x8,Internal RC oscillator CONFIG1H~1~9=0xf,0x5,EC oscillator (High power, 16 MHz - 25 MHz) CONFIG1H~1~10=0xf,0x4,EC oscillator, CLKOUT function on OSC2 (High power, 16 MHz - 25 MHz) CONFIG1H~1~11=0xf,0x3,HS oscillator (Medium power, 4 MHz - 16 MHz) CONFIG1H~1~12=0xf,0x2,HS oscillator (High power, 16 MHz - 25 MHz) CONFIG1H~1~13=0xf,0x1,XT oscillator CONFIG1H~1~14=0xf,0x0,LP oscillator CONFIG1H~2~1=0x10,0x10,Enabled CONFIG1H~2~2=0x10,0x0,Disabled CONFIG1H~3~1=0x20,0x0,Disabled CONFIG1H~3~2=0x20,0x20,Enabled CONFIG1H~4~1=0x40,0x0,Disabled CONFIG1H~4~2=0x40,0x40,Enabled CONFIG1H~5~1=0x80,0x0,Disabled CONFIG1H~5~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PWRTEN,0x1,Power Up Timer CONFIG2L~2=BOREN,0x6,Brown Out Detect CONFIG2L~3=BORV,0x18,Brown-out Reset Voltage bits CONFIG2L~4=BORPWR,0x60,BORMV Power level CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active, disabled in SLEEP, SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,1.8V CONFIG2L~3~2=0x18,0x10,2.0V CONFIG2L~3~3=0x18,0x8,2.7V CONFIG2L~3~4=0x18,0x0,3.0V CONFIG2L~4~1=0x60,0x60,ZPBORMV instead of BORMV is selected CONFIG2L~4~2=0x60,0x40,BORMV set to high power level CONFIG2L~4~3=0x60,0x20,BORMV set to medium power level CONFIG2L~4~4=0x60,0x0,BORMV set to low power level CONFIG2H_unused=0x0 CONFIG2H~1=WDTEN,0x3,Watchdog Timer CONFIG2H~2=WDTPS,0x7c,Watchdog Postscaler CONFIG2H~1~1=0x3,0x3,Enabled in hardware, SWDTEN disabled CONFIG2H~1~2=0x3,0x2,Enabled while active, disabled in SLEEP, SWDTEN disabled CONFIG2H~1~3=0x3,0x1,Controlled with SWDTEN bit CONFIG2H~1~4=0x3,0x0,Disabled in hardware, SWDTEN disabled CONFIG2H~2~1=0x7c,0x7c,1:1048576 CONFIG2H~2~2=0x7c,0x4c,1:524288 CONFIG2H~2~3=0x7c,0x48,1:262144 CONFIG2H~2~4=0x7c,0x44,1:131072 CONFIG2H~2~5=0x7c,0x40,1:65536 CONFIG2H~2~6=0x7c,0x3c,1:32768 CONFIG2H~2~7=0x7c,0x38,1:16384 CONFIG2H~2~8=0x7c,0x34,1:8192 CONFIG2H~2~9=0x7c,0x30,1:4096 CONFIG2H~2~10=0x7c,0x2c,1:2048 CONFIG2H~2~11=0x7c,0x28,1:1024 CONFIG2H~2~12=0x7c,0x24,1:512 CONFIG2H~2~13=0x7c,0x20,1:256 CONFIG2H~2~14=0x7c,0x1c,1:128 CONFIG2H~2~15=0x7c,0x18,1:64 CONFIG2H~2~16=0x7c,0x14,1:32 CONFIG2H~2~17=0x7c,0x10,1:16 CONFIG2H~2~18=0x7c,0xc,1:8 CONFIG2H~2~19=0x7c,0x8,1:4 CONFIG2H~2~20=0x7c,0x4,1:2 CONFIG2H~2~21=0x7c,0x0,1:1 CONFIG3L_unused=0x0 CONFIG3L~1=RTCOSC,0x1,RTCC Clock Select CONFIG3L~1~1=0x1,0x1,RTCC uses T1OSC/T1CKI CONFIG3L~1~2=0x1,0x0,RTCC uses INTRC CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MX,0x1,CCP2 Mux CONFIG3H~2=MSSPMSK,0x8,MSSP address masking CONFIG3H~3=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RE7-Microcontroller Mode/RB3-All other modes CONFIG3H~2~1=0x8,0x8,7 Bit address masking mode CONFIG3H~2~2=0x8,0x0,5 bit address masking mode CONFIG3H~3~1=0x80,0x80,MCLR Enabled, RG5 Disabled CONFIG3H~3~2=0x80,0x0,MCLR Disabled, RG5 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVREN,0x1,Stack Overflow Reset CONFIG4L~2=BBSIZ0,0x10,Boot Block Size CONFIG4L~3=DEBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x10,0x10,2K word Boot Block size CONFIG4L~2~2=0x10,0x0,1K word Boot Block size CONFIG4L~3~1=0x80,0x80,Disabled CONFIG4L~3~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP0,0x1,Code Protect 00800-03FFF CONFIG5L~2=CP1,0x2,Code Protect 04000-07FFF CONFIG5L~3=CP2,0x4,Code Protect 08000-0BFFF CONFIG5L~4=CP3,0x8,Code Protect 0C000-0FFFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x0,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x0,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x0,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x0,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPB,0x40,Code Protect Boot CONFIG5H~2=CPD,0x80,Data EE Read Protect CONFIG5H~1~1=0x40,0x40,Disabled CONFIG5H~1~2=0x40,0x0,Enabled CONFIG5H~2~1=0x80,0x80,Disabled CONFIG5H~2~2=0x80,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT0,0x1,Table Write Protect 00800-03FFF CONFIG6L~2=WRT1,0x2,Table Write Protect 04000-07FFF CONFIG6L~3=WRT2,0x4,Table Write Protect 08000-0BFFF CONFIG6L~4=WRT3,0x8,Table Write Protect 0C000-0FFFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x0,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x0,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x0,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x0,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTC,0x20,Config. Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTD,0x80,Data EE Write Protect CONFIG6H~1~1=0x20,0x20,Disabled CONFIG6H~1~2=0x20,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x80,0x80,Disabled CONFIG6H~3~2=0x80,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBRT0,0x1,Table Read Protect 00800-03FFF CONFIG7L~2=EBRT1,0x2,Table Read Protect 04000-07FFF CONFIG7L~3=EBRT2,0x4,Table Read Protect 08000-0BFFF CONFIG7L~4=EBRT3,0x8,Table Read Protect 0C000-0FFFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x0,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x0,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x0,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x0,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBRTB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F66K95] pgmmem=0x0 ~pgmmem=0x17fff cfgmem=0x300000 ~cfgmem=0x30000d userid=0x200000 ~userid=0x200007 eedata=0x0 ~eedata=0x3ff devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0x5120 configslots=14 0x300000=CONFIG1L 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004=CONFIG3L 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000a=CONFIG6L 0x30000b=CONFIG6H 0x30000c=CONFIG7L 0x30000d=CONFIG7H CONFIG1L_unused=0x0 CONFIG1L~1=RETEN,0x1,VREG Sleep Enable bit CONFIG1L~2=SOSCEL,0x18,SOSC Power Selection and mode Configuration bits CONFIG1L~3=XINST,0x40,Extended Instruction Set CONFIG1L~1~1=0x1,0x1,Enabled CONFIG1L~1~2=0x1,0x0,Disabled CONFIG1L~2~1=0x18,0x18,High Power SOSC circuit selected CONFIG1L~2~2=0x18,0x8,Low Power SOSC circuit selected CONFIG1L~2~3=0x18,0x10,Digital (SCLKI) mode CONFIG1L~3~1=0x40,0x40,Enabled CONFIG1L~3~2=0x40,0x0,Disabled CONFIG1H_unused=0x0 CONFIG1H~1=FOSC,0xf,Oscillator CONFIG1H~2=PLLCFG,0x10,PLL x4 Enable bit CONFIG1H~3=PRCKEN,0x20,Primary Clock Enable bit CONFIG1H~4=FCMEN,0x40,Fail-Safe Clock Monitor CONFIG1H~5=IESO,0x80,Internal External Oscillator Switch Over Mode CONFIG1H~1~1=0x7,0x7,External RC oscillator CONFIG1H~1~2=0x7,0x6,External RC oscillator, CLKOUT function on OSC2 CONFIG1H~1~3=0xf,0xd,EC oscillator (Low power, DC - 160 kHz) CONFIG1H~1~4=0xf,0xc,EC oscillator, CLKOUT function on OSC2 (Low power, DC - 160 kHz) CONFIG1H~1~5=0xf,0xb,EC oscillator (Medium power, 160 kHz - 4 MHz) CONFIG1H~1~6=0xf,0xa,EC oscillator, CLKOUT function on OSC2 (Medium power, 160 kHz - 4 MHz) CONFIG1H~1~7=0xf,0x9,Internal RC oscillator, CLKOUT function on OSC2 CONFIG1H~1~8=0xf,0x8,Internal RC oscillator CONFIG1H~1~9=0xf,0x5,EC oscillator (High power, 16 MHz - 25 MHz) CONFIG1H~1~10=0xf,0x4,EC oscillator, CLKOUT function on OSC2 (High power, 16 MHz - 25 MHz) CONFIG1H~1~11=0xf,0x3,HS oscillator (Medium power, 4 MHz - 16 MHz) CONFIG1H~1~12=0xf,0x2,HS oscillator (High power, 16 MHz - 25 MHz) CONFIG1H~1~13=0xf,0x1,XT oscillator CONFIG1H~1~14=0xf,0x0,LP oscillator CONFIG1H~2~1=0x10,0x10,Enabled CONFIG1H~2~2=0x10,0x0,Disabled CONFIG1H~3~1=0x20,0x0,Disabled CONFIG1H~3~2=0x20,0x20,Enabled CONFIG1H~4~1=0x40,0x0,Disabled CONFIG1H~4~2=0x40,0x40,Enabled CONFIG1H~5~1=0x80,0x0,Disabled CONFIG1H~5~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PWRTEN,0x1,Power Up Timer CONFIG2L~2=BOREN,0x6,Brown Out Detect CONFIG2L~3=BORV,0x18,Brown-out Reset Voltage bits CONFIG2L~4=BORPWR,0x60,BORMV Power level CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active, disabled in SLEEP, SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,1.8V CONFIG2L~3~2=0x18,0x10,2.0V CONFIG2L~3~3=0x18,0x8,2.7V CONFIG2L~3~4=0x18,0x0,3.0V CONFIG2L~4~1=0x60,0x60,ZPBORMV instead of BORMV is selected CONFIG2L~4~2=0x60,0x40,BORMV set to high power level CONFIG2L~4~3=0x60,0x20,BORMV set to medium power level CONFIG2L~4~4=0x60,0x0,BORMV set to low power level CONFIG2H_unused=0x0 CONFIG2H~1=WDTEN,0x3,Watchdog Timer CONFIG2H~2=WDTPS,0x7c,Watchdog Postscaler CONFIG2H~1~1=0x3,0x3,Enabled in hardware, SWDTEN disabled CONFIG2H~1~2=0x3,0x2,Enabled while active, disabled in SLEEP, SWDTEN disabled CONFIG2H~1~3=0x3,0x1,Controlled with SWDTEN bit CONFIG2H~1~4=0x3,0x0,Disabled in hardware, SWDTEN disabled CONFIG2H~2~1=0x7c,0x7c,1:1048576 CONFIG2H~2~2=0x7c,0x4c,1:524288 CONFIG2H~2~3=0x7c,0x48,1:262144 CONFIG2H~2~4=0x7c,0x44,1:131072 CONFIG2H~2~5=0x7c,0x40,1:65536 CONFIG2H~2~6=0x7c,0x3c,1:32768 CONFIG2H~2~7=0x7c,0x38,1:16384 CONFIG2H~2~8=0x7c,0x34,1:8192 CONFIG2H~2~9=0x7c,0x30,1:4096 CONFIG2H~2~10=0x7c,0x2c,1:2048 CONFIG2H~2~11=0x7c,0x28,1:1024 CONFIG2H~2~12=0x7c,0x24,1:512 CONFIG2H~2~13=0x7c,0x20,1:256 CONFIG2H~2~14=0x7c,0x1c,1:128 CONFIG2H~2~15=0x7c,0x18,1:64 CONFIG2H~2~16=0x7c,0x14,1:32 CONFIG2H~2~17=0x7c,0x10,1:16 CONFIG2H~2~18=0x7c,0xc,1:8 CONFIG2H~2~19=0x7c,0x8,1:4 CONFIG2H~2~20=0x7c,0x4,1:2 CONFIG2H~2~21=0x7c,0x0,1:1 CONFIG3L_unused=0x0 CONFIG3L~1=RTCOSC,0x1,RTCC Clock Select CONFIG3L~1~1=0x1,0x1,RTCC uses T1OSC/T1CKI CONFIG3L~1~2=0x1,0x0,RTCC uses INTRC CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MX,0x1,CCP2 Mux CONFIG3H~2=MSSPMSK,0x8,MSSP address masking CONFIG3H~3=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RE7-Microcontroller Mode/RB3-All other modes CONFIG3H~2~1=0x8,0x8,7 Bit address masking mode CONFIG3H~2~2=0x8,0x0,5 bit address masking mode CONFIG3H~3~1=0x80,0x80,MCLR Enabled, RG5 Disabled CONFIG3H~3~2=0x80,0x0,MCLR Disabled, RG5 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVREN,0x1,Stack Overflow Reset CONFIG4L~2=BBSIZ0,0x10,Boot Block Size CONFIG4L~3=DEBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x10,0x10,2K word Boot Block size CONFIG4L~2~2=0x10,0x0,1K word Boot Block size CONFIG4L~3~1=0x80,0x80,Disabled CONFIG4L~3~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP0,0x1,Code Protect 00800-03FFF CONFIG5L~2=CP1,0x2,Code Protect 04000-07FFF CONFIG5L~3=CP2,0x4,Code Protect 08000-0BFFF CONFIG5L~4=CP3,0x8,Code Protect 0C000-0FFFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x0,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x0,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x0,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x0,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPB,0x40,Code Protect Boot CONFIG5H~2=CPD,0x80,Data EE Read Protect CONFIG5H~1~1=0x40,0x40,Disabled CONFIG5H~1~2=0x40,0x0,Enabled CONFIG5H~2~1=0x80,0x80,Disabled CONFIG5H~2~2=0x80,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT0,0x1,Table Write Protect 00800-03FFF CONFIG6L~2=WRT1,0x2,Table Write Protect 04000-07FFF CONFIG6L~3=WRT2,0x4,Table Write Protect 08000-0BFFF CONFIG6L~4=WRT3,0x8,Table Write Protect 0C000-0FFFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x0,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x0,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x0,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x0,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTC,0x20,Config. Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTD,0x80,Data EE Write Protect CONFIG6H~1~1=0x20,0x20,Disabled CONFIG6H~1~2=0x20,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x80,0x80,Disabled CONFIG6H~3~2=0x80,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBRT0,0x1,Table Read Protect 00800-03FFF CONFIG7L~2=EBRT1,0x2,Table Read Protect 04000-07FFF CONFIG7L~3=EBRT2,0x4,Table Read Protect 08000-0BFFF CONFIG7L~4=EBRT3,0x8,Table Read Protect 0C000-0FFFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x0,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x0,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x0,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x0,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBRTB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F6723] pgmmem=0x0 ~pgmmem=0x1ffff cfgmem=0x300000 ~cfgmem=0x30000d userid=0x200000 ~userid=0x200007 eedata=0x0 ~eedata=0x3ff devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0x4a00 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000a=CONFIG6L 0x30000b=CONFIG6H 0x30000c=CONFIG7L 0x30000d=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xf,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xc,0xc,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xe,0xa,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xf,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xf,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xf,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xf,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xf,0x5,EC-Port on RA6 CONFIG1H~1~8=0xf,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xf,0x3,0011 EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xf,0x2,HS CONFIG1H~1~11=0xf,0x1,XT CONFIG1H~1~12=0xf,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x8,4.2V CONFIG2L~3~4=0x18,0x0,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1e,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1e,0x1e,1:32768 CONFIG2H~2~2=0x1e,0x1c,1:16384 CONFIG2H~2~3=0x1e,0x1a,1:8192 CONFIG2H~2~4=0x1e,0x18,1:4096 CONFIG2H~2~5=0x1e,0x16,1:2048 CONFIG2H~2~6=0x1e,0x14,1:1024 CONFIG2H~2~7=0x1e,0x12,1:512 CONFIG2H~2~8=0x1e,0x10,1:256 CONFIG2H~2~9=0x1e,0xe,1:128 CONFIG2H~2~10=0x1e,0xc,1:64 CONFIG2H~2~11=0x1e,0xa,1:32 CONFIG2H~2~12=0x1e,0x8,1:16 CONFIG2H~2~13=0x1e,0x6,1:8 CONFIG2H~2~14=0x1e,0x4,1:4 CONFIG2H~2~15=0x1e,0x2,1:2 CONFIG2H~2~16=0x1e,0x0,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=LPT1OSC,0x4,Low Power Timer1 Osc enable CONFIG3H~3=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,CCP2 muxed with RC1 CONFIG3H~1~2=0x1,0x0,CCP2 muxed with RE7 CONFIG3H~2~1=0x4,0x4,Enabled CONFIG3H~2~2=0x4,0x0,Disabled CONFIG3H~3~1=0x80,0x80,MCLR Enabled,RG5 Disabled CONFIG3H~3~2=0x80,0x0,MCLR Disabled, RG5 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=BBSIZ,0x30,Boot Block Size CONFIG4L~4=XINST,0x40,Extended Instruction Set Enable bit CONFIG4L~5=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x20,0x20,4K Words (8 Kbytes) CONFIG4L~3~2=0x30,0x10,2K Words (4 Kbytes) CONFIG4L~3~3=0x30,0x0,1K Words (2 Kbytes) CONFIG4L~4~1=0x40,0x40,Enabled CONFIG4L~4~2=0x40,0x0,Disabled CONFIG4L~5~1=0x80,0x80,Disabled CONFIG4L~5~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-03FFF CONFIG5L~2=CP_1,0x2,Code Protect 04000-07FFF CONFIG5L~3=CP_2,0x4,Code Protect 08000-0BFFF CONFIG5L~4=CP_3,0x8,Code Protect 0C000-0FFFF CONFIG5L~5=CP_4,0x10,Code Protect 10000-13FFF CONFIG5L~6=CP_5,0x20,Code Protect 14000-17FFF CONFIG5L~7=CP_6,0x40,Code Protect 18000-1BFFF CONFIG5L~8=CP_7,0x80,Code Protect 1C000-1FFFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x0,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x0,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x0,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x0,Enabled CONFIG5L~5~1=0x10,0x10,Disabled CONFIG5L~5~2=0x10,0x0,Enabled CONFIG5L~6~1=0x20,0x20,Disabled CONFIG5L~6~2=0x20,0x0,Enabled CONFIG5L~7~1=0x40,0x40,Disabled CONFIG5L~7~2=0x40,0x0,Enabled CONFIG5L~8~1=0x80,0x80,Disabled CONFIG5L~8~2=0x80,0x0,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPB,0x40,Code Protect Boot CONFIG5H~2=CPD,0x80,Data EE Read Protect CONFIG5H~1~1=0x40,0x40,Disabled CONFIG5H~1~2=0x40,0x0,Enabled CONFIG5H~2~1=0x80,0x80,Disabled CONFIG5H~2~2=0x80,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-03FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 04000-07FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 08000-0BFFF CONFIG6L~4=WRT_3,0x8,Table Write Protect 0C000-0FFFF CONFIG6L~5=WRT_4,0x10,Table Write Protect 10000-13FFF CONFIG6L~6=WRT_5,0x20,Table Write Protect 14000-17FFF CONFIG6L~7=WRT_6,0x40,Table Write Protect 18000-1BFFF CONFIG6L~8=WRT_7,0x80,Table Write Protect 1C000-1FFFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x0,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x0,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x0,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x0,Enabled CONFIG6L~5~1=0x10,0x10,Disabled CONFIG6L~5~2=0x10,0x0,Enabled CONFIG6L~6~1=0x20,0x20,Disabled CONFIG6L~6~2=0x20,0x0,Enabled CONFIG6L~7~1=0x40,0x40,Disabled CONFIG6L~7~2=0x40,0x0,Enabled CONFIG6L~8~1=0x80,0x80,Disabled CONFIG6L~8~2=0x80,0x0,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTC,0x20,Config. Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTD,0x80,Data EE Write Protect CONFIG6H~1~1=0x20,0x20,Disabled CONFIG6H~1~2=0x20,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x80,0x80,Disabled CONFIG6H~3~2=0x80,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-03FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 04000-07FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 08000-0BFFF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 0C000-0FFFF CONFIG7L~5=EBTR_4,0x10,Table Read Protect 10000-13FFF CONFIG7L~6=EBTR_5,0x20,Table Read Protect 14000-17FFF CONFIG7L~7=EBTR_6,0x40,Table Read Protect 18000-1BFFF CONFIG7L~8=EBTR_7,0x80,Table Read Protect 1C000-1FFFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x0,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x0,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x0,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x0,Enabled CONFIG7L~5~1=0x10,0x10,Disabled CONFIG7L~5~2=0x10,0x0,Enabled CONFIG7L~6~1=0x20,0x20,Disabled CONFIG7L~6~2=0x20,0x0,Enabled CONFIG7L~7~1=0x40,0x40,Disabled CONFIG7L~7~2=0x40,0x0,Enabled CONFIG7L~8~1=0x80,0x80,Disabled CONFIG7L~8~2=0x80,0x0,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F67J90] pgmmem=0x20000 ~pgmmem=0x1fffff cfgmem=0x1fff8 ~cfgmem=0x1ffff userid= ~userid= eedata= ~eedata= devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0x5020 configslots=8 0x1fff8=CONFIG1L 0x1fff9=CONFIG1H 0x1fffa=CONFIG2L 0x1fffb=CONFIG2H 0x1fffc=CONFIG3L 0x1fffd=CONFIG3H 0x1fffe= 0x1ffff= CONFIG1L_unused=0x0 CONFIG1L~1=WDTEN,0x1,Watchdog Timer CONFIG1L~2=STVREN,0x20,Stack Overflow Reset CONFIG1L~3=XINST,0x40,Extended Instruction Set Enable bit CONFIG1L~4=DEBUG,0x80,Background Debugger Enable bit CONFIG1L~1~1=0x1,0x1,Enabled CONFIG1L~1~2=0x1,0x0,Disabled CONFIG1L~2~1=0x20,0x20,Enabled CONFIG1L~2~2=0x20,0x0,Disabled CONFIG1L~3~1=0x40,0x40,Enabled CONFIG1L~3~2=0x40,0x0,Disabled CONFIG1L~4~1=0x80,0x80,Disabled CONFIG1L~4~2=0x80,0x0,Enabled CONFIG1H_unused=0x0 CONFIG1H~1=CP0,0x4,Code Protect CONFIG1H~2=SIGN,0x8,Config Word Signature Bit CONFIG1H~3=RESERVED,0xf0,RESERVED CONFIG1H~1~1=0x4,0x4,Disabled CONFIG1H~1~2=0x4,0x0,Enabled CONFIG1H~2~1=0x8,0x8,Bulk erase of memory not conducated CONFIG1H~2~2=0x8,0x0,Bulk erase of memory area complete CONFIG1H~3~1=0xf0,0xf0,RESERVED CONFIG2L_unused=0x0 CONFIG2L~1=OSC,0x7,Oscillator Selection bits CONFIG2L~2=T1DIG,0x8,Secondary Clock Source T1OSCEN Enforcement CONFIG2L~3=LPT1OSC,0x10,Low-Power Timer1 Oscillator Enable bit CONFIG2L~4=FCMEN,0x40,Fail-Safe Clock Monitor Enable bit CONFIG2L~5=IESO,0x80,Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit CONFIG2L~1~1=0x7,0x7,EC Oscillator with PLL CONFIG2L~1~2=0x7,0x6,EC Oscillator with clock out on RA6 CONFIG2L~1~3=0x7,0x5,HS oscillator, PLL enabled CONFIG2L~1~4=0x7,0x4,HS oscillator CONFIG2L~1~5=0x7,0x3,INTOSC with PLL enabled, CLKOUT on RA6 and port function on RA7 CONFIG2L~1~6=0x7,0x2,Internal oscillator, CLKOUT on RA6 and port function on RA7 CONFIG2L~1~7=0x7,0x1,INTOSC with PLL enabled, port function on RA6 and RA7 CONFIG2L~1~8=0x7,0x0,Internal oscillator, port function on RA6 and RA7 CONFIG2L~2~1=0x8,0x8,Enabled CONFIG2L~2~2=0x8,0x0,Disabled CONFIG2L~3~1=0x10,0x0,Enabled CONFIG2L~3~2=0x10,0x10,Disabled CONFIG2L~4~1=0x40,0x0,Disabled CONFIG2L~4~2=0x40,0x40,Enabled CONFIG2L~5~1=0x80,0x0,Disabled CONFIG2L~5~2=0x80,0x80,Enabled CONFIG2H_unused=0x0 CONFIG2H~1=WDTPS,0xf,Watchdog Timer Postscaler Select bits CONFIG2H~2=RESERVED,0xf0,RESERVED CONFIG2H~1~1=0xf,0xf,1:32768 CONFIG2H~1~2=0xf,0xe,1:16384 CONFIG2H~1~3=0xf,0xd,1:8192 CONFIG2H~1~4=0xf,0xc,1:4096 CONFIG2H~1~5=0xf,0xb,1:2048 CONFIG2H~1~6=0xf,0xa,1:1024 CONFIG2H~1~7=0xf,0x9,1:512 CONFIG2H~1~8=0xf,0x8,1:256 CONFIG2H~1~9=0xf,0x7,1:128 CONFIG2H~1~10=0xf,0x6,1:64 CONFIG2H~1~11=0xf,0x5,1:32 CONFIG2H~1~12=0xf,0x4,1:16 CONFIG2H~1~13=0xf,0x3,1:8 CONFIG2H~1~14=0xf,0x2,1:4 CONFIG2H~1~15=0xf,0x1,1:2 CONFIG2H~1~16=0xf,0x0,1:1 CONFIG2H~2~1=0xf0,0xf0,RESERVED CONFIG3L_unused=0x0 CONFIG3L~1=RTCSOSC,0x2,RTCC Reference Clock Select bit CONFIG3L~1~1=0x2,0x2,RTCC uses T1OSC/T1CKI as reference clock CONFIG3L~1~2=0x2,0x0,RTCC uses INTOSC/INTRC as reference clock CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MX,0x1,CCP2 MUX CONFIG3H~2=RESERVED,0xf0,RESERVED CONFIG3H~1~1=0x1,0x0,RE7 / RB3 CONFIG3H~1~2=0x1,0x1,RC1 CONFIG3H~2~1=0xf0,0xf0,RESERVED erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F67J93] pgmmem=0x20000 ~pgmmem=0x1fffff cfgmem=0x1fff8 ~cfgmem=0x1ffff userid= ~userid= eedata= ~eedata= devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0x5060 configslots=8 0x1fff8=CONFIG1L 0x1fff9=CONFIG1H 0x1fffa=CONFIG2L 0x1fffb=CONFIG2H 0x1fffc=CONFIG3L 0x1fffd=CONFIG3H 0x1fffe= 0x1ffff= CONFIG1L_unused=0x0 CONFIG1L~1=WDTEN,0x1,Watchdog Timer CONFIG1L~2=STVREN,0x20,Stack Overflow Reset CONFIG1L~3=XINST,0x40,Extended Instruction Set Enable bit CONFIG1L~4=DEBUG,0x80,Background Debugger Enable bit CONFIG1L~1~1=0x1,0x1,Enabled CONFIG1L~1~2=0x1,0x0,Disabled CONFIG1L~2~1=0x20,0x20,Enabled CONFIG1L~2~2=0x20,0x0,Disabled CONFIG1L~3~1=0x40,0x40,Enabled CONFIG1L~3~2=0x40,0x0,Disabled CONFIG1L~4~1=0x80,0x80,Disabled CONFIG1L~4~2=0x80,0x0,Enabled CONFIG1H_unused=0x0 CONFIG1H~1=CP0,0x4,Code Protect CONFIG1H~2=SIGN,0x8,Config Word Signature Bit CONFIG1H~3=RESERVED,0xf0,RESERVED CONFIG1H~1~1=0x4,0x4,Disabled CONFIG1H~1~2=0x4,0x0,Enabled CONFIG1H~2~1=0x8,0x8,Bulk erase of memory not conducated CONFIG1H~2~2=0x8,0x0,Bulk erase of memory area complete CONFIG1H~3~1=0xf0,0xf0,RESERVED CONFIG2L_unused=0x0 CONFIG2L~1=OSC,0x7,Oscillator Selection bits CONFIG2L~2=T1DIG,0x8,Secondary Clock Source T1OSCEN Enforcement CONFIG2L~3=LPT1OSC,0x10,Low-Power Timer1 Oscillator Enable bit CONFIG2L~4=FCMEN,0x40,Fail-Safe Clock Monitor Enable bit CONFIG2L~5=IESO,0x80,Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit CONFIG2L~1~1=0x7,0x7,EC Oscillator with PLL CONFIG2L~1~2=0x7,0x6,EC Oscillator with clock out on RA6 CONFIG2L~1~3=0x7,0x5,HS oscillator, PLL enabled CONFIG2L~1~4=0x7,0x4,HS oscillator CONFIG2L~1~5=0x7,0x3,INTOSC with PLL enabled, CLKOUT on RA6 and port function on RA7 CONFIG2L~1~6=0x7,0x2,Internal oscillator, CLKOUT on RA6 and port function on RA7 CONFIG2L~1~7=0x7,0x1,INTOSC with PLL enabled, port function on RA6 and RA7 CONFIG2L~1~8=0x7,0x0,Internal oscillator, port function on RA6 and RA7 CONFIG2L~2~1=0x8,0x8,Enabled CONFIG2L~2~2=0x8,0x0,Disabled CONFIG2L~3~1=0x10,0x0,Enabled CONFIG2L~3~2=0x10,0x10,Disabled CONFIG2L~4~1=0x40,0x0,Disabled CONFIG2L~4~2=0x40,0x40,Enabled CONFIG2L~5~1=0x80,0x0,Disabled CONFIG2L~5~2=0x80,0x80,Enabled CONFIG2H_unused=0x0 CONFIG2H~1=WDTPS,0xf,Watchdog Timer Postscaler Select bits CONFIG2H~2=RESERVED,0xf0,RESERVED CONFIG2H~1~1=0xf,0xf,1:32768 CONFIG2H~1~2=0xf,0xe,1:16384 CONFIG2H~1~3=0xf,0xd,1:8192 CONFIG2H~1~4=0xf,0xc,1:4096 CONFIG2H~1~5=0xf,0xb,1:2048 CONFIG2H~1~6=0xf,0xa,1:1024 CONFIG2H~1~7=0xf,0x9,1:512 CONFIG2H~1~8=0xf,0x8,1:256 CONFIG2H~1~9=0xf,0x7,1:128 CONFIG2H~1~10=0xf,0x6,1:64 CONFIG2H~1~11=0xf,0x5,1:32 CONFIG2H~1~12=0xf,0x4,1:16 CONFIG2H~1~13=0xf,0x3,1:8 CONFIG2H~1~14=0xf,0x2,1:4 CONFIG2H~1~15=0xf,0x1,1:2 CONFIG2H~1~16=0xf,0x0,1:1 CONFIG2H~2~1=0xf0,0xf0,RESERVED CONFIG3L_unused=0x0 CONFIG3L~1=RTCSOSC,0x2,RTCC Reference Clock Select bit CONFIG3L~1~1=0x2,0x2,RTCC uses T1OSC/T1CKI as reference clock CONFIG3L~1~2=0x2,0x0,RTCC uses INTOSC/INTRC as reference clock CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MX,0x1,CCP2 MUX CONFIG3H~2=RESERVED,0xf0,RESERVED CONFIG3H~1~1=0x1,0x0,RE7 / RB3 CONFIG3H~1~2=0x1,0x1,RC1 CONFIG3H~2~1=0xf0,0xf0,RESERVED erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F67K22] pgmmem=0x0 ~pgmmem=0x1ffff cfgmem=0x300000 ~cfgmem=0x30000d userid=0x200000 ~userid=0x200007 eedata=0x0 ~eedata=0x3ff devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0x5180 configslots=14 0x300000=CONFIG1L 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004=CONFIG3L 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000a=CONFIG6L 0x30000b=CONFIG6H 0x30000c=CONFIG7L 0x30000d=CONFIG7H CONFIG1L_unused=0x0 CONFIG1L~1=RETEN,0x1,VREG Sleep Enable bit CONFIG1L~2=SOSCEL,0x18,SOSC Power Selection and mode Configuration bits CONFIG1L~3=XINST,0x40,Extended Instruction Set CONFIG1L~1~1=0x1,0x1,Enabled CONFIG1L~1~2=0x1,0x0,Disabled CONFIG1L~2~1=0x18,0x18,High Power SOSC circuit selected CONFIG1L~2~2=0x18,0x8,Low Power SOSC circuit selected CONFIG1L~2~3=0x18,0x10,Digital (SCLKI) mode CONFIG1L~3~1=0x40,0x40,Enabled CONFIG1L~3~2=0x40,0x0,Disabled CONFIG1H_unused=0x0 CONFIG1H~1=FOSC,0xf,Oscillator CONFIG1H~2=PLLCFG,0x10,PLL x4 Enable bit CONFIG1H~3=PRCKEN,0x20,Primary Clock Enable bit CONFIG1H~4=FCMEN,0x40,Fail-Safe Clock Monitor CONFIG1H~5=IESO,0x80,Internal External Oscillator Switch Over Mode CONFIG1H~1~1=0xf,0xd,EC oscillator (Low power, DC - 160 kHz) CONFIG1H~1~2=0xf,0xc,EC oscillator, CLKOUT function on OSC2 (Low power, DC - 160 kHz) CONFIG1H~1~3=0xf,0xb,EC oscillator (Medium power, 160 kHz - 4 MHz) CONFIG1H~1~4=0xf,0xa,EC oscillator, CLKOUT function on OSC2 (Medium power, 160 kHz - 4 MHz) CONFIG1H~1~5=0xf,0x9,Internal RC oscillator, CLKOUT function on OSC2 CONFIG1H~1~6=0xf,0x8,Internal RC oscillator CONFIG1H~1~7=0xf,0x5,EC oscillator (High power, 16 MHz - 25 MHz) CONFIG1H~1~8=0xf,0x4,EC oscillator, CLKOUT function on OSC2 (High power, 16 MHz - 25 MHz) CONFIG1H~1~9=0xf,0x3,HS oscillator (Medium power, 4 MHz - 16 MHz) CONFIG1H~1~10=0xf,0x2,HS oscillator (High power, 16 MHz - 25 MHz) CONFIG1H~1~11=0xf,0x1,XT oscillator CONFIG1H~1~12=0xf,0x0,LP oscillator CONFIG1H~1~13=0x7,0x7,External RC oscillator CONFIG1H~1~14=0x7,0x6,External RC oscillator, CLKOUT function on OSC2 CONFIG1H~2~1=0x10,0x10,Enabled CONFIG1H~2~2=0x10,0x0,Disabled CONFIG1H~3~1=0x20,0x0,Disabled CONFIG1H~3~2=0x20,0x20,Enabled CONFIG1H~4~1=0x40,0x0,Disabled CONFIG1H~4~2=0x40,0x40,Enabled CONFIG1H~5~1=0x80,0x0,Disabled CONFIG1H~5~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PWRTEN,0x1,Power Up Timer CONFIG2L~2=BOREN,0x6,Brown Out Detect CONFIG2L~3=BORV,0x18,Brown-out Reset Voltage bits CONFIG2L~4=BORPWR,0x60,BORMV Power level CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active, disabled in SLEEP, SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,1.8V CONFIG2L~3~2=0x18,0x10,2.0V CONFIG2L~3~3=0x18,0x8,2.7V CONFIG2L~3~4=0x18,0x0,3.0V CONFIG2L~4~1=0x60,0x60,ZPBORMV instead of BORMV is selected CONFIG2L~4~2=0x60,0x40,BORMV set to high power level CONFIG2L~4~3=0x60,0x20,BORMV set to medium power level CONFIG2L~4~4=0x60,0x0,BORMV set to low power level CONFIG2H_unused=0x0 CONFIG2H~1=WDTEN,0x3,Watchdog Timer CONFIG2H~2=WDTPS,0x7c,Watchdog Postscaler CONFIG2H~1~1=0x3,0x3,Enabled in hardware, SWDTEN disabled CONFIG2H~1~2=0x3,0x2,Enabled while active, disabled in SLEEP, SWDTEN disabled CONFIG2H~1~3=0x3,0x1,Controlled with SWDTEN bit CONFIG2H~1~4=0x3,0x0,Disabled in hardware, SWDTEN disabled CONFIG2H~2~1=0x7c,0x7c,1:1048576 CONFIG2H~2~2=0x7c,0x4c,1:524288 CONFIG2H~2~3=0x7c,0x48,1:262144 CONFIG2H~2~4=0x7c,0x44,1:131072 CONFIG2H~2~5=0x7c,0x40,1:65536 CONFIG2H~2~6=0x7c,0x3c,1:32768 CONFIG2H~2~7=0x7c,0x38,1:16384 CONFIG2H~2~8=0x7c,0x34,1:8192 CONFIG2H~2~9=0x7c,0x30,1:4096 CONFIG2H~2~10=0x7c,0x2c,1:2048 CONFIG2H~2~11=0x7c,0x28,1:1024 CONFIG2H~2~12=0x7c,0x24,1:512 CONFIG2H~2~13=0x7c,0x20,1:256 CONFIG2H~2~14=0x7c,0x1c,1:128 CONFIG2H~2~15=0x7c,0x18,1:64 CONFIG2H~2~16=0x7c,0x14,1:32 CONFIG2H~2~17=0x7c,0x10,1:16 CONFIG2H~2~18=0x7c,0xc,1:8 CONFIG2H~2~19=0x7c,0x8,1:4 CONFIG2H~2~20=0x7c,0x4,1:2 CONFIG2H~2~21=0x7c,0x0,1:1 CONFIG3L_unused=0x0 CONFIG3L~1=RTCOSC,0x1,RTCC Clock Select CONFIG3L~1~1=0x1,0x1,RTCC uses T1OSC/T1CKI CONFIG3L~1~2=0x1,0x0,RTCC uses INTRC CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MX,0x1,CCP2 Mux CONFIG3H~2=MSSPMSK,0x8,MSSP address masking CONFIG3H~3=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RE7-Microcontroller Mode/RB3-All other modes CONFIG3H~2~1=0x8,0x8,7 Bit address masking mode CONFIG3H~2~2=0x8,0x0,5 bit address masking mode CONFIG3H~3~1=0x80,0x80,MCLR Enabled, RG5 Disabled CONFIG3H~3~2=0x80,0x0,MCLR Disabled, RG5 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVREN,0x1,Stack Overflow Reset CONFIG4L~2=BBSIZ0,0x10,Boot Block Size CONFIG4L~3=DEBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x10,0x10,2K word Boot Block size CONFIG4L~2~2=0x10,0x0,1K word Boot Block size CONFIG4L~3~1=0x80,0x80,Disabled CONFIG4L~3~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP0,0x1,Code Protect 00800-03FFF CONFIG5L~2=CP1,0x2,Code Protect 04000-07FFF CONFIG5L~3=CP2,0x4,Code Protect 08000-0BFFF CONFIG5L~4=CP3,0x8,Code Protect 0C000-0FFFF CONFIG5L~5=CP4,0x10,Code Protect 10000-13FFF CONFIG5L~6=CP5,0x20,Code Protect 14000-17FFF CONFIG5L~7=CP6,0x40,Code Protect 18000-1BFFF CONFIG5L~8=CP7,0x80,Code Protect 1C000-1FFFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x0,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x0,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x0,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x0,Enabled CONFIG5L~5~1=0x10,0x10,Disabled CONFIG5L~5~2=0x10,0x0,Enabled CONFIG5L~6~1=0x20,0x20,Disabled CONFIG5L~6~2=0x20,0x0,Enabled CONFIG5L~7~1=0x40,0x40,Disabled CONFIG5L~7~2=0x40,0x0,Enabled CONFIG5L~8~1=0x80,0x80,Disabled CONFIG5L~8~2=0x80,0x0,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPB,0x40,Code Protect Boot CONFIG5H~2=CPD,0x80,Data EE Read Protect CONFIG5H~1~1=0x40,0x40,Disabled CONFIG5H~1~2=0x40,0x0,Enabled CONFIG5H~2~1=0x80,0x80,Disabled CONFIG5H~2~2=0x80,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT0,0x1,Table Write Protect 00800-03FFF CONFIG6L~2=WRT1,0x2,Table Write Protect 04000-07FFF CONFIG6L~3=WRT2,0x4,Table Write Protect 08000-0BFFF CONFIG6L~4=WRT3,0x8,Table Write Protect 0C000-0FFFF CONFIG6L~5=WRT4,0x10,Table Write Protect 10000-13FFF CONFIG6L~6=WRT5,0x20,Table Write Protect 14000-17FFF CONFIG6L~7=WRT6,0x40,Table Write Protect 18000-1BFFF CONFIG6L~8=WRT7,0x80,Table Write Protect 1C000-1FFFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x0,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x0,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x0,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x0,Enabled CONFIG6L~5~1=0x10,0x10,Disabled CONFIG6L~5~2=0x10,0x0,Enabled CONFIG6L~6~1=0x20,0x20,Disabled CONFIG6L~6~2=0x20,0x0,Enabled CONFIG6L~7~1=0x40,0x40,Disabled CONFIG6L~7~2=0x40,0x0,Enabled CONFIG6L~8~1=0x80,0x80,Disabled CONFIG6L~8~2=0x80,0x0,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTC,0x20,Config. Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTD,0x80,Data EE Write Protect CONFIG6H~1~1=0x20,0x20,Disabled CONFIG6H~1~2=0x20,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x80,0x80,Disabled CONFIG6H~3~2=0x80,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBRT0,0x1,Table Read Protect 00800-03FFF CONFIG7L~2=EBRT1,0x2,Table Read Protect 04000-07FFF CONFIG7L~3=EBRT2,0x4,Table Read Protect 08000-0BFFF CONFIG7L~4=EBRT3,0x8,Table Read Protect 0C000-0FFFF CONFIG7L~5=EBRT4,0x10,Table Read Protect 10000-13FFF CONFIG7L~6=EBRT5,0x20,Table Read Protect 14000-17FFF CONFIG7L~7=EBRT6,0x40,Table Read Protect 18000-1BFFF CONFIG7L~8=EBRT7,0x80,Table Read Protect 1C000-1FFFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x0,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x0,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x0,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x0,Enabled CONFIG7L~5~1=0x10,0x10,Disabled CONFIG7L~5~2=0x10,0x0,Enabled CONFIG7L~6~1=0x20,0x20,Disabled CONFIG7L~6~2=0x20,0x0,Enabled CONFIG7L~7~1=0x40,0x40,Disabled CONFIG7L~7~2=0x40,0x0,Enabled CONFIG7L~8~1=0x80,0x80,Disabled CONFIG7L~8~2=0x80,0x0,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBRTB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F67K90] pgmmem=0x0 ~pgmmem=0x1ffff cfgmem=0x300000 ~cfgmem=0x30000d userid=0x200000 ~userid=0x200007 eedata=0x0 ~eedata=0x3ff devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0x5100 configslots=14 0x300000=CONFIG1L 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004=CONFIG3L 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000a=CONFIG6L 0x30000b=CONFIG6H 0x30000c=CONFIG7L 0x30000d=CONFIG7H CONFIG1L_unused=0x0 CONFIG1L~1=RETEN,0x1,VREG Sleep Enable bit CONFIG1L~2=SOSCEL,0x18,SOSC Power Selection and mode Configuration bits CONFIG1L~3=XINST,0x40,Extended Instruction Set CONFIG1L~1~1=0x1,0x1,Enabled CONFIG1L~1~2=0x1,0x0,Disabled CONFIG1L~2~1=0x18,0x18,High Power SOSC circuit selected CONFIG1L~2~2=0x18,0x8,Low Power SOSC circuit selected CONFIG1L~2~3=0x18,0x10,Digital (SCLKI) mode CONFIG1L~3~1=0x40,0x40,Enabled CONFIG1L~3~2=0x40,0x0,Disabled CONFIG1H_unused=0x0 CONFIG1H~1=FOSC,0xf,Oscillator CONFIG1H~2=PLLCFG,0x10,PLL x4 Enable bit CONFIG1H~3=PRCKEN,0x20,Primary Clock Enable bit CONFIG1H~4=FCMEN,0x40,Fail-Safe Clock Monitor CONFIG1H~5=IESO,0x80,Internal External Oscillator Switch Over Mode CONFIG1H~1~1=0x7,0x7,External RC oscillator CONFIG1H~1~2=0x7,0x6,External RC oscillator, CLKOUT function on OSC2 CONFIG1H~1~3=0xf,0xd,EC oscillator (Low power, DC - 160 kHz) CONFIG1H~1~4=0xf,0xc,EC oscillator, CLKOUT function on OSC2 (Low power, DC - 160 kHz) CONFIG1H~1~5=0xf,0xb,EC oscillator (Medium power, 160 kHz - 4 MHz) CONFIG1H~1~6=0xf,0xa,EC oscillator, CLKOUT function on OSC2 (Medium power, 160 kHz - 4 MHz) CONFIG1H~1~7=0xf,0x9,Internal RC oscillator, CLKOUT function on OSC2 CONFIG1H~1~8=0xf,0x8,Internal RC oscillator CONFIG1H~1~9=0xf,0x5,EC oscillator (High power, 16 MHz - 25 MHz) CONFIG1H~1~10=0xf,0x4,EC oscillator, CLKOUT function on OSC2 (High power, 16 MHz - 25 MHz) CONFIG1H~1~11=0xf,0x3,HS oscillator (Medium power, 4 MHz - 16 MHz) CONFIG1H~1~12=0xf,0x2,HS oscillator (High power, 16 MHz - 25 MHz) CONFIG1H~1~13=0xf,0x1,XT oscillator CONFIG1H~1~14=0xf,0x0,LP oscillator CONFIG1H~2~1=0x10,0x10,Enabled CONFIG1H~2~2=0x10,0x0,Disabled CONFIG1H~3~1=0x20,0x0,Disabled CONFIG1H~3~2=0x20,0x20,Enabled CONFIG1H~4~1=0x40,0x0,Disabled CONFIG1H~4~2=0x40,0x40,Enabled CONFIG1H~5~1=0x80,0x0,Disabled CONFIG1H~5~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PWRTEN,0x1,Power Up Timer CONFIG2L~2=BOREN,0x6,Brown Out Detect CONFIG2L~3=BORV,0x18,Brown-out Reset Voltage bits CONFIG2L~4=BORPWR,0x60,BORMV Power level CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active, disabled in SLEEP, SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,1.8V CONFIG2L~3~2=0x18,0x10,2.0V CONFIG2L~3~3=0x18,0x8,2.7V CONFIG2L~3~4=0x18,0x0,3.0V CONFIG2L~4~1=0x60,0x60,ZPBORMV instead of BORMV is selected CONFIG2L~4~2=0x60,0x40,BORMV set to high power level CONFIG2L~4~3=0x60,0x20,BORMV set to medium power level CONFIG2L~4~4=0x60,0x0,BORMV set to low power level CONFIG2H_unused=0x0 CONFIG2H~1=WDTEN,0x3,Watchdog Timer CONFIG2H~2=WDTPS,0x7c,Watchdog Postscaler CONFIG2H~1~1=0x3,0x3,Enabled in hardware, SWDTEN disabled CONFIG2H~1~2=0x3,0x2,Enabled while active, disabled in SLEEP, SWDTEN disabled CONFIG2H~1~3=0x3,0x1,Controlled with SWDTEN bit CONFIG2H~1~4=0x3,0x0,Disabled in hardware, SWDTEN disabled CONFIG2H~2~1=0x7c,0x7c,1:1048576 CONFIG2H~2~2=0x7c,0x4c,1:524288 CONFIG2H~2~3=0x7c,0x48,1:262144 CONFIG2H~2~4=0x7c,0x44,1:131072 CONFIG2H~2~5=0x7c,0x40,1:65536 CONFIG2H~2~6=0x7c,0x3c,1:32768 CONFIG2H~2~7=0x7c,0x38,1:16384 CONFIG2H~2~8=0x7c,0x34,1:8192 CONFIG2H~2~9=0x7c,0x30,1:4096 CONFIG2H~2~10=0x7c,0x2c,1:2048 CONFIG2H~2~11=0x7c,0x28,1:1024 CONFIG2H~2~12=0x7c,0x24,1:512 CONFIG2H~2~13=0x7c,0x20,1:256 CONFIG2H~2~14=0x7c,0x1c,1:128 CONFIG2H~2~15=0x7c,0x18,1:64 CONFIG2H~2~16=0x7c,0x14,1:32 CONFIG2H~2~17=0x7c,0x10,1:16 CONFIG2H~2~18=0x7c,0xc,1:8 CONFIG2H~2~19=0x7c,0x8,1:4 CONFIG2H~2~20=0x7c,0x4,1:2 CONFIG2H~2~21=0x7c,0x0,1:1 CONFIG3L_unused=0x0 CONFIG3L~1=RTCOSC,0x1,RTCC Clock Select CONFIG3L~1~1=0x1,0x1,RTCC uses T1OSC/T1CKI CONFIG3L~1~2=0x1,0x0,RTCC uses INTRC CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MX,0x1,CCP2 Mux CONFIG3H~2=MSSPMSK,0x8,MSSP address masking CONFIG3H~3=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RE7-Microcontroller Mode/RB3-All other modes CONFIG3H~2~1=0x8,0x8,7 Bit address masking mode CONFIG3H~2~2=0x8,0x0,5 bit address masking mode CONFIG3H~3~1=0x80,0x80,MCLR Enabled, RG5 Disabled CONFIG3H~3~2=0x80,0x0,MCLR Disabled, RG5 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVREN,0x1,Stack Overflow Reset CONFIG4L~2=BBSIZ0,0x10,Boot Block Size CONFIG4L~3=DEBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x10,0x10,2K word Boot Block size CONFIG4L~2~2=0x10,0x0,1K word Boot Block size CONFIG4L~3~1=0x80,0x80,Disabled CONFIG4L~3~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP0,0x1,Code Protect 00800-03FFF CONFIG5L~2=CP1,0x2,Code Protect 04000-07FFF CONFIG5L~3=CP2,0x4,Code Protect 08000-0BFFF CONFIG5L~4=CP3,0x8,Code Protect 0C000-0FFFF CONFIG5L~5=CP4,0x10,Code Protect 10000-13FFF CONFIG5L~6=CP5,0x20,Code Protect 14000-17FFF CONFIG5L~7=CP6,0x40,Code Protect 18000-1BFFF CONFIG5L~8=CP7,0x80,Code Protect 1C000-1FFFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x0,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x0,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x0,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x0,Enabled CONFIG5L~5~1=0x10,0x10,Disabled CONFIG5L~5~2=0x10,0x0,Enabled CONFIG5L~6~1=0x20,0x20,Disabled CONFIG5L~6~2=0x20,0x0,Enabled CONFIG5L~7~1=0x40,0x40,Disabled CONFIG5L~7~2=0x40,0x0,Enabled CONFIG5L~8~1=0x80,0x80,Disabled CONFIG5L~8~2=0x80,0x0,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPB,0x40,Code Protect Boot CONFIG5H~2=CPD,0x80,Data EE Read Protect CONFIG5H~1~1=0x40,0x40,Disabled CONFIG5H~1~2=0x40,0x0,Enabled CONFIG5H~2~1=0x80,0x80,Disabled CONFIG5H~2~2=0x80,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT0,0x1,Table Write Protect 00800-03FFF CONFIG6L~2=WRT1,0x2,Table Write Protect 04000-07FFF CONFIG6L~3=WRT2,0x4,Table Write Protect 08000-0BFFF CONFIG6L~4=WRT3,0x8,Table Write Protect 0C000-0FFFF CONFIG6L~5=WRT4,0x10,Table Write Protect 10000-13FFF CONFIG6L~6=WRT5,0x20,Table Write Protect 14000-17FFF CONFIG6L~7=WRT6,0x40,Table Write Protect 18000-1BFFF CONFIG6L~8=WRT7,0x80,Table Write Protect 1C000-1FFFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x0,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x0,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x0,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x0,Enabled CONFIG6L~5~1=0x10,0x10,Disabled CONFIG6L~5~2=0x10,0x0,Enabled CONFIG6L~6~1=0x20,0x20,Disabled CONFIG6L~6~2=0x20,0x0,Enabled CONFIG6L~7~1=0x40,0x40,Disabled CONFIG6L~7~2=0x40,0x0,Enabled CONFIG6L~8~1=0x80,0x80,Disabled CONFIG6L~8~2=0x80,0x0,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTC,0x20,Config. Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTD,0x80,Data EE Write Protect CONFIG6H~1~1=0x20,0x20,Disabled CONFIG6H~1~2=0x20,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x80,0x80,Disabled CONFIG6H~3~2=0x80,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBRT0,0x1,Table Read Protect 00800-03FFF CONFIG7L~2=EBRT1,0x2,Table Read Protect 04000-07FFF CONFIG7L~3=EBRT2,0x4,Table Read Protect 08000-0BFFF CONFIG7L~4=EBRT3,0x8,Table Read Protect 0C000-0FFFF CONFIG7L~5=EBRT4,0x10,Table Read Protect 10000-13FFF CONFIG7L~6=EBRT5,0x20,Table Read Protect 14000-17FFF CONFIG7L~7=EBRT6,0x40,Table Read Protect 18000-1BFFF CONFIG7L~8=EBRT7,0x80,Table Read Protect 1C000-1FFFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x0,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x0,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x0,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x0,Enabled CONFIG7L~5~1=0x10,0x10,Disabled CONFIG7L~5~2=0x10,0x0,Enabled CONFIG7L~6~1=0x20,0x20,Disabled CONFIG7L~6~2=0x20,0x0,Enabled CONFIG7L~7~1=0x40,0x40,Disabled CONFIG7L~7~2=0x40,0x0,Enabled CONFIG7L~8~1=0x80,0x80,Disabled CONFIG7L~8~2=0x80,0x0,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBRTB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F8313] pgmmem=0x0 ~pgmmem=0x1fff cfgmem=0x300000 ~cfgmem=0x30000d userid=0x200000 ~userid=0x200007 eedata= ~eedata= devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0x1a60 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004=CONFIG3L 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009= 0x30000a= 0x30000b= 0x30000c=CONFIG7L 0x30000d= CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xf,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xc,0xc,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xe,0xa,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xf,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xf,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xf,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xf,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xf,0x5,EC-Port on RA6 CONFIG1H~1~8=0xf,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xf,0x3,0011 EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xf,0x2,HS CONFIG1H~1~11=0xf,0x1,XT CONFIG1H~1~12=0xf,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x8,4.2V CONFIG2L~3~4=0x18,0x0,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1e,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1e,0x1e,1:32768 CONFIG2H~2~2=0x1e,0x1c,1:16384 CONFIG2H~2~3=0x1e,0x1a,1:8192 CONFIG2H~2~4=0x1e,0x18,1:4096 CONFIG2H~2~5=0x1e,0x16,1:2048 CONFIG2H~2~6=0x1e,0x14,1:1024 CONFIG2H~2~7=0x1e,0x12,1:512 CONFIG2H~2~8=0x1e,0x10,1:256 CONFIG2H~2~9=0x1e,0xe,1:128 CONFIG2H~2~10=0x1e,0xc,1:64 CONFIG2H~2~11=0x1e,0xa,1:32 CONFIG2H~2~12=0x1e,0x8,1:16 CONFIG2H~2~13=0x1e,0x6,1:8 CONFIG2H~2~14=0x1e,0x4,1:4 CONFIG2H~2~15=0x1e,0x2,1:2 CONFIG2H~2~16=0x1e,0x0,1:1 CONFIG3L_unused=0x0 CONFIG3L~1=PMODE,0x3,Processor Mode CONFIG3L~2=BW,0x40,Bus Width CONFIG3L~3=WAIT,0x80,External Bus Wait CONFIG3L~1~1=0x3,0x3,Microcontroller CONFIG3L~1~2=0x3,0x2,Microprocessor CONFIG3L~1~3=0x3,0x1,Microprocessor w/Boot CONFIG3L~1~4=0x3,0x0,Ext Microcontroller CONFIG3L~2~1=0x40,0x40,16-bit external CONFIG3L~2~2=0x40,0x0,8-bit external CONFIG3L~3~1=0x80,0x80,Disabled CONFIG3L~3~2=0x80,0x0,Enabled CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=LPT1OSC,0x4,Low Power Timer1 Osc enable CONFIG3H~3=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RE7 in microcontroller mode - RB3 in others CONFIG3H~2~1=0x4,0x4,Enabled CONFIG3H~2~2=0x4,0x0,Disabled CONFIG3H~3~1=0x80,0x80,MCLR Enabled, RG5 Disabled CONFIG3H~3~2=0x80,0x0,MCLR Disabled, RG5 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=ENHCPU,0x40,Extended CPU Enable CONFIG4L~3=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x40,0x40,Enabled CONFIG4L~2~2=0x40,0x0,Disabled CONFIG4L~3~1=0x80,0x80,Disabled CONFIG4L~3~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00000-01FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00000-01FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F8393] pgmmem=0x2000 ~pgmmem=0x1fffff cfgmem=0x300000 ~cfgmem=0x30000d userid=0x200000 ~userid=0x200007 eedata= ~eedata= devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0x1a20 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004=CONFIG3L 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009= 0x30000a= 0x30000b= 0x30000c=CONFIG7L 0x30000d= CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xf,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xc,0xc,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xe,0xa,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xf,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xf,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xf,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xf,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xf,0x5,EC-Port on RA6 CONFIG1H~1~8=0xf,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xf,0x3,0011 EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xf,0x2,HS CONFIG1H~1~11=0xf,0x1,XT CONFIG1H~1~12=0xf,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x8,4.2V CONFIG2L~3~4=0x18,0x0,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1e,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1e,0x1e,1:32768 CONFIG2H~2~2=0x1e,0x1c,1:16384 CONFIG2H~2~3=0x1e,0x1a,1:8192 CONFIG2H~2~4=0x1e,0x18,1:4096 CONFIG2H~2~5=0x1e,0x16,1:2048 CONFIG2H~2~6=0x1e,0x14,1:1024 CONFIG2H~2~7=0x1e,0x12,1:512 CONFIG2H~2~8=0x1e,0x10,1:256 CONFIG2H~2~9=0x1e,0xe,1:128 CONFIG2H~2~10=0x1e,0xc,1:64 CONFIG2H~2~11=0x1e,0xa,1:32 CONFIG2H~2~12=0x1e,0x8,1:16 CONFIG2H~2~13=0x1e,0x6,1:8 CONFIG2H~2~14=0x1e,0x4,1:4 CONFIG2H~2~15=0x1e,0x2,1:2 CONFIG2H~2~16=0x1e,0x0,1:1 CONFIG3L_unused=0x0 CONFIG3L~1=PMODE,0x3,Processor Mode CONFIG3L~2=BW,0x40,Bus Width CONFIG3L~3=WAIT,0x80,External Bus Wait CONFIG3L~1~1=0x3,0x3,Microcontroller CONFIG3L~1~2=0x3,0x2,Microprocessor CONFIG3L~1~3=0x3,0x1,Microprocessor w/Boot CONFIG3L~1~4=0x3,0x0,Ext Microcontroller CONFIG3L~2~1=0x40,0x40,16-bit external CONFIG3L~2~2=0x40,0x0,8-bit external CONFIG3L~3~1=0x80,0x80,Disabled CONFIG3L~3~2=0x80,0x0,Enabled CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=LPT1OSC,0x4,Low Power Timer1 Osc enable CONFIG3H~3=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RE7 CONFIG3H~2~1=0x4,0x4,Enabled CONFIG3H~2~2=0x4,0x0,Disabled CONFIG3H~3~1=0x80,0x80,MCLR Enabled, RG5 Disabled CONFIG3H~3~2=0x80,0x0,MCLR Disabled, RG5 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=XINST,0x40,Extended Instruction Set Enable bit CONFIG4L~3=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x40,0x40,Enabled CONFIG4L~2~2=0x40,0x0,Disabled CONFIG4L~3~1=0x80,0x80,Disabled CONFIG4L~3~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00000-01FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00000-01FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F8413] pgmmem=0x0 ~pgmmem=0x3fff cfgmem=0x300000 ~cfgmem=0x30000d userid=0x200000 ~userid=0x200007 eedata= ~eedata= devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0xe60 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004=CONFIG3L 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009= 0x30000a= 0x30000b= 0x30000c=CONFIG7L 0x30000d= CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xf,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xc,0xc,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xe,0xa,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xf,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xf,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xf,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xf,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xf,0x5,EC-Port on RA6 CONFIG1H~1~8=0xf,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xf,0x3,0011 EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xf,0x2,HS CONFIG1H~1~11=0xf,0x1,XT CONFIG1H~1~12=0xf,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x8,4.2V CONFIG2L~3~4=0x18,0x0,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1e,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1e,0x1e,1:32768 CONFIG2H~2~2=0x1e,0x1c,1:16384 CONFIG2H~2~3=0x1e,0x1a,1:8192 CONFIG2H~2~4=0x1e,0x18,1:4096 CONFIG2H~2~5=0x1e,0x16,1:2048 CONFIG2H~2~6=0x1e,0x14,1:1024 CONFIG2H~2~7=0x1e,0x12,1:512 CONFIG2H~2~8=0x1e,0x10,1:256 CONFIG2H~2~9=0x1e,0xe,1:128 CONFIG2H~2~10=0x1e,0xc,1:64 CONFIG2H~2~11=0x1e,0xa,1:32 CONFIG2H~2~12=0x1e,0x8,1:16 CONFIG2H~2~13=0x1e,0x6,1:8 CONFIG2H~2~14=0x1e,0x4,1:4 CONFIG2H~2~15=0x1e,0x2,1:2 CONFIG2H~2~16=0x1e,0x0,1:1 CONFIG3L_unused=0x0 CONFIG3L~1=PMODE,0x3,Processor Mode CONFIG3L~2=BW,0x40,Bus Width CONFIG3L~3=WAIT,0x80,External Bus Wait CONFIG3L~1~1=0x3,0x3,Microcontroller CONFIG3L~1~2=0x3,0x2,Microprocessor CONFIG3L~1~3=0x3,0x1,Microprocessor w/Boot CONFIG3L~1~4=0x3,0x0,Ext Microcontroller CONFIG3L~2~1=0x40,0x40,16-bit external CONFIG3L~2~2=0x40,0x0,8-bit external CONFIG3L~3~1=0x80,0x80,Disabled CONFIG3L~3~2=0x80,0x0,Enabled CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=LPT1OSC,0x4,Low Power Timer1 Osc enable CONFIG3H~3=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RE7 in microcontroller mode - RB3 in others CONFIG3H~2~1=0x4,0x4,Enabled CONFIG3H~2~2=0x4,0x0,Disabled CONFIG3H~3~1=0x80,0x80,MCLR Enabled, RG5 Disabled CONFIG3H~3~2=0x80,0x0,MCLR Disabled, RG5 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=ENHCPU,0x40,Extended CPU Enable CONFIG4L~3=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x40,0x40,Enabled CONFIG4L~2~2=0x40,0x0,Disabled CONFIG4L~3~1=0x80,0x80,Disabled CONFIG4L~3~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00000-03FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00000-03FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F8493] pgmmem=0x2000 ~pgmmem=0x1fffff cfgmem=0x300000 ~cfgmem=0x30000d userid=0x200000 ~userid=0x200007 eedata= ~eedata= devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0xe20 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004=CONFIG3L 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009= 0x30000a= 0x30000b= 0x30000c=CONFIG7L 0x30000d= CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xf,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xc,0xc,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xe,0xa,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xf,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xf,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xf,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xf,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xf,0x5,EC-Port on RA6 CONFIG1H~1~8=0xf,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xf,0x3,0011 EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xf,0x2,HS CONFIG1H~1~11=0xf,0x1,XT CONFIG1H~1~12=0xf,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x8,4.2V CONFIG2L~3~4=0x18,0x0,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1e,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1e,0x1e,1:32768 CONFIG2H~2~2=0x1e,0x1c,1:16384 CONFIG2H~2~3=0x1e,0x1a,1:8192 CONFIG2H~2~4=0x1e,0x18,1:4096 CONFIG2H~2~5=0x1e,0x16,1:2048 CONFIG2H~2~6=0x1e,0x14,1:1024 CONFIG2H~2~7=0x1e,0x12,1:512 CONFIG2H~2~8=0x1e,0x10,1:256 CONFIG2H~2~9=0x1e,0xe,1:128 CONFIG2H~2~10=0x1e,0xc,1:64 CONFIG2H~2~11=0x1e,0xa,1:32 CONFIG2H~2~12=0x1e,0x8,1:16 CONFIG2H~2~13=0x1e,0x6,1:8 CONFIG2H~2~14=0x1e,0x4,1:4 CONFIG2H~2~15=0x1e,0x2,1:2 CONFIG2H~2~16=0x1e,0x0,1:1 CONFIG3L_unused=0x0 CONFIG3L~1=PMODE,0x3,Processor Mode CONFIG3L~2=BW,0x40,Bus Width CONFIG3L~3=WAIT,0x80,External Bus Wait CONFIG3L~1~1=0x3,0x3,Microcontroller CONFIG3L~1~2=0x3,0x2,Microprocessor CONFIG3L~1~3=0x3,0x1,Microprocessor w/Boot CONFIG3L~1~4=0x3,0x0,Ext Microcontroller CONFIG3L~2~1=0x40,0x40,16-bit external CONFIG3L~2~2=0x40,0x0,8-bit external CONFIG3L~3~1=0x80,0x80,Disabled CONFIG3L~3~2=0x80,0x0,Enabled CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=LPT1OSC,0x4,Low Power Timer1 Osc enable CONFIG3H~3=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RE7 CONFIG3H~2~1=0x4,0x4,Enabled CONFIG3H~2~2=0x4,0x0,Disabled CONFIG3H~3~1=0x80,0x80,MCLR Enabled, RG5 Disabled CONFIG3H~3~2=0x80,0x0,MCLR Disabled, RG5 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=XINST,0x40,Extended Instruction Set Enable bit CONFIG4L~3=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x40,0x40,Enabled CONFIG4L~2~2=0x40,0x0,Disabled CONFIG4L~3~1=0x80,0x80,Disabled CONFIG4L~3~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00000-03FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00000-03FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F85K22] pgmmem=0x0 ~pgmmem=0x7fff cfgmem=0x300000 ~cfgmem=0x30000d userid=0x200000 ~userid=0x200007 eedata=0x0 ~eedata=0x3ff devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0x5360 configslots=14 0x300000=CONFIG1L 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004=CONFIG3L 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000a=CONFIG6L 0x30000b=CONFIG6H 0x30000c=CONFIG7L 0x30000d=CONFIG7H CONFIG1L_unused=0x0 CONFIG1L~1=RETEN,0x1,VREG Sleep Enable bit CONFIG1L~2=SOSCEL,0x18,SOSC Power Selection and mode Configuration bits CONFIG1L~3=XINST,0x40,Extended Instruction Set CONFIG1L~1~1=0x1,0x1,Enabled CONFIG1L~1~2=0x1,0x0,Disabled CONFIG1L~2~1=0x18,0x18,High Power SOSC circuit selected CONFIG1L~2~2=0x18,0x8,Low Power SOSC circuit selected CONFIG1L~2~3=0x18,0x10,Digital (SCLKI) mode CONFIG1L~3~1=0x40,0x40,Enabled CONFIG1L~3~2=0x40,0x0,Disabled CONFIG1H_unused=0x0 CONFIG1H~1=FOSC,0xf,Oscillator CONFIG1H~2=PLLCFG,0x10,PLL x4 Enable bit CONFIG1H~3=PRCKEN,0x20,Primary Clock Enable bit CONFIG1H~4=FCMEN,0x40,Fail-Safe Clock Monitor CONFIG1H~5=IESO,0x80,Internal External Oscillator Switch Over Mode CONFIG1H~1~1=0xf,0xd,EC oscillator (Low power, DC - 160 kHz) CONFIG1H~1~2=0xf,0xc,EC oscillator, CLKOUT function on OSC2 (Low power, DC - 160 kHz) CONFIG1H~1~3=0xf,0xb,EC oscillator (Medium power, 160 kHz - 4 MHz) CONFIG1H~1~4=0xf,0xa,EC oscillator, CLKOUT function on OSC2 (Medium power, 160 kHz - 4 MHz) CONFIG1H~1~5=0xf,0x9,Internal RC oscillator, CLKOUT function on OSC2 CONFIG1H~1~6=0xf,0x8,Internal RC oscillator CONFIG1H~1~7=0xf,0x5,EC oscillator (High power, 16 MHz - 25 MHz) CONFIG1H~1~8=0xf,0x4,EC oscillator, CLKOUT function on OSC2 (High power, 16 MHz - 25 MHz) CONFIG1H~1~9=0xf,0x3,HS oscillator (Medium power, 4 MHz - 16 MHz) CONFIG1H~1~10=0xf,0x2,HS oscillator (High power, 16 MHz - 25 MHz) CONFIG1H~1~11=0xf,0x1,XT oscillator CONFIG1H~1~12=0xf,0x0,LP oscillator CONFIG1H~1~13=0x7,0x7,External RC oscillator CONFIG1H~1~14=0x7,0x6,External RC oscillator, CLKOUT function on OSC2 CONFIG1H~2~1=0x10,0x10,Enabled CONFIG1H~2~2=0x10,0x0,Disabled CONFIG1H~3~1=0x20,0x0,Disabled CONFIG1H~3~2=0x20,0x20,Enabled CONFIG1H~4~1=0x40,0x0,Disabled CONFIG1H~4~2=0x40,0x40,Enabled CONFIG1H~5~1=0x80,0x0,Disabled CONFIG1H~5~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PWRTEN,0x1,Power Up Timer CONFIG2L~2=BOREN,0x6,Brown Out Detect CONFIG2L~3=BORV,0x18,Brown-out Reset Voltage bits CONFIG2L~4=BORPWR,0x60,BORMV Power level CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active, disabled in SLEEP, SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,1.8V CONFIG2L~3~2=0x18,0x10,2.0V CONFIG2L~3~3=0x18,0x8,2.7V CONFIG2L~3~4=0x18,0x0,3.0V CONFIG2L~4~1=0x60,0x60,ZPBORMV instead of BORMV is selected CONFIG2L~4~2=0x60,0x40,BORMV set to high power level CONFIG2L~4~3=0x60,0x20,BORMV set to medium power level CONFIG2L~4~4=0x60,0x0,BORMV set to low power level CONFIG2H_unused=0x0 CONFIG2H~1=WDTEN,0x3,Watchdog Timer CONFIG2H~2=WDTPS,0x7c,Watchdog Postscaler CONFIG2H~1~1=0x3,0x3,Enabled in hardware, SWDTEN disabled CONFIG2H~1~2=0x3,0x2,Enabled while active, disabled in SLEEP, SWDTEN disabled CONFIG2H~1~3=0x3,0x1,Controlled with SWDTEN bit CONFIG2H~1~4=0x3,0x0,Disabled in hardware, SWDTEN disabled CONFIG2H~2~1=0x7c,0x7c,1:1048576 CONFIG2H~2~2=0x7c,0x4c,1:524288 CONFIG2H~2~3=0x7c,0x48,1:262144 CONFIG2H~2~4=0x7c,0x44,1:131072 CONFIG2H~2~5=0x7c,0x40,1:65536 CONFIG2H~2~6=0x7c,0x3c,1:32768 CONFIG2H~2~7=0x7c,0x38,1:16384 CONFIG2H~2~8=0x7c,0x34,1:8192 CONFIG2H~2~9=0x7c,0x30,1:4096 CONFIG2H~2~10=0x7c,0x2c,1:2048 CONFIG2H~2~11=0x7c,0x28,1:1024 CONFIG2H~2~12=0x7c,0x24,1:512 CONFIG2H~2~13=0x7c,0x20,1:256 CONFIG2H~2~14=0x7c,0x1c,1:128 CONFIG2H~2~15=0x7c,0x18,1:64 CONFIG2H~2~16=0x7c,0x14,1:32 CONFIG2H~2~17=0x7c,0x10,1:16 CONFIG2H~2~18=0x7c,0xc,1:8 CONFIG2H~2~19=0x7c,0x8,1:4 CONFIG2H~2~20=0x7c,0x4,1:2 CONFIG2H~2~21=0x7c,0x0,1:1 CONFIG3L_unused=0x0 CONFIG3L~1=RTCOSC,0x1,RTCC Clock Select CONFIG3L~2=EASHFT,0x8,External Address Shift bit CONFIG3L~3=ABW,0x30,Address Bus Width Select bits CONFIG3L~4=BW,0x40,Data Bus Width CONFIG3L~5=WAIT,0x80,External Bus Wait CONFIG3L~1~1=0x1,0x1,RTCC uses T1OSC/T1CKI CONFIG3L~1~2=0x1,0x0,RTCC uses INTRC CONFIG3L~2~1=0x8,0x8,Enabled CONFIG3L~2~2=0x8,0x0,Disabled CONFIG3L~3~1=0x30,0x30,20-bit address bus CONFIG3L~3~2=0x30,0x20,16-bit address bus CONFIG3L~3~3=0x30,0x10,12-bit address bus CONFIG3L~3~4=0x30,0x0,8-bit address bus CONFIG3L~4~1=0x40,0x40,16-bit external bus mode CONFIG3L~4~2=0x40,0x0,8-bit external bus mode CONFIG3L~5~1=0x80,0x80,Disabled CONFIG3L~5~2=0x80,0x0,Enabled CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MX,0x1,CCP2 Mux CONFIG3H~2=ECCPMX,0x2,ECCP Mux CONFIG3H~3=MSSPMSK,0x8,MSSP address masking CONFIG3H~4=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RE7-Microcontroller Mode/RB3-All other modes CONFIG3H~2~1=0x2,0x2,Enhanced CCP1/3 [P1B/P1C/P3B/P3C] muxed with RE6/RE5/RE4/RE3 CONFIG3H~2~2=0x2,0x0,Enhanced CCP1/3 [P1B/P1C/P3B/P3C] muxed with RH7/RH6/RH5/RH4 CONFIG3H~3~1=0x8,0x8,7 Bit address masking mode CONFIG3H~3~2=0x8,0x0,5 bit address masking mode CONFIG3H~4~1=0x80,0x80,MCLR Enabled, RG5 Disabled CONFIG3H~4~2=0x80,0x0,MCLR Disabled, RG5 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVREN,0x1,Stack Overflow Reset CONFIG4L~2=BBSIZ0,0x10,Boot Block Size CONFIG4L~3=DEBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x10,0x10,2K word Boot Block size CONFIG4L~2~2=0x10,0x0,1K word Boot Block size CONFIG4L~3~1=0x80,0x80,Disabled CONFIG4L~3~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP0,0x1,Code Protect 00800-017FF CONFIG5L~2=CP1,0x2,Code Protect 01800-03FFF CONFIG5L~3=CP2,0x4,Code Protect 04000-05FFF CONFIG5L~4=CP3,0x8,Code Protect 06000-07FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x0,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x0,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x0,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x0,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPB,0x40,Code Protect Boot CONFIG5H~2=CPD,0x80,Data EE Read Protect CONFIG5H~1~1=0x40,0x40,Disabled CONFIG5H~1~2=0x40,0x0,Enabled CONFIG5H~2~1=0x80,0x80,Disabled CONFIG5H~2~2=0x80,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT0,0x1,Table Write Protect 00800-017FF CONFIG6L~2=WRT1,0x2,Table Write Protect 01800-03FFF CONFIG6L~3=WRT2,0x4,Table Write Protect 04000-05FFF CONFIG6L~4=WRT3,0x8,Table Write Protect 06000-07FFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x0,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x0,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x0,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x0,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTC,0x20,Config. Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTD,0x80,Data EE Write Protect CONFIG6H~1~1=0x20,0x20,Disabled CONFIG6H~1~2=0x20,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x80,0x80,Disabled CONFIG6H~3~2=0x80,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBRT0,0x1,Table Read Protect 00800-017FF CONFIG7L~2=EBRT1,0x2,Table Read Protect 01800-03FFF CONFIG7L~3=EBRT2,0x4,Table Read Protect 04000-05FFF CONFIG7L~4=EBRT3,0x8,Table Read Protect 06000-07FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x0,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x0,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x0,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x0,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBRTB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F85K90] pgmmem=0x0 ~pgmmem=0x7fff cfgmem=0x300000 ~cfgmem=0x30000d userid=0x200000 ~userid=0x200007 eedata=0x0 ~eedata=0x3ff devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0x52a0 configslots=14 0x300000=CONFIG1L 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004=CONFIG3L 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000a=CONFIG6L 0x30000b=CONFIG6H 0x30000c=CONFIG7L 0x30000d=CONFIG7H CONFIG1L_unused=0x0 CONFIG1L~1=RETEN,0x1,VREG Sleep Enable bit CONFIG1L~2=SOSCEL,0x18,SOSC Power Selection and mode Configuration bits CONFIG1L~3=XINST,0x40,Extended Instruction Set CONFIG1L~1~1=0x1,0x1,Enabled CONFIG1L~1~2=0x1,0x0,Disabled CONFIG1L~2~1=0x18,0x18,High Power SOSC circuit selected CONFIG1L~2~2=0x18,0x8,Low Power SOSC circuit selected CONFIG1L~2~3=0x18,0x10,Digital (SCLKI) mode CONFIG1L~3~1=0x40,0x40,Enabled CONFIG1L~3~2=0x40,0x0,Disabled CONFIG1H_unused=0x0 CONFIG1H~1=FOSC,0xf,Oscillator CONFIG1H~2=PLLCFG,0x10,PLL x4 Enable bit CONFIG1H~3=PRCKEN,0x20,Primary Clock Enable bit CONFIG1H~4=FCMEN,0x40,Fail-Safe Clock Monitor CONFIG1H~5=IESO,0x80,Internal External Oscillator Switch Over Mode CONFIG1H~1~1=0x7,0x7,External RC oscillator CONFIG1H~1~2=0x7,0x6,External RC oscillator, CLKOUT function on OSC2 CONFIG1H~1~3=0xf,0xd,EC oscillator (Low power, DC - 160 kHz) CONFIG1H~1~4=0xf,0xc,EC oscillator, CLKOUT function on OSC2 (Low power, DC - 160 kHz) CONFIG1H~1~5=0xf,0xb,EC oscillator (Medium power, 160 kHz - 4 MHz) CONFIG1H~1~6=0xf,0xa,EC oscillator, CLKOUT function on OSC2 (Medium power, 160 kHz - 4 MHz) CONFIG1H~1~7=0xf,0x9,Internal RC oscillator, CLKOUT function on OSC2 CONFIG1H~1~8=0xf,0x8,Internal RC oscillator CONFIG1H~1~9=0xf,0x5,EC oscillator (High power, 16 MHz - 25 MHz) CONFIG1H~1~10=0xf,0x4,EC oscillator, CLKOUT function on OSC2 (High power, 16 MHz - 25 MHz) CONFIG1H~1~11=0xf,0x3,HS oscillator (Medium power, 4 MHz - 16 MHz) CONFIG1H~1~12=0xf,0x2,HS oscillator (High power, 16 MHz - 25 MHz) CONFIG1H~1~13=0xf,0x1,XT oscillator CONFIG1H~1~14=0xf,0x0,LP oscillator CONFIG1H~2~1=0x10,0x10,Enabled CONFIG1H~2~2=0x10,0x0,Disabled CONFIG1H~3~1=0x20,0x0,Disabled CONFIG1H~3~2=0x20,0x20,Enabled CONFIG1H~4~1=0x40,0x0,Disabled CONFIG1H~4~2=0x40,0x40,Enabled CONFIG1H~5~1=0x80,0x0,Disabled CONFIG1H~5~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PWRTEN,0x1,Power Up Timer CONFIG2L~2=BOREN,0x6,Brown Out Detect CONFIG2L~3=BORV,0x18,Brown-out Reset Voltage bits CONFIG2L~4=BORPWR,0x60,BORMV Power level CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active, disabled in SLEEP, SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,1.8V CONFIG2L~3~2=0x18,0x10,2.0V CONFIG2L~3~3=0x18,0x8,2.7V CONFIG2L~3~4=0x18,0x0,3.0V CONFIG2L~4~1=0x60,0x60,ZPBORMV instead of BORMV is selected CONFIG2L~4~2=0x60,0x40,BORMV set to high power level CONFIG2L~4~3=0x60,0x20,BORMV set to medium power level CONFIG2L~4~4=0x60,0x0,BORMV set to low power level CONFIG2H_unused=0x0 CONFIG2H~1=WDTEN,0x3,Watchdog Timer CONFIG2H~2=WDTPS,0x7c,Watchdog Postscaler CONFIG2H~1~1=0x3,0x3,Enabled in hardware, SWDTEN disabled CONFIG2H~1~2=0x3,0x2,Enabled while active, disabled in SLEEP, SWDTEN disabled CONFIG2H~1~3=0x3,0x1,Controlled with SWDTEN bit CONFIG2H~1~4=0x3,0x0,Disabled in hardware, SWDTEN disabled CONFIG2H~2~1=0x7c,0x7c,1:1048576 CONFIG2H~2~2=0x7c,0x4c,1:524288 CONFIG2H~2~3=0x7c,0x48,1:262144 CONFIG2H~2~4=0x7c,0x44,1:131072 CONFIG2H~2~5=0x7c,0x40,1:65536 CONFIG2H~2~6=0x7c,0x3c,1:32768 CONFIG2H~2~7=0x7c,0x38,1:16384 CONFIG2H~2~8=0x7c,0x34,1:8192 CONFIG2H~2~9=0x7c,0x30,1:4096 CONFIG2H~2~10=0x7c,0x2c,1:2048 CONFIG2H~2~11=0x7c,0x28,1:1024 CONFIG2H~2~12=0x7c,0x24,1:512 CONFIG2H~2~13=0x7c,0x20,1:256 CONFIG2H~2~14=0x7c,0x1c,1:128 CONFIG2H~2~15=0x7c,0x18,1:64 CONFIG2H~2~16=0x7c,0x14,1:32 CONFIG2H~2~17=0x7c,0x10,1:16 CONFIG2H~2~18=0x7c,0xc,1:8 CONFIG2H~2~19=0x7c,0x8,1:4 CONFIG2H~2~20=0x7c,0x4,1:2 CONFIG2H~2~21=0x7c,0x0,1:1 CONFIG3L_unused=0x0 CONFIG3L~1=RTCOSC,0x1,RTCC Clock Select CONFIG3L~1~1=0x1,0x1,RTCC uses T1OSC/T1CKI CONFIG3L~1~2=0x1,0x0,RTCC uses INTRC CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MX,0x1,CCP2 Mux CONFIG3H~2=ECCPMX,0x2,ECCP Mux CONFIG3H~3=MSSPMSK,0x8,MSSP address masking CONFIG3H~4=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RE7-Microcontroller Mode/RB3-All other modes CONFIG3H~2~1=0x2,0x2,Enhanced CCP1/3 [P1B/P1C/P3B/P3C] muxed with RE6/RE5/RE4/RE3 CONFIG3H~2~2=0x2,0x0,Enhanced CCP1/3 [P1B/P1C/P3B/P3C] muxed with RH7/RH6/RH5/RH4 CONFIG3H~3~1=0x8,0x8,7 Bit address masking mode CONFIG3H~3~2=0x8,0x0,5 bit address masking mode CONFIG3H~4~1=0x80,0x80,MCLR Enabled, RG5 Disabled CONFIG3H~4~2=0x80,0x0,MCLR Disabled, RG5 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVREN,0x1,Stack Overflow Reset CONFIG4L~2=BBSIZ0,0x10,Boot Block Size CONFIG4L~3=DEBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x10,0x10,2K word Boot Block size CONFIG4L~2~2=0x10,0x0,1K word Boot Block size CONFIG4L~3~1=0x80,0x80,Disabled CONFIG4L~3~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP0,0x1,Code Protect 00800-017FF CONFIG5L~2=CP1,0x2,Code Protect 01800-03FFF CONFIG5L~3=CP2,0x4,Code Protect 04000-05FFF CONFIG5L~4=CP3,0x8,Code Protect 06000-07FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x0,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x0,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x0,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x0,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPB,0x40,Code Protect Boot CONFIG5H~2=CPD,0x80,Data EE Read Protect CONFIG5H~1~1=0x40,0x40,Disabled CONFIG5H~1~2=0x40,0x0,Enabled CONFIG5H~2~1=0x80,0x80,Disabled CONFIG5H~2~2=0x80,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT0,0x1,Table Write Protect 00800-017FF CONFIG6L~2=WRT1,0x2,Table Write Protect 01800-03FFF CONFIG6L~3=WRT2,0x4,Table Write Protect 04000-05FFF CONFIG6L~4=WRT3,0x8,Table Write Protect 06000-07FFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x0,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x0,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x0,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x0,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTC,0x20,Config. Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTD,0x80,Data EE Write Protect CONFIG6H~1~1=0x20,0x20,Disabled CONFIG6H~1~2=0x20,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x80,0x80,Disabled CONFIG6H~3~2=0x80,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBRT0,0x1,Table Read Protect 00800-017FF CONFIG7L~2=EBRT1,0x2,Table Read Protect 01800-03FFF CONFIG7L~3=EBRT2,0x4,Table Read Protect 04000-05FFF CONFIG7L~4=EBRT3,0x8,Table Read Protect 06000-07FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x0,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x0,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x0,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x0,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBRTB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F8628] pgmmem=0x4650 ~pgmmem=0x1fffff cfgmem=0x300000 ~cfgmem=0x30000d userid=0x200000 ~userid=0x200007 eedata=0x0 ~eedata=0x3ff devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0x49e0 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004=CONFIG3L 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000a=CONFIG6L 0x30000b=CONFIG6H 0x30000c=CONFIG7L 0x30000d=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xf,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xc,0xc,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xe,0xa,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xf,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xf,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xf,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xf,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xf,0x5,EC-Port on RA6 CONFIG1H~1~8=0xf,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xf,0x3,0011 EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xf,0x2,HS CONFIG1H~1~11=0xf,0x1,XT CONFIG1H~1~12=0xf,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x8,4.2V CONFIG2L~3~4=0x18,0x0,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1e,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1e,0x1e,1:32768 CONFIG2H~2~2=0x1e,0x1c,1:16384 CONFIG2H~2~3=0x1e,0x1a,1:8192 CONFIG2H~2~4=0x1e,0x18,1:4096 CONFIG2H~2~5=0x1e,0x16,1:2048 CONFIG2H~2~6=0x1e,0x14,1:1024 CONFIG2H~2~7=0x1e,0x12,1:512 CONFIG2H~2~8=0x1e,0x10,1:256 CONFIG2H~2~9=0x1e,0xe,1:128 CONFIG2H~2~10=0x1e,0xc,1:64 CONFIG2H~2~11=0x1e,0xa,1:32 CONFIG2H~2~12=0x1e,0x8,1:16 CONFIG2H~2~13=0x1e,0x6,1:8 CONFIG2H~2~14=0x1e,0x4,1:4 CONFIG2H~2~15=0x1e,0x2,1:2 CONFIG2H~2~16=0x1e,0x0,1:1 CONFIG3L_unused=0x0 CONFIG3L~1=PMODE,0x3,Processor Mode CONFIG3L~2=ABW,0x30,Address Bus Width CONFIG3L~3=BW,0x40,Bus Width CONFIG3L~4=WAIT,0x80,External Bus Wait CONFIG3L~1~1=0x3,0x3,Microcontroller CONFIG3L~1~2=0x3,0x2,Microprocessor CONFIG3L~1~3=0x3,0x1,Microprocessor w/Boot CONFIG3L~1~4=0x3,0x0,Ext Microcontroller CONFIG3L~2~1=0x30,0x30,20-bit CONFIG3L~2~2=0x30,0x20,16-bit CONFIG3L~2~3=0x30,0x10,12-bit CONFIG3L~2~4=0x30,0x0,8-bit CONFIG3L~3~1=0x40,0x40,16-bit external bus CONFIG3L~3~2=0x40,0x0,8-bit external bus CONFIG3L~4~1=0x80,0x80,Disabled CONFIG3L~4~2=0x80,0x0,Enabled CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=ECCPMX,0x2,ECCP Mux CONFIG3H~3=LPT1OSC,0x4,Low Power Timer1 Osc enable CONFIG3H~4=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RE7-Microcontroller Mode/RB3-All other modes CONFIG3H~2~1=0x2,0x2,Enhanced CCP1/3 [P1B/P1C/P3B/P3C] muxed with RE6/RE5/RE4/RE3 CONFIG3H~2~2=0x2,0x0,Enhanced CCP1/3 [P1B/P1C/P3B/P3C] muxed with RH7/RH6/RH5/RH4 CONFIG3H~3~1=0x4,0x4,Enabled CONFIG3H~3~2=0x4,0x0,Disabled CONFIG3H~4~1=0x80,0x80,MCLR Enabled, RG5 Disabled CONFIG3H~4~2=0x80,0x0,MCLR Disabled, RG5 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=BBSIZ,0x30,Boot Block Size CONFIG4L~4=XINST,0x40,Extended Instruction Set Enable bit CONFIG4L~5=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x20,0x20,4K Words (8 Kbytes) CONFIG4L~3~2=0x30,0x10,2K Words (4 Kbytes) CONFIG4L~3~3=0x30,0x0,1K Words (2 Kbytes) CONFIG4L~4~1=0x40,0x40,Enabled CONFIG4L~4~2=0x40,0x0,Disabled CONFIG4L~5~1=0x80,0x80,Disabled CONFIG4L~5~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-03FFF CONFIG5L~2=CP_1,0x2,Code Protect 04000-07FFF CONFIG5L~3=CP_2,0x4,Code Protect 08000-0BFFF CONFIG5L~4=CP_3,0x8,Code Protect 0C000-0FFFF CONFIG5L~5=CP_4,0x10,Code Protect 10000-13FFF CONFIG5L~6=CP_5,0x20,Code Protect 14000-17FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x0,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x0,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x0,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x0,Enabled CONFIG5L~5~1=0x10,0x10,Disabled CONFIG5L~5~2=0x10,0x0,Enabled CONFIG5L~6~1=0x20,0x20,Disabled CONFIG5L~6~2=0x20,0x0,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPB,0x40,Code Protect Boot CONFIG5H~2=CPD,0x80,Data EE Read Protect CONFIG5H~1~1=0x40,0x40,Disabled CONFIG5H~1~2=0x40,0x0,Enabled CONFIG5H~2~1=0x80,0x80,Disabled CONFIG5H~2~2=0x80,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-03FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 04000-07FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 08000-0BFFF CONFIG6L~4=WRT_3,0x8,Table Write Protect 0C000-0FFFF CONFIG6L~5=WRT_4,0x10,Table Write Protect 10000-13FFF CONFIG6L~6=WRT_5,0x20,Table Write Protect 14000-17FFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x0,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x0,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x0,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x0,Enabled CONFIG6L~5~1=0x10,0x10,Disabled CONFIG6L~5~2=0x10,0x0,Enabled CONFIG6L~6~1=0x20,0x20,Disabled CONFIG6L~6~2=0x20,0x0,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTC,0x20,Config. Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTD,0x80,Data EE Write Protect CONFIG6H~1~1=0x20,0x20,Disabled CONFIG6H~1~2=0x20,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x80,0x80,Disabled CONFIG6H~3~2=0x80,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-03FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 04000-07FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 08000-0BFFF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 0C000-0FFFF CONFIG7L~5=EBTR_4,0x10,Table Read Protect 10000-13FFF CONFIG7L~6=EBTR_5,0x20,Table Read Protect 14000-17FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x0,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x0,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x0,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x0,Enabled CONFIG7L~5~1=0x10,0x10,Disabled CONFIG7L~5~2=0x10,0x0,Enabled CONFIG7L~6~1=0x20,0x20,Disabled CONFIG7L~6~2=0x20,0x0,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F86J90] pgmmem=0x20000 ~pgmmem=0x1fffff cfgmem=0xfff8 ~cfgmem=0xffff userid= ~userid= eedata= ~eedata= devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0x5080 configslots=8 0xfff8=CONFIG1L 0xfff9=CONFIG1H 0xfffa=CONFIG2L 0xfffb=CONFIG2H 0xfffc=CONFIG3L 0xfffd=CONFIG3H 0xfffe= 0xffff= CONFIG1L_unused=0x0 CONFIG1L~1=WDTEN,0x1,Watchdog Timer CONFIG1L~2=STVREN,0x20,Stack Overflow Reset CONFIG1L~3=XINST,0x40,Extended Instruction Set Enable bit CONFIG1L~4=DEBUG,0x80,Background Debugger Enable bit CONFIG1L~1~1=0x1,0x1,Enabled CONFIG1L~1~2=0x1,0x0,Disabled CONFIG1L~2~1=0x20,0x20,Enabled CONFIG1L~2~2=0x20,0x0,Disabled CONFIG1L~3~1=0x40,0x40,Enabled CONFIG1L~3~2=0x40,0x0,Disabled CONFIG1L~4~1=0x80,0x80,Disabled CONFIG1L~4~2=0x80,0x0,Enabled CONFIG1H_unused=0x0 CONFIG1H~1=CP0,0x4,Code Protect CONFIG1H~2=SIGN,0x8,Config Word Signature Bit CONFIG1H~3=RESERVED,0xf0,RESERVED CONFIG1H~1~1=0x4,0x4,Disabled CONFIG1H~1~2=0x4,0x0,Enabled CONFIG1H~2~1=0x8,0x8,Bulk erase of memory not conducated CONFIG1H~2~2=0x8,0x0,Bulk erase of memory area complete CONFIG1H~3~1=0xf0,0xf0,RESERVED CONFIG2L_unused=0x0 CONFIG2L~1=OSC,0x7,Oscillator Selection bits CONFIG2L~2=T1DIG,0x8,Secondary Clock Source T1OSCEN Enforcement CONFIG2L~3=LPT1OSC,0x10,Low-Power Timer1 Oscillator Enable bit CONFIG2L~4=FCMEN,0x40,Fail-Safe Clock Monitor Enable bit CONFIG2L~5=IESO,0x80,Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit CONFIG2L~1~1=0x7,0x7,EC Oscillator with PLL CONFIG2L~1~2=0x7,0x6,EC Oscillator with clock out on RA6 CONFIG2L~1~3=0x7,0x5,HS oscillator, PLL enabled CONFIG2L~1~4=0x7,0x4,HS oscillator CONFIG2L~1~5=0x7,0x3,INTOSC with PLL enabled, CLKOUT on RA6 and port function on RA7 CONFIG2L~1~6=0x7,0x2,Internal oscillator, CLKOUT on RA6 and port function on RA7 CONFIG2L~1~7=0x7,0x1,INTOSC with PLL enabled, port function on RA6 and RA7 CONFIG2L~1~8=0x7,0x0,Internal oscillator, port function on RA6 and RA7 CONFIG2L~2~1=0x8,0x8,Enabled CONFIG2L~2~2=0x8,0x0,Disabled CONFIG2L~3~1=0x10,0x0,Enabled CONFIG2L~3~2=0x10,0x10,Disabled CONFIG2L~4~1=0x40,0x0,Disabled CONFIG2L~4~2=0x40,0x40,Enabled CONFIG2L~5~1=0x80,0x0,Disabled CONFIG2L~5~2=0x80,0x80,Enabled CONFIG2H_unused=0x0 CONFIG2H~1=WDTPS,0xf,Watchdog Timer Postscaler Select bits CONFIG2H~2=RESERVED,0xf0,RESERVED CONFIG2H~1~1=0xf,0xf,1:32768 CONFIG2H~1~2=0xf,0xe,1:16384 CONFIG2H~1~3=0xf,0xd,1:8192 CONFIG2H~1~4=0xf,0xc,1:4096 CONFIG2H~1~5=0xf,0xb,1:2048 CONFIG2H~1~6=0xf,0xa,1:1024 CONFIG2H~1~7=0xf,0x9,1:512 CONFIG2H~1~8=0xf,0x8,1:256 CONFIG2H~1~9=0xf,0x7,1:128 CONFIG2H~1~10=0xf,0x6,1:64 CONFIG2H~1~11=0xf,0x5,1:32 CONFIG2H~1~12=0xf,0x4,1:16 CONFIG2H~1~13=0xf,0x3,1:8 CONFIG2H~1~14=0xf,0x2,1:4 CONFIG2H~1~15=0xf,0x1,1:2 CONFIG2H~1~16=0xf,0x0,1:1 CONFIG2H~2~1=0xf0,0xf0,RESERVED CONFIG3L_unused=0x0 CONFIG3L~1=RTCSOSC,0x2,RTCC Reference Clock Select bit CONFIG3L~1~1=0x2,0x2,RTCC uses T1OSC/T1CKI as reference clock CONFIG3L~1~2=0x2,0x0,RTCC uses INTOSC/INTRC as reference clock CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MX,0x1,CCP2 MUX CONFIG3H~2=RESERVED,0xf0,RESERVED CONFIG3H~1~1=0x1,0x0,RE7 / RB3 CONFIG3H~1~2=0x1,0x1,RC1 CONFIG3H~2~1=0xf0,0xf0,RESERVED erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F86J93] pgmmem=0x20000 ~pgmmem=0x1fffff cfgmem=0xfff8 ~cfgmem=0xffff userid= ~userid= eedata= ~eedata= devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0x50c0 configslots=8 0xfff8=CONFIG1L 0xfff9=CONFIG1H 0xfffa=CONFIG2L 0xfffb=CONFIG2H 0xfffc=CONFIG3L 0xfffd=CONFIG3H 0xfffe= 0xffff= CONFIG1L_unused=0x0 CONFIG1L~1=WDTEN,0x1,Watchdog Timer CONFIG1L~2=STVREN,0x20,Stack Overflow Reset CONFIG1L~3=XINST,0x40,Extended Instruction Set Enable bit CONFIG1L~4=DEBUG,0x80,Background Debugger Enable bit CONFIG1L~1~1=0x1,0x1,Enabled CONFIG1L~1~2=0x1,0x0,Disabled CONFIG1L~2~1=0x20,0x20,Enabled CONFIG1L~2~2=0x20,0x0,Disabled CONFIG1L~3~1=0x40,0x40,Enabled CONFIG1L~3~2=0x40,0x0,Disabled CONFIG1L~4~1=0x80,0x80,Disabled CONFIG1L~4~2=0x80,0x0,Enabled CONFIG1H_unused=0x0 CONFIG1H~1=CP0,0x4,Code Protect CONFIG1H~2=SIGN,0x8,Config Word Signature Bit CONFIG1H~3=RESERVED,0xf0,RESERVED CONFIG1H~1~1=0x4,0x4,Disabled CONFIG1H~1~2=0x4,0x0,Enabled CONFIG1H~2~1=0x8,0x8,Bulk erase of memory not conducated CONFIG1H~2~2=0x8,0x0,Bulk erase of memory area complete CONFIG1H~3~1=0xf0,0xf0,RESERVED CONFIG2L_unused=0x0 CONFIG2L~1=OSC,0x7,Oscillator Selection bits CONFIG2L~2=T1DIG,0x8,Secondary Clock Source T1OSCEN Enforcement CONFIG2L~3=LPT1OSC,0x10,Low-Power Timer1 Oscillator Enable bit CONFIG2L~4=FCMEN,0x40,Fail-Safe Clock Monitor Enable bit CONFIG2L~5=IESO,0x80,Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit CONFIG2L~1~1=0x7,0x7,EC Oscillator with PLL CONFIG2L~1~2=0x7,0x6,EC Oscillator with clock out on RA6 CONFIG2L~1~3=0x7,0x5,HS oscillator, PLL enabled CONFIG2L~1~4=0x7,0x4,HS oscillator CONFIG2L~1~5=0x7,0x3,INTOSC with PLL enabled, CLKOUT on RA6 and port function on RA7 CONFIG2L~1~6=0x7,0x2,Internal oscillator, CLKOUT on RA6 and port function on RA7 CONFIG2L~1~7=0x7,0x1,INTOSC with PLL enabled, port function on RA6 and RA7 CONFIG2L~1~8=0x7,0x0,Internal oscillator, port function on RA6 and RA7 CONFIG2L~2~1=0x8,0x8,Enabled CONFIG2L~2~2=0x8,0x0,Disabled CONFIG2L~3~1=0x10,0x0,Enabled CONFIG2L~3~2=0x10,0x10,Disabled CONFIG2L~4~1=0x40,0x0,Disabled CONFIG2L~4~2=0x40,0x40,Enabled CONFIG2L~5~1=0x80,0x0,Disabled CONFIG2L~5~2=0x80,0x80,Enabled CONFIG2H_unused=0x0 CONFIG2H~1=WDTPS,0xf,Watchdog Timer Postscaler Select bits CONFIG2H~2=RESERVED,0xf0,RESERVED CONFIG2H~1~1=0xf,0xf,1:32768 CONFIG2H~1~2=0xf,0xe,1:16384 CONFIG2H~1~3=0xf,0xd,1:8192 CONFIG2H~1~4=0xf,0xc,1:4096 CONFIG2H~1~5=0xf,0xb,1:2048 CONFIG2H~1~6=0xf,0xa,1:1024 CONFIG2H~1~7=0xf,0x9,1:512 CONFIG2H~1~8=0xf,0x8,1:256 CONFIG2H~1~9=0xf,0x7,1:128 CONFIG2H~1~10=0xf,0x6,1:64 CONFIG2H~1~11=0xf,0x5,1:32 CONFIG2H~1~12=0xf,0x4,1:16 CONFIG2H~1~13=0xf,0x3,1:8 CONFIG2H~1~14=0xf,0x2,1:4 CONFIG2H~1~15=0xf,0x1,1:2 CONFIG2H~1~16=0xf,0x0,1:1 CONFIG2H~2~1=0xf0,0xf0,RESERVED CONFIG3L_unused=0x0 CONFIG3L~1=RTCSOSC,0x2,RTCC Reference Clock Select bit CONFIG3L~1~1=0x2,0x2,RTCC uses T1OSC/T1CKI as reference clock CONFIG3L~1~2=0x2,0x0,RTCC uses INTOSC/INTRC as reference clock CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MX,0x1,CCP2 MUX CONFIG3H~2=RESERVED,0xf0,RESERVED CONFIG3H~1~1=0x1,0x0,RE7 / RB3 CONFIG3H~1~2=0x1,0x1,RC1 CONFIG3H~2~1=0xf0,0xf0,RESERVED erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F86K22] pgmmem=0x0 ~pgmmem=0xffff cfgmem=0x300000 ~cfgmem=0x30000d userid=0x200000 ~userid=0x200007 eedata=0x0 ~eedata=0x3ff devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0x5320 configslots=14 0x300000=CONFIG1L 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004=CONFIG3L 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000a=CONFIG6L 0x30000b=CONFIG6H 0x30000c=CONFIG7L 0x30000d=CONFIG7H CONFIG1L_unused=0x0 CONFIG1L~1=RETEN,0x1,VREG Sleep Enable bit CONFIG1L~2=SOSCEL,0x18,SOSC Power Selection and mode Configuration bits CONFIG1L~3=XINST,0x40,Extended Instruction Set CONFIG1L~1~1=0x1,0x1,Enabled CONFIG1L~1~2=0x1,0x0,Disabled CONFIG1L~2~1=0x18,0x18,High Power SOSC circuit selected CONFIG1L~2~2=0x18,0x8,Low Power SOSC circuit selected CONFIG1L~2~3=0x18,0x10,Digital (SCLKI) mode CONFIG1L~3~1=0x40,0x40,Enabled CONFIG1L~3~2=0x40,0x0,Disabled CONFIG1H_unused=0x0 CONFIG1H~1=FOSC,0xf,Oscillator CONFIG1H~2=PLLCFG,0x10,PLL x4 Enable bit CONFIG1H~3=PRCKEN,0x20,Primary Clock Enable bit CONFIG1H~4=FCMEN,0x40,Fail-Safe Clock Monitor CONFIG1H~5=IESO,0x80,Internal External Oscillator Switch Over Mode CONFIG1H~1~1=0xf,0xd,EC oscillator (Low power, DC - 160 kHz) CONFIG1H~1~2=0xf,0xc,EC oscillator, CLKOUT function on OSC2 (Low power, DC - 160 kHz) CONFIG1H~1~3=0xf,0xb,EC oscillator (Medium power, 160 kHz - 4 MHz) CONFIG1H~1~4=0xf,0xa,EC oscillator, CLKOUT function on OSC2 (Medium power, 160 kHz - 4 MHz) CONFIG1H~1~5=0xf,0x9,Internal RC oscillator, CLKOUT function on OSC2 CONFIG1H~1~6=0xf,0x8,Internal RC oscillator CONFIG1H~1~7=0xf,0x5,EC oscillator (High power, 16 MHz - 25 MHz) CONFIG1H~1~8=0xf,0x4,EC oscillator, CLKOUT function on OSC2 (High power, 16 MHz - 25 MHz) CONFIG1H~1~9=0xf,0x3,HS oscillator (Medium power, 4 MHz - 16 MHz) CONFIG1H~1~10=0xf,0x2,HS oscillator (High power, 16 MHz - 25 MHz) CONFIG1H~1~11=0xf,0x1,XT oscillator CONFIG1H~1~12=0xf,0x0,LP oscillator CONFIG1H~1~13=0x7,0x7,External RC oscillator CONFIG1H~1~14=0x7,0x6,External RC oscillator, CLKOUT function on OSC2 CONFIG1H~2~1=0x10,0x10,Enabled CONFIG1H~2~2=0x10,0x0,Disabled CONFIG1H~3~1=0x20,0x0,Disabled CONFIG1H~3~2=0x20,0x20,Enabled CONFIG1H~4~1=0x40,0x0,Disabled CONFIG1H~4~2=0x40,0x40,Enabled CONFIG1H~5~1=0x80,0x0,Disabled CONFIG1H~5~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PWRTEN,0x1,Power Up Timer CONFIG2L~2=BOREN,0x6,Brown Out Detect CONFIG2L~3=BORV,0x18,Brown-out Reset Voltage bits CONFIG2L~4=BORPWR,0x60,BORMV Power level CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active, disabled in SLEEP, SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,1.8V CONFIG2L~3~2=0x18,0x10,2.0V CONFIG2L~3~3=0x18,0x8,2.7V CONFIG2L~3~4=0x18,0x0,3.0V CONFIG2L~4~1=0x60,0x60,ZPBORMV instead of BORMV is selected CONFIG2L~4~2=0x60,0x40,BORMV set to high power level CONFIG2L~4~3=0x60,0x20,BORMV set to medium power level CONFIG2L~4~4=0x60,0x0,BORMV set to low power level CONFIG2H_unused=0x0 CONFIG2H~1=WDTEN,0x3,Watchdog Timer CONFIG2H~2=WDTPS,0x7c,Watchdog Postscaler CONFIG2H~1~1=0x3,0x3,Enabled in hardware, SWDTEN disabled CONFIG2H~1~2=0x3,0x2,Enabled while active, disabled in SLEEP, SWDTEN disabled CONFIG2H~1~3=0x3,0x1,Controlled with SWDTEN bit CONFIG2H~1~4=0x3,0x0,Disabled in hardware, SWDTEN disabled CONFIG2H~2~1=0x7c,0x7c,1:1048576 CONFIG2H~2~2=0x7c,0x4c,1:524288 CONFIG2H~2~3=0x7c,0x48,1:262144 CONFIG2H~2~4=0x7c,0x44,1:131072 CONFIG2H~2~5=0x7c,0x40,1:65536 CONFIG2H~2~6=0x7c,0x3c,1:32768 CONFIG2H~2~7=0x7c,0x38,1:16384 CONFIG2H~2~8=0x7c,0x34,1:8192 CONFIG2H~2~9=0x7c,0x30,1:4096 CONFIG2H~2~10=0x7c,0x2c,1:2048 CONFIG2H~2~11=0x7c,0x28,1:1024 CONFIG2H~2~12=0x7c,0x24,1:512 CONFIG2H~2~13=0x7c,0x20,1:256 CONFIG2H~2~14=0x7c,0x1c,1:128 CONFIG2H~2~15=0x7c,0x18,1:64 CONFIG2H~2~16=0x7c,0x14,1:32 CONFIG2H~2~17=0x7c,0x10,1:16 CONFIG2H~2~18=0x7c,0xc,1:8 CONFIG2H~2~19=0x7c,0x8,1:4 CONFIG2H~2~20=0x7c,0x4,1:2 CONFIG2H~2~21=0x7c,0x0,1:1 CONFIG3L_unused=0x0 CONFIG3L~1=RTCOSC,0x1,RTCC Clock Select CONFIG3L~2=EASHFT,0x8,External Address Shift bit CONFIG3L~3=ABW,0x30,Address Bus Width Select bits CONFIG3L~4=BW,0x40,Data Bus Width CONFIG3L~5=WAIT,0x80,External Bus Wait CONFIG3L~1~1=0x1,0x1,RTCC uses T1OSC/T1CKI CONFIG3L~1~2=0x1,0x0,RTCC uses INTRC CONFIG3L~2~1=0x8,0x8,Enabled CONFIG3L~2~2=0x8,0x0,Disabled CONFIG3L~3~1=0x30,0x30,20-bit address bus CONFIG3L~3~2=0x30,0x20,16-bit address bus CONFIG3L~3~3=0x30,0x10,12-bit address bus CONFIG3L~3~4=0x30,0x0,8-bit address bus CONFIG3L~4~1=0x40,0x40,16-bit external bus mode CONFIG3L~4~2=0x40,0x0,8-bit external bus mode CONFIG3L~5~1=0x80,0x80,Disabled CONFIG3L~5~2=0x80,0x0,Enabled CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MX,0x1,CCP2 Mux CONFIG3H~2=ECCPMX,0x2,ECCP Mux CONFIG3H~3=MSSPMSK,0x8,MSSP address masking CONFIG3H~4=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RE7-Microcontroller Mode/RB3-All other modes CONFIG3H~2~1=0x2,0x2,Enhanced CCP1/3 [P1B/P1C/P3B/P3C] muxed with RE6/RE5/RE4/RE3 CONFIG3H~2~2=0x2,0x0,Enhanced CCP1/3 [P1B/P1C/P3B/P3C] muxed with RH7/RH6/RH5/RH4 CONFIG3H~3~1=0x8,0x8,7 Bit address masking mode CONFIG3H~3~2=0x8,0x0,5 bit address masking mode CONFIG3H~4~1=0x80,0x80,MCLR Enabled, RG5 Disabled CONFIG3H~4~2=0x80,0x0,MCLR Disabled, RG5 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVREN,0x1,Stack Overflow Reset CONFIG4L~2=BBSIZ0,0x10,Boot Block Size CONFIG4L~3=DEBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x10,0x10,2K word Boot Block size CONFIG4L~2~2=0x10,0x0,1K word Boot Block size CONFIG4L~3~1=0x80,0x80,Disabled CONFIG4L~3~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP0,0x1,Code Protect 00800-03FFF CONFIG5L~2=CP1,0x2,Code Protect 04000-07FFF CONFIG5L~3=CP2,0x4,Code Protect 08000-0BFFF CONFIG5L~4=CP3,0x8,Code Protect 0C000-0FFFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x0,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x0,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x0,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x0,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPB,0x40,Code Protect Boot CONFIG5H~2=CPD,0x80,Data EE Read Protect CONFIG5H~1~1=0x40,0x40,Disabled CONFIG5H~1~2=0x40,0x0,Enabled CONFIG5H~2~1=0x80,0x80,Disabled CONFIG5H~2~2=0x80,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT0,0x1,Table Write Protect 00800-03FFF CONFIG6L~2=WRT1,0x2,Table Write Protect 04000-07FFF CONFIG6L~3=WRT2,0x4,Table Write Protect 08000-0BFFF CONFIG6L~4=WRT3,0x8,Table Write Protect 0C000-0FFFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x0,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x0,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x0,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x0,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTC,0x20,Config. Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTD,0x80,Data EE Write Protect CONFIG6H~1~1=0x20,0x20,Disabled CONFIG6H~1~2=0x20,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x80,0x80,Disabled CONFIG6H~3~2=0x80,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBRT0,0x1,Table Read Protect 00800-03FFF CONFIG7L~2=EBRT1,0x2,Table Read Protect 04000-07FFF CONFIG7L~3=EBRT2,0x4,Table Read Protect 08000-0BFFF CONFIG7L~4=EBRT3,0x8,Table Read Protect 0C000-0FFFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x0,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x0,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x0,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x0,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBRTB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F86K27] pgmmem=0x0 ~pgmmem=0x17fff cfgmem=0x300000 ~cfgmem=0x30000d userid=0x200000 ~userid=0x200007 eedata=0x0 ~eedata=0x3ff devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0x51e0 configslots=14 0x300000=CONFIG1L 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004=CONFIG3L 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000a=CONFIG6L 0x30000b=CONFIG6H 0x30000c=CONFIG7L 0x30000d=CONFIG7H CONFIG1L_unused=0x0 CONFIG1L~1=RETEN,0x1,VREG Sleep Enable bit CONFIG1L~2=SOSCEL,0x18,SOSC Power Selection and mode Configuration bits CONFIG1L~3=XINST,0x40,Extended Instruction Set CONFIG1L~1~1=0x1,0x1,Enabled CONFIG1L~1~2=0x1,0x0,Disabled CONFIG1L~2~1=0x18,0x18,High Power SOSC circuit selected CONFIG1L~2~2=0x18,0x8,Low Power SOSC circuit selected CONFIG1L~2~3=0x18,0x10,Digital (SCLKI) mode CONFIG1L~3~1=0x40,0x40,Enabled CONFIG1L~3~2=0x40,0x0,Disabled CONFIG1H_unused=0x0 CONFIG1H~1=FOSC,0xf,Oscillator CONFIG1H~2=PLLCFG,0x10,PLL x4 Enable bit CONFIG1H~3=PRCKEN,0x20,Primary Clock Enable bit CONFIG1H~4=FCMEN,0x40,Fail-Safe Clock Monitor CONFIG1H~5=IESO,0x80,Internal External Oscillator Switch Over Mode CONFIG1H~1~1=0xf,0xd,EC oscillator (Low power, DC - 160 kHz) CONFIG1H~1~2=0xf,0xc,EC oscillator, CLKOUT function on OSC2 (Low power, DC - 160 kHz) CONFIG1H~1~3=0xf,0xb,EC oscillator (Medium power, 160 kHz - 4 MHz) CONFIG1H~1~4=0xf,0xa,EC oscillator, CLKOUT function on OSC2 (Medium power, 160 kHz - 4 MHz) CONFIG1H~1~5=0xf,0x9,Internal RC oscillator, CLKOUT function on OSC2 CONFIG1H~1~6=0xf,0x8,Internal RC oscillator CONFIG1H~1~7=0xf,0x5,EC oscillator (High power, 16 MHz - 25 MHz) CONFIG1H~1~8=0xf,0x4,EC oscillator, CLKOUT function on OSC2 (High power, 16 MHz - 25 MHz) CONFIG1H~1~9=0xf,0x3,HS oscillator (Medium power, 4 MHz - 16 MHz) CONFIG1H~1~10=0xf,0x2,HS oscillator (High power, 16 MHz - 25 MHz) CONFIG1H~1~11=0xf,0x1,XT oscillator CONFIG1H~1~12=0xf,0x0,LP oscillator CONFIG1H~1~13=0x7,0x7,External RC oscillator CONFIG1H~1~14=0x7,0x6,External RC oscillator, CLKOUT function on OSC2 CONFIG1H~2~1=0x10,0x10,Enabled CONFIG1H~2~2=0x10,0x0,Disabled CONFIG1H~3~1=0x20,0x0,Disabled CONFIG1H~3~2=0x20,0x20,Enabled CONFIG1H~4~1=0x40,0x0,Disabled CONFIG1H~4~2=0x40,0x40,Enabled CONFIG1H~5~1=0x80,0x0,Disabled CONFIG1H~5~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PWRTEN,0x1,Power Up Timer CONFIG2L~2=BOREN,0x6,Brown Out Detect CONFIG2L~3=BORV,0x18,Brown-out Reset Voltage bits CONFIG2L~4=BORPWR,0x60,BORMV Power level CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active, disabled in SLEEP, SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,1.8V CONFIG2L~3~2=0x18,0x10,2.0V CONFIG2L~3~3=0x18,0x8,2.7V CONFIG2L~3~4=0x18,0x0,3.0V CONFIG2L~4~1=0x60,0x60,ZPBORMV instead of BORMV is selected CONFIG2L~4~2=0x60,0x40,BORMV set to high power level CONFIG2L~4~3=0x60,0x20,BORMV set to medium power level CONFIG2L~4~4=0x60,0x0,BORMV set to low power level CONFIG2H_unused=0x0 CONFIG2H~1=WDTEN,0x3,Watchdog Timer CONFIG2H~2=WDTPS,0x7c,Watchdog Postscaler CONFIG2H~1~1=0x3,0x3,Enabled in hardware, SWDTEN disabled CONFIG2H~1~2=0x3,0x2,Enabled while active, disabled in SLEEP, SWDTEN disabled CONFIG2H~1~3=0x3,0x1,Controlled with SWDTEN bit CONFIG2H~1~4=0x3,0x0,Disabled in hardware, SWDTEN disabled CONFIG2H~2~1=0x7c,0x7c,1:1048576 CONFIG2H~2~2=0x7c,0x4c,1:524288 CONFIG2H~2~3=0x7c,0x48,1:262144 CONFIG2H~2~4=0x7c,0x44,1:131072 CONFIG2H~2~5=0x7c,0x40,1:65536 CONFIG2H~2~6=0x7c,0x3c,1:32768 CONFIG2H~2~7=0x7c,0x38,1:16384 CONFIG2H~2~8=0x7c,0x34,1:8192 CONFIG2H~2~9=0x7c,0x30,1:4096 CONFIG2H~2~10=0x7c,0x2c,1:2048 CONFIG2H~2~11=0x7c,0x28,1:1024 CONFIG2H~2~12=0x7c,0x24,1:512 CONFIG2H~2~13=0x7c,0x20,1:256 CONFIG2H~2~14=0x7c,0x1c,1:128 CONFIG2H~2~15=0x7c,0x18,1:64 CONFIG2H~2~16=0x7c,0x14,1:32 CONFIG2H~2~17=0x7c,0x10,1:16 CONFIG2H~2~18=0x7c,0xc,1:8 CONFIG2H~2~19=0x7c,0x8,1:4 CONFIG2H~2~20=0x7c,0x4,1:2 CONFIG2H~2~21=0x7c,0x0,1:1 CONFIG3L_unused=0x0 CONFIG3L~1=RTCOSC,0x1,RTCC Clock Select CONFIG3L~2=EASHFT,0x8,External Address Shift bit CONFIG3L~3=ABW,0x30,Address Bus Width Select bits CONFIG3L~4=BW,0x40,Data Bus Width CONFIG3L~5=WAIT,0x80,External Bus Wait CONFIG3L~1~1=0x1,0x1,RTCC uses T1OSC/T1CKI CONFIG3L~1~2=0x1,0x0,RTCC uses INTRC CONFIG3L~2~1=0x8,0x8,Enabled CONFIG3L~2~2=0x8,0x0,Disabled CONFIG3L~3~1=0x30,0x30,20-bit address bus CONFIG3L~3~2=0x30,0x20,16-bit address bus CONFIG3L~3~3=0x30,0x10,12-bit address bus CONFIG3L~3~4=0x30,0x0,8-bit address bus CONFIG3L~4~1=0x40,0x40,16-bit external bus mode CONFIG3L~4~2=0x40,0x0,8-bit external bus mode CONFIG3L~5~1=0x80,0x80,Disabled CONFIG3L~5~2=0x80,0x0,Enabled CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MX,0x1,CCP2 Mux CONFIG3H~2=ECCPMX,0x2,ECCP Mux CONFIG3H~3=MSSPMSK,0x8,MSSP address masking CONFIG3H~4=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RE7-Microcontroller Mode/RB3-All other modes CONFIG3H~2~1=0x2,0x2,Enhanced CCP1/3 [P1B/P1C/P3B/P3C] muxed with RE6/RE5/RE4/RE3 CONFIG3H~2~2=0x2,0x0,Enhanced CCP1/3 [P1B/P1C/P3B/P3C] muxed with RH7/RH6/RH5/RH4 CONFIG3H~3~1=0x8,0x8,7 Bit address masking mode CONFIG3H~3~2=0x8,0x0,5 bit address masking mode CONFIG3H~4~1=0x80,0x80,MCLR Enabled, RG5 Disabled CONFIG3H~4~2=0x80,0x0,MCLR Disabled, RG5 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVREN,0x1,Stack Overflow Reset CONFIG4L~2=BBSIZ0,0x10,Boot Block Size CONFIG4L~3=DEBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x10,0x10,2K word Boot Block size CONFIG4L~2~2=0x10,0x0,1K word Boot Block size CONFIG4L~3~1=0x80,0x80,Disabled CONFIG4L~3~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP0,0x1,Code Protect 00800-03FFF CONFIG5L~2=CP1,0x2,Code Protect 04000-07FFF CONFIG5L~3=CP2,0x4,Code Protect 08000-0BFFF CONFIG5L~4=CP3,0x8,Code Protect 0C000-0FFFF CONFIG5L~5=CP4,0x10,Code Protect 10000-13FFF CONFIG5L~6=CP5,0x20,Code Protect 14000-17FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x0,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x0,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x0,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x0,Enabled CONFIG5L~5~1=0x10,0x10,Disabled CONFIG5L~5~2=0x10,0x0,Enabled CONFIG5L~6~1=0x20,0x20,Disabled CONFIG5L~6~2=0x20,0x0,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPB,0x40,Code Protect Boot CONFIG5H~2=CPD,0x80,Data EE Read Protect CONFIG5H~1~1=0x40,0x40,Disabled CONFIG5H~1~2=0x40,0x0,Enabled CONFIG5H~2~1=0x80,0x80,Disabled CONFIG5H~2~2=0x80,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT0,0x1,Table Write Protect 00800-03FFF CONFIG6L~2=WRT1,0x2,Table Write Protect 04000-07FFF CONFIG6L~3=WRT2,0x4,Table Write Protect 08000-0BFFF CONFIG6L~4=WRT3,0x8,Table Write Protect 0C000-0FFFF CONFIG6L~5=WRT4,0x10,Table Write Protect 10000-13FFF CONFIG6L~6=WRT5,0x20,Table Write Protect 14000-17FFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x0,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x0,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x0,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x0,Enabled CONFIG6L~5~1=0x10,0x10,Disabled CONFIG6L~5~2=0x10,0x0,Enabled CONFIG6L~6~1=0x20,0x20,Disabled CONFIG6L~6~2=0x20,0x0,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTC,0x20,Config. Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTD,0x80,Data EE Write Protect CONFIG6H~1~1=0x20,0x20,Disabled CONFIG6H~1~2=0x20,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x80,0x80,Disabled CONFIG6H~3~2=0x80,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBRT0,0x1,Table Read Protect 00800-03FFF CONFIG7L~2=EBRT1,0x2,Table Read Protect 04000-07FFF CONFIG7L~3=EBRT2,0x4,Table Read Protect 08000-0BFFF CONFIG7L~4=EBRT3,0x8,Table Read Protect 0C000-0FFFF CONFIG7L~5=EBRT4,0x10,Table Read Protect 10000-13FFF CONFIG7L~6=EBRT5,0x20,Table Read Protect 14000-17FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x0,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x0,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x0,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x0,Enabled CONFIG7L~5~1=0x10,0x10,Disabled CONFIG7L~5~2=0x10,0x0,Enabled CONFIG7L~6~1=0x20,0x20,Disabled CONFIG7L~6~2=0x20,0x0,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBRTB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F86K90] pgmmem=0x0 ~pgmmem=0xffff cfgmem=0x300000 ~cfgmem=0x30000d userid=0x200000 ~userid=0x200007 eedata=0x0 ~eedata=0x3ff devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0x5260 configslots=14 0x300000=CONFIG1L 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004=CONFIG3L 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000a=CONFIG6L 0x30000b=CONFIG6H 0x30000c=CONFIG7L 0x30000d=CONFIG7H CONFIG1L_unused=0x0 CONFIG1L~1=RETEN,0x1,VREG Sleep Enable bit CONFIG1L~2=SOSCEL,0x18,SOSC Power Selection and mode Configuration bits CONFIG1L~3=XINST,0x40,Extended Instruction Set CONFIG1L~1~1=0x1,0x1,Enabled CONFIG1L~1~2=0x1,0x0,Disabled CONFIG1L~2~1=0x18,0x18,High Power SOSC circuit selected CONFIG1L~2~2=0x18,0x8,Low Power SOSC circuit selected CONFIG1L~2~3=0x18,0x10,Digital (SCLKI) mode CONFIG1L~3~1=0x40,0x40,Enabled CONFIG1L~3~2=0x40,0x0,Disabled CONFIG1H_unused=0x0 CONFIG1H~1=FOSC,0xf,Oscillator CONFIG1H~2=PLLCFG,0x10,PLL x4 Enable bit CONFIG1H~3=PRCKEN,0x20,Primary Clock Enable bit CONFIG1H~4=FCMEN,0x40,Fail-Safe Clock Monitor CONFIG1H~5=IESO,0x80,Internal External Oscillator Switch Over Mode CONFIG1H~1~1=0x7,0x7,External RC oscillator CONFIG1H~1~2=0x7,0x6,External RC oscillator, CLKOUT function on OSC2 CONFIG1H~1~3=0xf,0xd,EC oscillator (Low power, DC - 160 kHz) CONFIG1H~1~4=0xf,0xc,EC oscillator, CLKOUT function on OSC2 (Low power, DC - 160 kHz) CONFIG1H~1~5=0xf,0xb,EC oscillator (Medium power, 160 kHz - 4 MHz) CONFIG1H~1~6=0xf,0xa,EC oscillator, CLKOUT function on OSC2 (Medium power, 160 kHz - 4 MHz) CONFIG1H~1~7=0xf,0x9,Internal RC oscillator, CLKOUT function on OSC2 CONFIG1H~1~8=0xf,0x8,Internal RC oscillator CONFIG1H~1~9=0xf,0x5,EC oscillator (High power, 16 MHz - 25 MHz) CONFIG1H~1~10=0xf,0x4,EC oscillator, CLKOUT function on OSC2 (High power, 16 MHz - 25 MHz) CONFIG1H~1~11=0xf,0x3,HS oscillator (Medium power, 4 MHz - 16 MHz) CONFIG1H~1~12=0xf,0x2,HS oscillator (High power, 16 MHz - 25 MHz) CONFIG1H~1~13=0xf,0x1,XT oscillator CONFIG1H~1~14=0xf,0x0,LP oscillator CONFIG1H~2~1=0x10,0x10,Enabled CONFIG1H~2~2=0x10,0x0,Disabled CONFIG1H~3~1=0x20,0x0,Disabled CONFIG1H~3~2=0x20,0x20,Enabled CONFIG1H~4~1=0x40,0x0,Disabled CONFIG1H~4~2=0x40,0x40,Enabled CONFIG1H~5~1=0x80,0x0,Disabled CONFIG1H~5~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PWRTEN,0x1,Power Up Timer CONFIG2L~2=BOREN,0x6,Brown Out Detect CONFIG2L~3=BORV,0x18,Brown-out Reset Voltage bits CONFIG2L~4=BORPWR,0x60,BORMV Power level CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active, disabled in SLEEP, SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,1.8V CONFIG2L~3~2=0x18,0x10,2.0V CONFIG2L~3~3=0x18,0x8,2.7V CONFIG2L~3~4=0x18,0x0,3.0V CONFIG2L~4~1=0x60,0x60,ZPBORMV instead of BORMV is selected CONFIG2L~4~2=0x60,0x40,BORMV set to high power level CONFIG2L~4~3=0x60,0x20,BORMV set to medium power level CONFIG2L~4~4=0x60,0x0,BORMV set to low power level CONFIG2H_unused=0x0 CONFIG2H~1=WDTEN,0x3,Watchdog Timer CONFIG2H~2=WDTPS,0x7c,Watchdog Postscaler CONFIG2H~1~1=0x3,0x3,Enabled in hardware, SWDTEN disabled CONFIG2H~1~2=0x3,0x2,Enabled while active, disabled in SLEEP, SWDTEN disabled CONFIG2H~1~3=0x3,0x1,Controlled with SWDTEN bit CONFIG2H~1~4=0x3,0x0,Disabled in hardware, SWDTEN disabled CONFIG2H~2~1=0x7c,0x7c,1:1048576 CONFIG2H~2~2=0x7c,0x4c,1:524288 CONFIG2H~2~3=0x7c,0x48,1:262144 CONFIG2H~2~4=0x7c,0x44,1:131072 CONFIG2H~2~5=0x7c,0x40,1:65536 CONFIG2H~2~6=0x7c,0x3c,1:32768 CONFIG2H~2~7=0x7c,0x38,1:16384 CONFIG2H~2~8=0x7c,0x34,1:8192 CONFIG2H~2~9=0x7c,0x30,1:4096 CONFIG2H~2~10=0x7c,0x2c,1:2048 CONFIG2H~2~11=0x7c,0x28,1:1024 CONFIG2H~2~12=0x7c,0x24,1:512 CONFIG2H~2~13=0x7c,0x20,1:256 CONFIG2H~2~14=0x7c,0x1c,1:128 CONFIG2H~2~15=0x7c,0x18,1:64 CONFIG2H~2~16=0x7c,0x14,1:32 CONFIG2H~2~17=0x7c,0x10,1:16 CONFIG2H~2~18=0x7c,0xc,1:8 CONFIG2H~2~19=0x7c,0x8,1:4 CONFIG2H~2~20=0x7c,0x4,1:2 CONFIG2H~2~21=0x7c,0x0,1:1 CONFIG3L_unused=0x0 CONFIG3L~1=RTCOSC,0x1,RTCC Clock Select CONFIG3L~1~1=0x1,0x1,RTCC uses T1OSC/T1CKI CONFIG3L~1~2=0x1,0x0,RTCC uses INTRC CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MX,0x1,CCP2 Mux CONFIG3H~2=ECCPMX,0x2,ECCP Mux CONFIG3H~3=MSSPMSK,0x8,MSSP address masking CONFIG3H~4=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RE7-Microcontroller Mode/RB3-All other modes CONFIG3H~2~1=0x2,0x2,Enhanced CCP1/3 [P1B/P1C/P3B/P3C] muxed with RE6/RE5/RE4/RE3 CONFIG3H~2~2=0x2,0x0,Enhanced CCP1/3 [P1B/P1C/P3B/P3C] muxed with RH7/RH6/RH5/RH4 CONFIG3H~3~1=0x8,0x8,7 Bit address masking mode CONFIG3H~3~2=0x8,0x0,5 bit address masking mode CONFIG3H~4~1=0x80,0x80,MCLR Enabled, RG5 Disabled CONFIG3H~4~2=0x80,0x0,MCLR Disabled, RG5 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVREN,0x1,Stack Overflow Reset CONFIG4L~2=BBSIZ0,0x10,Boot Block Size CONFIG4L~3=DEBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x10,0x10,2K word Boot Block size CONFIG4L~2~2=0x10,0x0,1K word Boot Block size CONFIG4L~3~1=0x80,0x80,Disabled CONFIG4L~3~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP0,0x1,Code Protect 00800-03FFF CONFIG5L~2=CP1,0x2,Code Protect 04000-07FFF CONFIG5L~3=CP2,0x4,Code Protect 08000-0BFFF CONFIG5L~4=CP3,0x8,Code Protect 0C000-0FFFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x0,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x0,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x0,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x0,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPB,0x40,Code Protect Boot CONFIG5H~2=CPD,0x80,Data EE Read Protect CONFIG5H~1~1=0x40,0x40,Disabled CONFIG5H~1~2=0x40,0x0,Enabled CONFIG5H~2~1=0x80,0x80,Disabled CONFIG5H~2~2=0x80,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT0,0x1,Table Write Protect 00800-03FFF CONFIG6L~2=WRT1,0x2,Table Write Protect 04000-07FFF CONFIG6L~3=WRT2,0x4,Table Write Protect 08000-0BFFF CONFIG6L~4=WRT3,0x8,Table Write Protect 0C000-0FFFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x0,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x0,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x0,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x0,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTC,0x20,Config. Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTD,0x80,Data EE Write Protect CONFIG6H~1~1=0x20,0x20,Disabled CONFIG6H~1~2=0x20,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x80,0x80,Disabled CONFIG6H~3~2=0x80,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBRT0,0x1,Table Read Protect 00800-03FFF CONFIG7L~2=EBRT1,0x2,Table Read Protect 04000-07FFF CONFIG7L~3=EBRT2,0x4,Table Read Protect 08000-0BFFF CONFIG7L~4=EBRT3,0x8,Table Read Protect 0C000-0FFFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x0,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x0,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x0,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x0,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBRTB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F86K95] pgmmem=0x0 ~pgmmem=0x17fff cfgmem=0x300000 ~cfgmem=0x30000d userid=0x200000 ~userid=0x200007 eedata=0x0 ~eedata=0x3ff devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0x5160 configslots=14 0x300000=CONFIG1L 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004=CONFIG3L 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000a=CONFIG6L 0x30000b=CONFIG6H 0x30000c=CONFIG7L 0x30000d=CONFIG7H CONFIG1L_unused=0x0 CONFIG1L~1=RETEN,0x1,VREG Sleep Enable bit CONFIG1L~2=SOSCEL,0x18,SOSC Power Selection and mode Configuration bits CONFIG1L~3=XINST,0x40,Extended Instruction Set CONFIG1L~1~1=0x1,0x1,Enabled CONFIG1L~1~2=0x1,0x0,Disabled CONFIG1L~2~1=0x18,0x18,High Power SOSC circuit selected CONFIG1L~2~2=0x18,0x8,Low Power SOSC circuit selected CONFIG1L~2~3=0x18,0x10,Digital (SCLKI) mode CONFIG1L~3~1=0x40,0x40,Enabled CONFIG1L~3~2=0x40,0x0,Disabled CONFIG1H_unused=0x0 CONFIG1H~1=FOSC,0xf,Oscillator CONFIG1H~2=PLLCFG,0x10,PLL x4 Enable bit CONFIG1H~3=PRCKEN,0x20,Primary Clock Enable bit CONFIG1H~4=FCMEN,0x40,Fail-Safe Clock Monitor CONFIG1H~5=IESO,0x80,Internal External Oscillator Switch Over Mode CONFIG1H~1~1=0x7,0x7,External RC oscillator CONFIG1H~1~2=0x7,0x6,External RC oscillator, CLKOUT function on OSC2 CONFIG1H~1~3=0xf,0xd,EC oscillator (Low power, DC - 160 kHz) CONFIG1H~1~4=0xf,0xc,EC oscillator, CLKOUT function on OSC2 (Low power, DC - 160 kHz) CONFIG1H~1~5=0xf,0xb,EC oscillator (Medium power, 160 kHz - 4 MHz) CONFIG1H~1~6=0xf,0xa,EC oscillator, CLKOUT function on OSC2 (Medium power, 160 kHz - 4 MHz) CONFIG1H~1~7=0xf,0x9,Internal RC oscillator, CLKOUT function on OSC2 CONFIG1H~1~8=0xf,0x8,Internal RC oscillator CONFIG1H~1~9=0xf,0x5,EC oscillator (High power, 16 MHz - 25 MHz) CONFIG1H~1~10=0xf,0x4,EC oscillator, CLKOUT function on OSC2 (High power, 16 MHz - 25 MHz) CONFIG1H~1~11=0xf,0x3,HS oscillator (Medium power, 4 MHz - 16 MHz) CONFIG1H~1~12=0xf,0x2,HS oscillator (High power, 16 MHz - 25 MHz) CONFIG1H~1~13=0xf,0x1,XT oscillator CONFIG1H~1~14=0xf,0x0,LP oscillator CONFIG1H~2~1=0x10,0x10,Enabled CONFIG1H~2~2=0x10,0x0,Disabled CONFIG1H~3~1=0x20,0x0,Disabled CONFIG1H~3~2=0x20,0x20,Enabled CONFIG1H~4~1=0x40,0x0,Disabled CONFIG1H~4~2=0x40,0x40,Enabled CONFIG1H~5~1=0x80,0x0,Disabled CONFIG1H~5~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PWRTEN,0x1,Power Up Timer CONFIG2L~2=BOREN,0x6,Brown Out Detect CONFIG2L~3=BORV,0x18,Brown-out Reset Voltage bits CONFIG2L~4=BORPWR,0x60,BORMV Power level CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active, disabled in SLEEP, SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,1.8V CONFIG2L~3~2=0x18,0x10,2.0V CONFIG2L~3~3=0x18,0x8,2.7V CONFIG2L~3~4=0x18,0x0,3.0V CONFIG2L~4~1=0x60,0x60,ZPBORMV instead of BORMV is selected CONFIG2L~4~2=0x60,0x40,BORMV set to high power level CONFIG2L~4~3=0x60,0x20,BORMV set to medium power level CONFIG2L~4~4=0x60,0x0,BORMV set to low power level CONFIG2H_unused=0x0 CONFIG2H~1=WDTEN,0x3,Watchdog Timer CONFIG2H~2=WDTPS,0x7c,Watchdog Postscaler CONFIG2H~1~1=0x3,0x3,Enabled in hardware, SWDTEN disabled CONFIG2H~1~2=0x3,0x2,Enabled while active, disabled in SLEEP, SWDTEN disabled CONFIG2H~1~3=0x3,0x1,Controlled with SWDTEN bit CONFIG2H~1~4=0x3,0x0,Disabled in hardware, SWDTEN disabled CONFIG2H~2~1=0x7c,0x7c,1:1048576 CONFIG2H~2~2=0x7c,0x4c,1:524288 CONFIG2H~2~3=0x7c,0x48,1:262144 CONFIG2H~2~4=0x7c,0x44,1:131072 CONFIG2H~2~5=0x7c,0x40,1:65536 CONFIG2H~2~6=0x7c,0x3c,1:32768 CONFIG2H~2~7=0x7c,0x38,1:16384 CONFIG2H~2~8=0x7c,0x34,1:8192 CONFIG2H~2~9=0x7c,0x30,1:4096 CONFIG2H~2~10=0x7c,0x2c,1:2048 CONFIG2H~2~11=0x7c,0x28,1:1024 CONFIG2H~2~12=0x7c,0x24,1:512 CONFIG2H~2~13=0x7c,0x20,1:256 CONFIG2H~2~14=0x7c,0x1c,1:128 CONFIG2H~2~15=0x7c,0x18,1:64 CONFIG2H~2~16=0x7c,0x14,1:32 CONFIG2H~2~17=0x7c,0x10,1:16 CONFIG2H~2~18=0x7c,0xc,1:8 CONFIG2H~2~19=0x7c,0x8,1:4 CONFIG2H~2~20=0x7c,0x4,1:2 CONFIG2H~2~21=0x7c,0x0,1:1 CONFIG3L_unused=0x0 CONFIG3L~1=RTCOSC,0x1,RTCC Clock Select CONFIG3L~1~1=0x1,0x1,RTCC uses T1OSC/T1CKI CONFIG3L~1~2=0x1,0x0,RTCC uses INTRC CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MX,0x1,CCP2 Mux CONFIG3H~2=ECCPMX,0x2,ECCP Mux CONFIG3H~3=MSSPMSK,0x8,MSSP address masking CONFIG3H~4=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RE7-Microcontroller Mode/RB3-All other modes CONFIG3H~2~1=0x2,0x2,Enhanced CCP1/3 [P1B/P1C/P3B/P3C] muxed with RE6/RE5/RE4/RE3 CONFIG3H~2~2=0x2,0x0,Enhanced CCP1/3 [P1B/P1C/P3B/P3C] muxed with RH7/RH6/RH5/RH4 CONFIG3H~3~1=0x8,0x8,7 Bit address masking mode CONFIG3H~3~2=0x8,0x0,5 bit address masking mode CONFIG3H~4~1=0x80,0x80,MCLR Enabled, RG5 Disabled CONFIG3H~4~2=0x80,0x0,MCLR Disabled, RG5 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVREN,0x1,Stack Overflow Reset CONFIG4L~2=BBSIZ0,0x10,Boot Block Size CONFIG4L~3=DEBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x10,0x10,2K word Boot Block size CONFIG4L~2~2=0x10,0x0,1K word Boot Block size CONFIG4L~3~1=0x80,0x80,Disabled CONFIG4L~3~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP0,0x1,Code Protect 00800-03FFF CONFIG5L~2=CP1,0x2,Code Protect 04000-07FFF CONFIG5L~3=CP2,0x4,Code Protect 08000-0BFFF CONFIG5L~4=CP3,0x8,Code Protect 0C000-0FFFF CONFIG5L~5=CP4,0x10,Code Protect 10000-13FFF CONFIG5L~6=CP5,0x20,Code Protect 14000-17FFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x0,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x0,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x0,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x0,Enabled CONFIG5L~5~1=0x10,0x10,Disabled CONFIG5L~5~2=0x10,0x0,Enabled CONFIG5L~6~1=0x20,0x20,Disabled CONFIG5L~6~2=0x20,0x0,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPB,0x40,Code Protect Boot CONFIG5H~2=CPD,0x80,Data EE Read Protect CONFIG5H~1~1=0x40,0x40,Disabled CONFIG5H~1~2=0x40,0x0,Enabled CONFIG5H~2~1=0x80,0x80,Disabled CONFIG5H~2~2=0x80,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT0,0x1,Table Write Protect 00800-03FFF CONFIG6L~2=WRT1,0x2,Table Write Protect 04000-07FFF CONFIG6L~3=WRT2,0x4,Table Write Protect 08000-0BFFF CONFIG6L~4=WRT3,0x8,Table Write Protect 0C000-0FFFF CONFIG6L~5=WRT4,0x10,Table Write Protect 10000-13FFF CONFIG6L~6=WRT5,0x20,Table Write Protect 14000-17FFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x0,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x0,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x0,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x0,Enabled CONFIG6L~5~1=0x10,0x10,Disabled CONFIG6L~5~2=0x10,0x0,Enabled CONFIG6L~6~1=0x20,0x20,Disabled CONFIG6L~6~2=0x20,0x0,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTC,0x20,Config. Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTD,0x80,Data EE Write Protect CONFIG6H~1~1=0x20,0x20,Disabled CONFIG6H~1~2=0x20,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x80,0x80,Disabled CONFIG6H~3~2=0x80,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBRT0,0x1,Table Read Protect 00800-03FFF CONFIG7L~2=EBRT1,0x2,Table Read Protect 04000-07FFF CONFIG7L~3=EBRT2,0x4,Table Read Protect 08000-0BFFF CONFIG7L~4=EBRT3,0x8,Table Read Protect 0C000-0FFFF CONFIG7L~5=EBRT4,0x10,Table Read Protect 10000-13FFF CONFIG7L~6=EBRT5,0x20,Table Read Protect 14000-17FFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x0,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x0,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x0,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x0,Enabled CONFIG7L~5~1=0x10,0x10,Disabled CONFIG7L~5~2=0x10,0x0,Enabled CONFIG7L~6~1=0x20,0x20,Disabled CONFIG7L~6~2=0x20,0x0,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBRTB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F8723] pgmmem=0x20000 ~pgmmem=0x1fffff cfgmem=0x300000 ~cfgmem=0x30000d userid=0x200000 ~userid=0x200007 eedata=0x0 ~eedata=0x3ff devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0x4a20 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004=CONFIG3L 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000a=CONFIG6L 0x30000b=CONFIG6H 0x30000c=CONFIG7L 0x30000d=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=OSC,0xf,Oscillator CONFIG1H~2=FCMEN,0x40,Fail-Safe Clock Monitor Enable CONFIG1H~3=IESO,0x80,Internal External Switch Over Mode CONFIG1H~1~1=0xc,0xc,11XX EXT RC-CLKOUT on RA6 CONFIG1H~1~2=0xe,0xa,101X EXT RC-CLKOUT on RA6 CONFIG1H~1~3=0xf,0x9,INT RC-CLKOUT on RA6,Port on RA7 CONFIG1H~1~4=0xf,0x8,INT RC-Port on RA6,Port on RA7 CONFIG1H~1~5=0xf,0x7,EXT RC-Port on RA6 CONFIG1H~1~6=0xf,0x6,HS-PLL enabled freq=4xFosc1 CONFIG1H~1~7=0xf,0x5,EC-Port on RA6 CONFIG1H~1~8=0xf,0x4,EC-CLKOUT on RA6 CONFIG1H~1~9=0xf,0x3,0011 EXT RC-CLKOUT on RA6 CONFIG1H~1~10=0xf,0x2,HS CONFIG1H~1~11=0xf,0x1,XT CONFIG1H~1~12=0xf,0x0,LP CONFIG1H~2~1=0x40,0x0,Disabled CONFIG1H~2~2=0x40,0x40,Enabled CONFIG1H~3~1=0x80,0x0,Disabled CONFIG1H~3~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PUT,0x1,Power Up Timer CONFIG2L~2=BODEN,0x6,Brown Out Detect CONFIG2L~3=BODENV,0x18,Brown Out Voltage CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active,disabled in SLEEP,SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,2.0V CONFIG2L~3~2=0x18,0x10,2.7V CONFIG2L~3~3=0x18,0x8,4.2V CONFIG2L~3~4=0x18,0x0,4.5V CONFIG2H_unused=0x0 CONFIG2H~1=WDT,0x1,Watchdog Timer CONFIG2H~2=WDTPS,0x1e,Watchdog Postscaler CONFIG2H~1~1=0x1,0x1,Enabled CONFIG2H~1~2=0x1,0x0,Disabled-Controlled by SWDTEN bit CONFIG2H~2~1=0x1e,0x1e,1:32768 CONFIG2H~2~2=0x1e,0x1c,1:16384 CONFIG2H~2~3=0x1e,0x1a,1:8192 CONFIG2H~2~4=0x1e,0x18,1:4096 CONFIG2H~2~5=0x1e,0x16,1:2048 CONFIG2H~2~6=0x1e,0x14,1:1024 CONFIG2H~2~7=0x1e,0x12,1:512 CONFIG2H~2~8=0x1e,0x10,1:256 CONFIG2H~2~9=0x1e,0xe,1:128 CONFIG2H~2~10=0x1e,0xc,1:64 CONFIG2H~2~11=0x1e,0xa,1:32 CONFIG2H~2~12=0x1e,0x8,1:16 CONFIG2H~2~13=0x1e,0x6,1:8 CONFIG2H~2~14=0x1e,0x4,1:4 CONFIG2H~2~15=0x1e,0x2,1:2 CONFIG2H~2~16=0x1e,0x0,1:1 CONFIG3L_unused=0x0 CONFIG3L~1=PMODE,0x3,Processor Mode CONFIG3L~2=ABW,0x30,Address Bus Width CONFIG3L~3=BW,0x40,Bus Width CONFIG3L~4=WAIT,0x80,External Bus Wait CONFIG3L~1~1=0x3,0x3,Microcontroller CONFIG3L~1~2=0x3,0x2,Microprocessor CONFIG3L~1~3=0x3,0x1,Microprocessor w/Boot CONFIG3L~1~4=0x3,0x0,Ext Microcontroller CONFIG3L~2~1=0x30,0x30,20-bit CONFIG3L~2~2=0x30,0x20,16-bit CONFIG3L~2~3=0x30,0x10,12-bit CONFIG3L~2~4=0x30,0x0,8-bit CONFIG3L~3~1=0x40,0x40,16-bit external bus CONFIG3L~3~2=0x40,0x0,8-bit external bus CONFIG3L~4~1=0x80,0x80,Disabled CONFIG3L~4~2=0x80,0x0,Enabled CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 Mux CONFIG3H~2=ECCPMX,0x2,ECCP Mux CONFIG3H~3=LPT1OSC,0x4,Low Power Timer1 Osc enable CONFIG3H~4=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RE7-Microcontroller Mode/RB3-All other modes CONFIG3H~2~1=0x2,0x2,Enhanced CCP1/3 [P1B/P1C/P3B/P3C] muxed with RE6/RE5/RE4/RE3 CONFIG3H~2~2=0x2,0x0,Enhanced CCP1/3 [P1B/P1C/P3B/P3C] muxed with RH7/RH6/RH5/RH4 CONFIG3H~3~1=0x4,0x4,Enabled CONFIG3H~3~2=0x4,0x0,Disabled CONFIG3H~4~1=0x80,0x80,MCLR Enabled,RG5 Disabled CONFIG3H~4~2=0x80,0x0,MCLR Disabled, RG5 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVR,0x1,Stack Overflow Reset CONFIG4L~2=LVP,0x4,Low Voltage Program CONFIG4L~3=BBSIZ,0x30,Boot Block Size CONFIG4L~4=XINST,0x40,Extended Instruction Set Enable bit CONFIG4L~5=BACKBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x20,0x20,4K Words (8 Kbytes) CONFIG4L~3~2=0x30,0x10,2K Words (4 Kbytes) CONFIG4L~3~3=0x30,0x0,1K Words (2 Kbytes) CONFIG4L~4~1=0x40,0x40,Enabled CONFIG4L~4~2=0x40,0x0,Disabled CONFIG4L~5~1=0x80,0x80,Disabled CONFIG4L~5~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP_0,0x1,Code Protect 00800-03FFF CONFIG5L~2=CP_1,0x2,Code Protect 04000-07FFF CONFIG5L~3=CP_2,0x4,Code Protect 08000-0BFFF CONFIG5L~4=CP_3,0x8,Code Protect 0C000-0FFFF CONFIG5L~5=CP_4,0x10,Code Protect 10000-13FFF CONFIG5L~6=CP_5,0x20,Code Protect 14000-17FFF CONFIG5L~7=CP_6,0x40,Code Protect 18000-1BFFF CONFIG5L~8=CP_7,0x80,Code Protect 1C000-1FFFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x0,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x0,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x0,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x0,Enabled CONFIG5L~5~1=0x10,0x10,Disabled CONFIG5L~5~2=0x10,0x0,Enabled CONFIG5L~6~1=0x20,0x20,Disabled CONFIG5L~6~2=0x20,0x0,Enabled CONFIG5L~7~1=0x40,0x40,Disabled CONFIG5L~7~2=0x40,0x0,Enabled CONFIG5L~8~1=0x80,0x80,Disabled CONFIG5L~8~2=0x80,0x0,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPB,0x40,Code Protect Boot CONFIG5H~2=CPD,0x80,Data EE Read Protect CONFIG5H~1~1=0x40,0x40,Disabled CONFIG5H~1~2=0x40,0x0,Enabled CONFIG5H~2~1=0x80,0x80,Disabled CONFIG5H~2~2=0x80,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT_0,0x1,Table Write Protect 00800-03FFF CONFIG6L~2=WRT_1,0x2,Table Write Protect 04000-07FFF CONFIG6L~3=WRT_2,0x4,Table Write Protect 08000-0BFFF CONFIG6L~4=WRT_3,0x8,Table Write Protect 0C000-0FFFF CONFIG6L~5=WRT_4,0x10,Table Write Protect 10000-13FFF CONFIG6L~6=WRT_5,0x20,Table Write Protect 14000-17FFF CONFIG6L~7=WRT_6,0x40,Table Write Protect 18000-1BFFF CONFIG6L~8=WRT_7,0x80,Table Write Protect 1C000-1FFFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x0,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x0,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x0,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x0,Enabled CONFIG6L~5~1=0x10,0x10,Disabled CONFIG6L~5~2=0x10,0x0,Enabled CONFIG6L~6~1=0x20,0x20,Disabled CONFIG6L~6~2=0x20,0x0,Enabled CONFIG6L~7~1=0x40,0x40,Disabled CONFIG6L~7~2=0x40,0x0,Enabled CONFIG6L~8~1=0x80,0x80,Disabled CONFIG6L~8~2=0x80,0x0,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTC,0x20,Config. Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTD,0x80,Data EE Write Protect CONFIG6H~1~1=0x20,0x20,Disabled CONFIG6H~1~2=0x20,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x80,0x80,Disabled CONFIG6H~3~2=0x80,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR_0,0x1,Table Read Protect 00800-03FFF CONFIG7L~2=EBTR_1,0x2,Table Read Protect 04000-07FFF CONFIG7L~3=EBTR_2,0x4,Table Read Protect 08000-0BFFF CONFIG7L~4=EBTR_3,0x8,Table Read Protect 0C000-0FFFF CONFIG7L~5=EBTR_4,0x10,Table Read Protect 10000-13FFF CONFIG7L~6=EBTR_5,0x20,Table Read Protect 14000-17FFF CONFIG7L~7=EBTR_6,0x40,Table Read Protect 18000-1BFFF CONFIG7L~8=EBTR_7,0x80,Table Read Protect 1C000-1FFFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x0,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x0,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x0,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x0,Enabled CONFIG7L~5~1=0x10,0x10,Disabled CONFIG7L~5~2=0x10,0x0,Enabled CONFIG7L~6~1=0x20,0x20,Disabled CONFIG7L~6~2=0x20,0x0,Enabled CONFIG7L~7~1=0x40,0x40,Disabled CONFIG7L~7~2=0x40,0x0,Enabled CONFIG7L~8~1=0x80,0x80,Disabled CONFIG7L~8~2=0x80,0x0,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F87J90] pgmmem=0x20000 ~pgmmem=0x1fffff cfgmem=0x1fff8 ~cfgmem=0x1ffff userid= ~userid= eedata= ~eedata= devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0x50a0 configslots=8 0x1fff8=CONFIG1L 0x1fff9=CONFIG1H 0x1fffa=CONFIG2L 0x1fffb=CONFIG2H 0x1fffc=CONFIG3L 0x1fffd=CONFIG3H 0x1fffe= 0x1ffff= CONFIG1L_unused=0x0 CONFIG1L~1=WDTEN,0x1,Watchdog Timer CONFIG1L~2=STVREN,0x20,Stack Overflow Reset CONFIG1L~3=XINST,0x40,Extended Instruction Set Enable bit CONFIG1L~4=DEBUG,0x80,Background Debugger Enable bit CONFIG1L~1~1=0x1,0x1,Enabled CONFIG1L~1~2=0x1,0x0,Disabled CONFIG1L~2~1=0x20,0x20,Enabled CONFIG1L~2~2=0x20,0x0,Disabled CONFIG1L~3~1=0x40,0x40,Enabled CONFIG1L~3~2=0x40,0x0,Disabled CONFIG1L~4~1=0x80,0x80,Disabled CONFIG1L~4~2=0x80,0x0,Enabled CONFIG1H_unused=0x0 CONFIG1H~1=CP0,0x4,Code Protect CONFIG1H~2=SIGN,0x8,Config Word Signature Bit CONFIG1H~3=RESERVED,0xf0,RESERVED CONFIG1H~1~1=0x4,0x4,Disabled CONFIG1H~1~2=0x4,0x0,Enabled CONFIG1H~2~1=0x8,0x8,Bulk erase of memory not conducated CONFIG1H~2~2=0x8,0x0,Bulk erase of memory area complete CONFIG1H~3~1=0xf0,0xf0,RESERVED CONFIG2L_unused=0x0 CONFIG2L~1=OSC,0x7,Oscillator Selection bits CONFIG2L~2=T1DIG,0x8,Secondary Clock Source T1OSCEN Enforcement CONFIG2L~3=LPT1OSC,0x10,Low-Power Timer1 Oscillator Enable bit CONFIG2L~4=FCMEN,0x40,Fail-Safe Clock Monitor Enable bit CONFIG2L~5=IESO,0x80,Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit CONFIG2L~1~1=0x7,0x7,EC Oscillator with PLL CONFIG2L~1~2=0x7,0x6,EC Oscillator with clock out on RA6 CONFIG2L~1~3=0x7,0x5,HS oscillator, PLL enabled CONFIG2L~1~4=0x7,0x4,HS oscillator CONFIG2L~1~5=0x7,0x3,INTOSC with PLL enabled, CLKOUT on RA6 and port function on RA7 CONFIG2L~1~6=0x7,0x2,Internal oscillator, CLKOUT on RA6 and port function on RA7 CONFIG2L~1~7=0x7,0x1,INTOSC with PLL enabled, port function on RA6 and RA7 CONFIG2L~1~8=0x7,0x0,Internal oscillator, port function on RA6 and RA7 CONFIG2L~2~1=0x8,0x8,Enabled CONFIG2L~2~2=0x8,0x0,Disabled CONFIG2L~3~1=0x10,0x0,Enabled CONFIG2L~3~2=0x10,0x10,Disabled CONFIG2L~4~1=0x40,0x0,Disabled CONFIG2L~4~2=0x40,0x40,Enabled CONFIG2L~5~1=0x80,0x0,Disabled CONFIG2L~5~2=0x80,0x80,Enabled CONFIG2H_unused=0x0 CONFIG2H~1=WDTPS,0xf,Watchdog Timer Postscaler Select bits CONFIG2H~2=RESERVED,0xf0,RESERVED CONFIG2H~1~1=0xf,0xf,1:32768 CONFIG2H~1~2=0xf,0xe,1:16384 CONFIG2H~1~3=0xf,0xd,1:8192 CONFIG2H~1~4=0xf,0xc,1:4096 CONFIG2H~1~5=0xf,0xb,1:2048 CONFIG2H~1~6=0xf,0xa,1:1024 CONFIG2H~1~7=0xf,0x9,1:512 CONFIG2H~1~8=0xf,0x8,1:256 CONFIG2H~1~9=0xf,0x7,1:128 CONFIG2H~1~10=0xf,0x6,1:64 CONFIG2H~1~11=0xf,0x5,1:32 CONFIG2H~1~12=0xf,0x4,1:16 CONFIG2H~1~13=0xf,0x3,1:8 CONFIG2H~1~14=0xf,0x2,1:4 CONFIG2H~1~15=0xf,0x1,1:2 CONFIG2H~1~16=0xf,0x0,1:1 CONFIG2H~2~1=0xf0,0xf0,RESERVED CONFIG3L_unused=0x0 CONFIG3L~1=RTCSOSC,0x2,RTCC Reference Clock Select bit CONFIG3L~1~1=0x2,0x2,RTCC uses T1OSC/T1CKI as reference clock CONFIG3L~1~2=0x2,0x0,RTCC uses INTOSC/INTRC as reference clock CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MX,0x1,CCP2 MUX CONFIG3H~2=RESERVED,0xf0,RESERVED CONFIG3H~1~1=0x1,0x0,RE7 / RB3 CONFIG3H~1~2=0x1,0x1,RC1 CONFIG3H~2~1=0xf0,0xf0,RESERVED erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F87J93] pgmmem=0x20000 ~pgmmem=0x1fffff cfgmem=0x1fff8 ~cfgmem=0x1ffff userid= ~userid= eedata= ~eedata= devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0x50e0 configslots=8 0x1fff8=CONFIG1L 0x1fff9=CONFIG1H 0x1fffa=CONFIG2L 0x1fffb=CONFIG2H 0x1fffc=CONFIG3L 0x1fffd=CONFIG3H 0x1fffe= 0x1ffff= CONFIG1L_unused=0x0 CONFIG1L~1=WDTEN,0x1,Watchdog Timer CONFIG1L~2=STVREN,0x20,Stack Overflow Reset CONFIG1L~3=XINST,0x40,Extended Instruction Set Enable bit CONFIG1L~4=DEBUG,0x80,Background Debugger Enable bit CONFIG1L~1~1=0x1,0x1,Enabled CONFIG1L~1~2=0x1,0x0,Disabled CONFIG1L~2~1=0x20,0x20,Enabled CONFIG1L~2~2=0x20,0x0,Disabled CONFIG1L~3~1=0x40,0x40,Enabled CONFIG1L~3~2=0x40,0x0,Disabled CONFIG1L~4~1=0x80,0x80,Disabled CONFIG1L~4~2=0x80,0x0,Enabled CONFIG1H_unused=0x0 CONFIG1H~1=CP0,0x4,Code Protect CONFIG1H~2=SIGN,0x8,Config Word Signature Bit CONFIG1H~3=RESERVED,0xf0,RESERVED CONFIG1H~1~1=0x4,0x4,Disabled CONFIG1H~1~2=0x4,0x0,Enabled CONFIG1H~2~1=0x8,0x8,Bulk erase of memory not conducated CONFIG1H~2~2=0x8,0x0,Bulk erase of memory area complete CONFIG1H~3~1=0xf0,0xf0,RESERVED CONFIG2L_unused=0x0 CONFIG2L~1=OSC,0x7,Oscillator Selection bits CONFIG2L~2=T1DIG,0x8,Secondary Clock Source T1OSCEN Enforcement CONFIG2L~3=LPT1OSC,0x10,Low-Power Timer1 Oscillator Enable bit CONFIG2L~4=FCMEN,0x40,Fail-Safe Clock Monitor Enable bit CONFIG2L~5=IESO,0x80,Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit CONFIG2L~1~1=0x7,0x7,EC Oscillator with PLL CONFIG2L~1~2=0x7,0x6,EC Oscillator with clock out on RA6 CONFIG2L~1~3=0x7,0x5,HS oscillator, PLL enabled CONFIG2L~1~4=0x7,0x4,HS oscillator CONFIG2L~1~5=0x7,0x3,INTOSC with PLL enabled, CLKOUT on RA6 and port function on RA7 CONFIG2L~1~6=0x7,0x2,Internal oscillator, CLKOUT on RA6 and port function on RA7 CONFIG2L~1~7=0x7,0x1,INTOSC with PLL enabled, port function on RA6 and RA7 CONFIG2L~1~8=0x7,0x0,Internal oscillator, port function on RA6 and RA7 CONFIG2L~2~1=0x8,0x8,Enabled CONFIG2L~2~2=0x8,0x0,Disabled CONFIG2L~3~1=0x10,0x0,Enabled CONFIG2L~3~2=0x10,0x10,Disabled CONFIG2L~4~1=0x40,0x0,Disabled CONFIG2L~4~2=0x40,0x40,Enabled CONFIG2L~5~1=0x80,0x0,Disabled CONFIG2L~5~2=0x80,0x80,Enabled CONFIG2H_unused=0x0 CONFIG2H~1=WDTPS,0xf,Watchdog Timer Postscaler Select bits CONFIG2H~2=RESERVED,0xf0,RESERVED CONFIG2H~1~1=0xf,0xf,1:32768 CONFIG2H~1~2=0xf,0xe,1:16384 CONFIG2H~1~3=0xf,0xd,1:8192 CONFIG2H~1~4=0xf,0xc,1:4096 CONFIG2H~1~5=0xf,0xb,1:2048 CONFIG2H~1~6=0xf,0xa,1:1024 CONFIG2H~1~7=0xf,0x9,1:512 CONFIG2H~1~8=0xf,0x8,1:256 CONFIG2H~1~9=0xf,0x7,1:128 CONFIG2H~1~10=0xf,0x6,1:64 CONFIG2H~1~11=0xf,0x5,1:32 CONFIG2H~1~12=0xf,0x4,1:16 CONFIG2H~1~13=0xf,0x3,1:8 CONFIG2H~1~14=0xf,0x2,1:4 CONFIG2H~1~15=0xf,0x1,1:2 CONFIG2H~1~16=0xf,0x0,1:1 CONFIG2H~2~1=0xf0,0xf0,RESERVED CONFIG3L_unused=0x0 CONFIG3L~1=RTCSOSC,0x2,RTCC Reference Clock Select bit CONFIG3L~1~1=0x2,0x2,RTCC uses T1OSC/T1CKI as reference clock CONFIG3L~1~2=0x2,0x0,RTCC uses INTOSC/INTRC as reference clock CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MX,0x1,CCP2 MUX CONFIG3H~2=RESERVED,0xf0,RESERVED CONFIG3H~1~1=0x1,0x0,RE7 / RB3 CONFIG3H~1~2=0x1,0x1,RC1 CONFIG3H~2~1=0xf0,0xf0,RESERVED erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F87K22] pgmmem=0x0 ~pgmmem=0x1ffff cfgmem=0x300000 ~cfgmem=0x30000d userid=0x200000 ~userid=0x200007 eedata=0x0 ~eedata=0x3ff devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0x51c0 configslots=14 0x300000=CONFIG1L 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004=CONFIG3L 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000a=CONFIG6L 0x30000b=CONFIG6H 0x30000c=CONFIG7L 0x30000d=CONFIG7H CONFIG1L_unused=0x0 CONFIG1L~1=RETEN,0x1,VREG Sleep Enable bit CONFIG1L~2=SOSCEL,0x18,SOSC Power Selection and mode Configuration bits CONFIG1L~3=XINST,0x40,Extended Instruction Set CONFIG1L~1~1=0x1,0x1,Enabled CONFIG1L~1~2=0x1,0x0,Disabled CONFIG1L~2~1=0x18,0x18,High Power SOSC circuit selected CONFIG1L~2~2=0x18,0x8,Low Power SOSC circuit selected CONFIG1L~2~3=0x18,0x10,Digital (SCLKI) mode CONFIG1L~3~1=0x40,0x40,Enabled CONFIG1L~3~2=0x40,0x0,Disabled CONFIG1H_unused=0x0 CONFIG1H~1=FOSC,0xf,Oscillator CONFIG1H~2=PLLCFG,0x10,PLL x4 Enable bit CONFIG1H~3=PRCKEN,0x20,Primary Clock Enable bit CONFIG1H~4=FCMEN,0x40,Fail-Safe Clock Monitor CONFIG1H~5=IESO,0x80,Internal External Oscillator Switch Over Mode CONFIG1H~1~1=0xf,0xd,EC oscillator (Low power, DC - 160 kHz) CONFIG1H~1~2=0xf,0xc,EC oscillator, CLKOUT function on OSC2 (Low power, DC - 160 kHz) CONFIG1H~1~3=0xf,0xb,EC oscillator (Medium power, 160 kHz - 4 MHz) CONFIG1H~1~4=0xf,0xa,EC oscillator, CLKOUT function on OSC2 (Medium power, 160 kHz - 4 MHz) CONFIG1H~1~5=0xf,0x9,Internal RC oscillator, CLKOUT function on OSC2 CONFIG1H~1~6=0xf,0x8,Internal RC oscillator CONFIG1H~1~7=0xf,0x5,EC oscillator (High power, 16 MHz - 25 MHz) CONFIG1H~1~8=0xf,0x4,EC oscillator, CLKOUT function on OSC2 (High power, 16 MHz - 25 MHz) CONFIG1H~1~9=0xf,0x3,HS oscillator (Medium power, 4 MHz - 16 MHz) CONFIG1H~1~10=0xf,0x2,HS oscillator (High power, 16 MHz - 25 MHz) CONFIG1H~1~11=0xf,0x1,XT oscillator CONFIG1H~1~12=0xf,0x0,LP oscillator CONFIG1H~1~13=0x7,0x7,External RC oscillator CONFIG1H~1~14=0x7,0x6,External RC oscillator, CLKOUT function on OSC2 CONFIG1H~2~1=0x10,0x10,Enabled CONFIG1H~2~2=0x10,0x0,Disabled CONFIG1H~3~1=0x20,0x0,Disabled CONFIG1H~3~2=0x20,0x20,Enabled CONFIG1H~4~1=0x40,0x0,Disabled CONFIG1H~4~2=0x40,0x40,Enabled CONFIG1H~5~1=0x80,0x0,Disabled CONFIG1H~5~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PWRTEN,0x1,Power Up Timer CONFIG2L~2=BOREN,0x6,Brown Out Detect CONFIG2L~3=BORV,0x18,Brown-out Reset Voltage bits CONFIG2L~4=BORPWR,0x60,BORMV Power level CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active, disabled in SLEEP, SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,1.8V CONFIG2L~3~2=0x18,0x10,2.0V CONFIG2L~3~3=0x18,0x8,2.7V CONFIG2L~3~4=0x18,0x0,3.0V CONFIG2L~4~1=0x60,0x60,ZPBORMV instead of BORMV is selected CONFIG2L~4~2=0x60,0x40,BORMV set to high power level CONFIG2L~4~3=0x60,0x20,BORMV set to medium power level CONFIG2L~4~4=0x60,0x0,BORMV set to low power level CONFIG2H_unused=0x0 CONFIG2H~1=WDTEN,0x3,Watchdog Timer CONFIG2H~2=WDTPS,0x7c,Watchdog Postscaler CONFIG2H~1~1=0x3,0x3,Enabled in hardware, SWDTEN disabled CONFIG2H~1~2=0x3,0x2,Enabled while active, disabled in SLEEP, SWDTEN disabled CONFIG2H~1~3=0x3,0x1,Controlled with SWDTEN bit CONFIG2H~1~4=0x3,0x0,Disabled in hardware, SWDTEN disabled CONFIG2H~2~1=0x7c,0x7c,1:1048576 CONFIG2H~2~2=0x7c,0x4c,1:524288 CONFIG2H~2~3=0x7c,0x48,1:262144 CONFIG2H~2~4=0x7c,0x44,1:131072 CONFIG2H~2~5=0x7c,0x40,1:65536 CONFIG2H~2~6=0x7c,0x3c,1:32768 CONFIG2H~2~7=0x7c,0x38,1:16384 CONFIG2H~2~8=0x7c,0x34,1:8192 CONFIG2H~2~9=0x7c,0x30,1:4096 CONFIG2H~2~10=0x7c,0x2c,1:2048 CONFIG2H~2~11=0x7c,0x28,1:1024 CONFIG2H~2~12=0x7c,0x24,1:512 CONFIG2H~2~13=0x7c,0x20,1:256 CONFIG2H~2~14=0x7c,0x1c,1:128 CONFIG2H~2~15=0x7c,0x18,1:64 CONFIG2H~2~16=0x7c,0x14,1:32 CONFIG2H~2~17=0x7c,0x10,1:16 CONFIG2H~2~18=0x7c,0xc,1:8 CONFIG2H~2~19=0x7c,0x8,1:4 CONFIG2H~2~20=0x7c,0x4,1:2 CONFIG2H~2~21=0x7c,0x0,1:1 CONFIG3L_unused=0x0 CONFIG3L~1=RTCOSC,0x1,RTCC Clock Select CONFIG3L~2=EASHFT,0x8,External Address Shift bit CONFIG3L~3=ABW,0x30,Address Bus Width Select bits CONFIG3L~4=BW,0x40,Data Bus Width CONFIG3L~5=WAIT,0x80,External Bus Wait CONFIG3L~1~1=0x1,0x1,RTCC uses T1OSC/T1CKI CONFIG3L~1~2=0x1,0x0,RTCC uses INTRC CONFIG3L~2~1=0x8,0x8,Enabled CONFIG3L~2~2=0x8,0x0,Disabled CONFIG3L~3~1=0x30,0x30,20-bit address bus CONFIG3L~3~2=0x30,0x20,16-bit address bus CONFIG3L~3~3=0x30,0x10,12-bit address bus CONFIG3L~3~4=0x30,0x0,8-bit address bus CONFIG3L~4~1=0x40,0x40,16-bit external bus mode CONFIG3L~4~2=0x40,0x0,8-bit external bus mode CONFIG3L~5~1=0x80,0x80,Disabled CONFIG3L~5~2=0x80,0x0,Enabled CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MX,0x1,CCP2 Mux CONFIG3H~2=ECCPMX,0x2,ECCP Mux CONFIG3H~3=MSSPMSK,0x8,MSSP address masking CONFIG3H~4=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RE7-Microcontroller Mode/RB3-All other modes CONFIG3H~2~1=0x2,0x2,Enhanced CCP1/3 [P1B/P1C/P3B/P3C] muxed with RE6/RE5/RE4/RE3 CONFIG3H~2~2=0x2,0x0,Enhanced CCP1/3 [P1B/P1C/P3B/P3C] muxed with RH7/RH6/RH5/RH4 CONFIG3H~3~1=0x8,0x8,7 Bit address masking mode CONFIG3H~3~2=0x8,0x0,5 bit address masking mode CONFIG3H~4~1=0x80,0x80,MCLR Enabled, RG5 Disabled CONFIG3H~4~2=0x80,0x0,MCLR Disabled, RG5 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVREN,0x1,Stack Overflow Reset CONFIG4L~2=BBSIZ0,0x10,Boot Block Size CONFIG4L~3=DEBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x10,0x10,2K word Boot Block size CONFIG4L~2~2=0x10,0x0,1K word Boot Block size CONFIG4L~3~1=0x80,0x80,Disabled CONFIG4L~3~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP0,0x1,Code Protect 00800-03FFF CONFIG5L~2=CP1,0x2,Code Protect 04000-07FFF CONFIG5L~3=CP2,0x4,Code Protect 08000-0BFFF CONFIG5L~4=CP3,0x8,Code Protect 0C000-0FFFF CONFIG5L~5=CP4,0x10,Code Protect 10000-13FFF CONFIG5L~6=CP5,0x20,Code Protect 14000-17FFF CONFIG5L~7=CP6,0x40,Code Protect 18000-1BFFF CONFIG5L~8=CP7,0x80,Code Protect 1C000-1FFFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x0,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x0,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x0,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x0,Enabled CONFIG5L~5~1=0x10,0x10,Disabled CONFIG5L~5~2=0x10,0x0,Enabled CONFIG5L~6~1=0x20,0x20,Disabled CONFIG5L~6~2=0x20,0x0,Enabled CONFIG5L~7~1=0x40,0x40,Disabled CONFIG5L~7~2=0x40,0x0,Enabled CONFIG5L~8~1=0x80,0x80,Disabled CONFIG5L~8~2=0x80,0x0,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPB,0x40,Code Protect Boot CONFIG5H~2=CPD,0x80,Data EE Read Protect CONFIG5H~1~1=0x40,0x40,Disabled CONFIG5H~1~2=0x40,0x0,Enabled CONFIG5H~2~1=0x80,0x80,Disabled CONFIG5H~2~2=0x80,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT0,0x1,Table Write Protect 00800-03FFF CONFIG6L~2=WRT1,0x2,Table Write Protect 04000-07FFF CONFIG6L~3=WRT2,0x4,Table Write Protect 08000-0BFFF CONFIG6L~4=WRT3,0x8,Table Write Protect 0C000-0FFFF CONFIG6L~5=WRT4,0x10,Table Write Protect 10000-13FFF CONFIG6L~6=WRT5,0x20,Table Write Protect 14000-17FFF CONFIG6L~7=WRT6,0x40,Table Write Protect 18000-1BFFF CONFIG6L~8=WRT7,0x80,Table Write Protect 1C000-1FFFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x0,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x0,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x0,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x0,Enabled CONFIG6L~5~1=0x10,0x10,Disabled CONFIG6L~5~2=0x10,0x0,Enabled CONFIG6L~6~1=0x20,0x20,Disabled CONFIG6L~6~2=0x20,0x0,Enabled CONFIG6L~7~1=0x40,0x40,Disabled CONFIG6L~7~2=0x40,0x0,Enabled CONFIG6L~8~1=0x80,0x80,Disabled CONFIG6L~8~2=0x80,0x0,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTC,0x20,Config. Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTD,0x80,Data EE Write Protect CONFIG6H~1~1=0x20,0x20,Disabled CONFIG6H~1~2=0x20,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x80,0x80,Disabled CONFIG6H~3~2=0x80,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBRT0,0x1,Table Read Protect 00800-03FFF CONFIG7L~2=EBRT1,0x2,Table Read Protect 04000-07FFF CONFIG7L~3=EBRT2,0x4,Table Read Protect 08000-0BFFF CONFIG7L~4=EBRT3,0x8,Table Read Protect 0C000-0FFFF CONFIG7L~5=EBRT4,0x10,Table Read Protect 10000-13FFF CONFIG7L~6=EBRT5,0x20,Table Read Protect 14000-17FFF CONFIG7L~7=EBRT6,0x40,Table Read Protect 18000-1BFFF CONFIG7L~8=EBRT7,0x80,Table Read Protect 1C000-1FFFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x0,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x0,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x0,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x0,Enabled CONFIG7L~5~1=0x10,0x10,Disabled CONFIG7L~5~2=0x10,0x0,Enabled CONFIG7L~6~1=0x20,0x20,Disabled CONFIG7L~6~2=0x20,0x0,Enabled CONFIG7L~7~1=0x40,0x40,Disabled CONFIG7L~7~2=0x40,0x0,Enabled CONFIG7L~8~1=0x80,0x80,Disabled CONFIG7L~8~2=0x80,0x0,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBRTB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F87K90] pgmmem=0x0 ~pgmmem=0x1ffff cfgmem=0x300000 ~cfgmem=0x30000d userid=0x200000 ~userid=0x200007 eedata=0x0 ~eedata=0x3ff devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0x5140 configslots=14 0x300000=CONFIG1L 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004=CONFIG3L 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000a=CONFIG6L 0x30000b=CONFIG6H 0x30000c=CONFIG7L 0x30000d=CONFIG7H CONFIG1L_unused=0x0 CONFIG1L~1=RETEN,0x1,VREG Sleep Enable bit CONFIG1L~2=SOSCEL,0x18,SOSC Power Selection and mode Configuration bits CONFIG1L~3=XINST,0x40,Extended Instruction Set CONFIG1L~1~1=0x1,0x1,Enabled CONFIG1L~1~2=0x1,0x0,Disabled CONFIG1L~2~1=0x18,0x18,High Power SOSC circuit selected CONFIG1L~2~2=0x18,0x8,Low Power SOSC circuit selected CONFIG1L~2~3=0x18,0x10,Digital (SCLKI) mode CONFIG1L~3~1=0x40,0x40,Enabled CONFIG1L~3~2=0x40,0x0,Disabled CONFIG1H_unused=0x0 CONFIG1H~1=FOSC,0xf,Oscillator CONFIG1H~2=PLLCFG,0x10,PLL x4 Enable bit CONFIG1H~3=PRCKEN,0x20,Primary Clock Enable bit CONFIG1H~4=FCMEN,0x40,Fail-Safe Clock Monitor CONFIG1H~5=IESO,0x80,Internal External Oscillator Switch Over Mode CONFIG1H~1~1=0x7,0x7,External RC oscillator CONFIG1H~1~2=0x7,0x6,External RC oscillator, CLKOUT function on OSC2 CONFIG1H~1~3=0xf,0xd,EC oscillator (Low power, DC - 160 kHz) CONFIG1H~1~4=0xf,0xc,EC oscillator, CLKOUT function on OSC2 (Low power, DC - 160 kHz) CONFIG1H~1~5=0xf,0xb,EC oscillator (Medium power, 160 kHz - 4 MHz) CONFIG1H~1~6=0xf,0xa,EC oscillator, CLKOUT function on OSC2 (Medium power, 160 kHz - 4 MHz) CONFIG1H~1~7=0xf,0x9,Internal RC oscillator, CLKOUT function on OSC2 CONFIG1H~1~8=0xf,0x8,Internal RC oscillator CONFIG1H~1~9=0xf,0x5,EC oscillator (High power, 16 MHz - 25 MHz) CONFIG1H~1~10=0xf,0x4,EC oscillator, CLKOUT function on OSC2 (High power, 16 MHz - 25 MHz) CONFIG1H~1~11=0xf,0x3,HS oscillator (Medium power, 4 MHz - 16 MHz) CONFIG1H~1~12=0xf,0x2,HS oscillator (High power, 16 MHz - 25 MHz) CONFIG1H~1~13=0xf,0x1,XT oscillator CONFIG1H~1~14=0xf,0x0,LP oscillator CONFIG1H~2~1=0x10,0x10,Enabled CONFIG1H~2~2=0x10,0x0,Disabled CONFIG1H~3~1=0x20,0x0,Disabled CONFIG1H~3~2=0x20,0x20,Enabled CONFIG1H~4~1=0x40,0x0,Disabled CONFIG1H~4~2=0x40,0x40,Enabled CONFIG1H~5~1=0x80,0x0,Disabled CONFIG1H~5~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PWRTEN,0x1,Power Up Timer CONFIG2L~2=BOREN,0x6,Brown Out Detect CONFIG2L~3=BORV,0x18,Brown-out Reset Voltage bits CONFIG2L~4=BORPWR,0x60,BORMV Power level CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active, disabled in SLEEP, SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,1.8V CONFIG2L~3~2=0x18,0x10,2.0V CONFIG2L~3~3=0x18,0x8,2.7V CONFIG2L~3~4=0x18,0x0,3.0V CONFIG2L~4~1=0x60,0x60,ZPBORMV instead of BORMV is selected CONFIG2L~4~2=0x60,0x40,BORMV set to high power level CONFIG2L~4~3=0x60,0x20,BORMV set to medium power level CONFIG2L~4~4=0x60,0x0,BORMV set to low power level CONFIG2H_unused=0x0 CONFIG2H~1=WDTEN,0x3,Watchdog Timer CONFIG2H~2=WDTPS,0x7c,Watchdog Postscaler CONFIG2H~1~1=0x3,0x3,Enabled in hardware, SWDTEN disabled CONFIG2H~1~2=0x3,0x2,Enabled while active, disabled in SLEEP, SWDTEN disabled CONFIG2H~1~3=0x3,0x1,Controlled with SWDTEN bit CONFIG2H~1~4=0x3,0x0,Disabled in hardware, SWDTEN disabled CONFIG2H~2~1=0x7c,0x7c,1:1048576 CONFIG2H~2~2=0x7c,0x4c,1:524288 CONFIG2H~2~3=0x7c,0x48,1:262144 CONFIG2H~2~4=0x7c,0x44,1:131072 CONFIG2H~2~5=0x7c,0x40,1:65536 CONFIG2H~2~6=0x7c,0x3c,1:32768 CONFIG2H~2~7=0x7c,0x38,1:16384 CONFIG2H~2~8=0x7c,0x34,1:8192 CONFIG2H~2~9=0x7c,0x30,1:4096 CONFIG2H~2~10=0x7c,0x2c,1:2048 CONFIG2H~2~11=0x7c,0x28,1:1024 CONFIG2H~2~12=0x7c,0x24,1:512 CONFIG2H~2~13=0x7c,0x20,1:256 CONFIG2H~2~14=0x7c,0x1c,1:128 CONFIG2H~2~15=0x7c,0x18,1:64 CONFIG2H~2~16=0x7c,0x14,1:32 CONFIG2H~2~17=0x7c,0x10,1:16 CONFIG2H~2~18=0x7c,0xc,1:8 CONFIG2H~2~19=0x7c,0x8,1:4 CONFIG2H~2~20=0x7c,0x4,1:2 CONFIG2H~2~21=0x7c,0x0,1:1 CONFIG3L_unused=0x0 CONFIG3L~1=RTCOSC,0x1,RTCC Clock Select CONFIG3L~1~1=0x1,0x1,RTCC uses T1OSC/T1CKI CONFIG3L~1~2=0x1,0x0,RTCC uses INTRC CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MX,0x1,CCP2 Mux CONFIG3H~2=ECCPMX,0x2,ECCP Mux CONFIG3H~3=MSSPMSK,0x8,MSSP address masking CONFIG3H~4=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,RC1 CONFIG3H~1~2=0x1,0x0,RE7-Microcontroller Mode/RB3-All other modes CONFIG3H~2~1=0x2,0x2,Enhanced CCP1/3 [P1B/P1C/P3B/P3C] muxed with RE6/RE5/RE4/RE3 CONFIG3H~2~2=0x2,0x0,Enhanced CCP1/3 [P1B/P1C/P3B/P3C] muxed with RH7/RH6/RH5/RH4 CONFIG3H~3~1=0x8,0x8,7 Bit address masking mode CONFIG3H~3~2=0x8,0x0,5 bit address masking mode CONFIG3H~4~1=0x80,0x80,MCLR Enabled, RG5 Disabled CONFIG3H~4~2=0x80,0x0,MCLR Disabled, RG5 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVREN,0x1,Stack Overflow Reset CONFIG4L~2=BBSIZ0,0x10,Boot Block Size CONFIG4L~3=DEBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x10,0x10,2K word Boot Block size CONFIG4L~2~2=0x10,0x0,1K word Boot Block size CONFIG4L~3~1=0x80,0x80,Disabled CONFIG4L~3~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP0,0x1,Code Protect 00800-03FFF CONFIG5L~2=CP1,0x2,Code Protect 04000-07FFF CONFIG5L~3=CP2,0x4,Code Protect 08000-0BFFF CONFIG5L~4=CP3,0x8,Code Protect 0C000-0FFFF CONFIG5L~5=CP4,0x10,Code Protect 10000-13FFF CONFIG5L~6=CP5,0x20,Code Protect 14000-17FFF CONFIG5L~7=CP6,0x40,Code Protect 18000-1BFFF CONFIG5L~8=CP7,0x80,Code Protect 1C000-1FFFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x0,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x0,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x0,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x0,Enabled CONFIG5L~5~1=0x10,0x10,Disabled CONFIG5L~5~2=0x10,0x0,Enabled CONFIG5L~6~1=0x20,0x20,Disabled CONFIG5L~6~2=0x20,0x0,Enabled CONFIG5L~7~1=0x40,0x40,Disabled CONFIG5L~7~2=0x40,0x0,Enabled CONFIG5L~8~1=0x80,0x80,Disabled CONFIG5L~8~2=0x80,0x0,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPB,0x40,Code Protect Boot CONFIG5H~2=CPD,0x80,Data EE Read Protect CONFIG5H~1~1=0x40,0x40,Disabled CONFIG5H~1~2=0x40,0x0,Enabled CONFIG5H~2~1=0x80,0x80,Disabled CONFIG5H~2~2=0x80,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT0,0x1,Table Write Protect 00800-03FFF CONFIG6L~2=WRT1,0x2,Table Write Protect 04000-07FFF CONFIG6L~3=WRT2,0x4,Table Write Protect 08000-0BFFF CONFIG6L~4=WRT3,0x8,Table Write Protect 0C000-0FFFF CONFIG6L~5=WRT4,0x10,Table Write Protect 10000-13FFF CONFIG6L~6=WRT5,0x20,Table Write Protect 14000-17FFF CONFIG6L~7=WRT6,0x40,Table Write Protect 18000-1BFFF CONFIG6L~8=WRT7,0x80,Table Write Protect 1C000-1FFFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x0,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x0,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x0,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x0,Enabled CONFIG6L~5~1=0x10,0x10,Disabled CONFIG6L~5~2=0x10,0x0,Enabled CONFIG6L~6~1=0x20,0x20,Disabled CONFIG6L~6~2=0x20,0x0,Enabled CONFIG6L~7~1=0x40,0x40,Disabled CONFIG6L~7~2=0x40,0x0,Enabled CONFIG6L~8~1=0x80,0x80,Disabled CONFIG6L~8~2=0x80,0x0,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTC,0x20,Config. Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTD,0x80,Data EE Write Protect CONFIG6H~1~1=0x20,0x20,Disabled CONFIG6H~1~2=0x20,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x80,0x80,Disabled CONFIG6H~3~2=0x80,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBRT0,0x1,Table Read Protect 00800-03FFF CONFIG7L~2=EBRT1,0x2,Table Read Protect 04000-07FFF CONFIG7L~3=EBRT2,0x4,Table Read Protect 08000-0BFFF CONFIG7L~4=EBRT3,0x8,Table Read Protect 0C000-0FFFF CONFIG7L~5=EBRT4,0x10,Table Read Protect 10000-13FFF CONFIG7L~6=EBRT5,0x20,Table Read Protect 14000-17FFF CONFIG7L~7=EBRT6,0x40,Table Read Protect 18000-1BFFF CONFIG7L~8=EBRT7,0x80,Table Read Protect 1C000-1FFFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x0,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x0,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x0,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x0,Enabled CONFIG7L~5~1=0x10,0x10,Disabled CONFIG7L~5~2=0x10,0x0,Enabled CONFIG7L~6~1=0x20,0x20,Disabled CONFIG7L~6~2=0x20,0x0,Enabled CONFIG7L~7~1=0x40,0x40,Disabled CONFIG7L~7~2=0x40,0x0,Enabled CONFIG7L~8~1=0x80,0x80,Disabled CONFIG7L~8~2=0x80,0x0,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBRTB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F63J11] pgmmem=0x0 ~pgmmem=0x1fff7 cfgmem=0x1fff8 ~cfgmem=0x1ffff userid= ~userid= eedata=0x00 ~eedata=0xf5f devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x3900 configslots=8 0x1fff8=CONFIG1L 0x1fff9=CONFIG1H 0x1fffa=CONFIG2L 0x1fffb=CONFIG2H 0x1fffc=CONFIG3L 0x1fffd=CONFIG3H 0x1fffe=CONFIG4L 0x1ffff=CONFIG4H CONFIG1L_unused=0x00 CONFIG1L~1=WDTEN,0x01,Watchdog Timer Enable CONFIG1L~2=STVREN,0x0E,PLL Configuration CONFIG1L~3=ENHCPU,0x20,Stack Overflow Reset CONFIG1L~4=EXTCPU,0x40,Extended CPU CONFIG1L~5=BACKBUG,0x80,Background Debug CONFIG1L~1~1=0x01,0x01,Enabled CONFIG1L~1~2=0x01,0x00,Disabled CONFIG1L~2~1=0x0E,0x0E,No Divide (4MHz input) CONFIG1L~2~2=0x0E,0x0C,Divide by 2 (8MHz input) CONFIG1L~2~3=0x0E,0x0A,Divide by 3 (12MHz input) CONFIG1L~2~4=0x0E,0x08,Divide by 4 (16MHz input) CONFIG1L~2~5=0x0E,0x06,Divide by 5 (20MHz input) CONFIG1L~2~6=0x0E,0x04,Divide by 6 (24MHz input) CONFIG1L~2~7=0x0E,0x02,Divide by 10 (40MHz input) CONFIG1L~2~8=0x0E,0x00,Divide by 12 (48MHz input) CONFIG1L~3~1=0x20,0x20,Enabled CONFIG1L~3~2=0x20,0x00,Disabled CONFIG1L~4~1=0x40,0x40,Enabled CONFIG1L~4~2=0x40,0x00,Disabled CONFIG1L~5~1=0x80,0x80,Disabled CONFIG1L~5~2=0x80,0x00,Enabled CONFIG1H_unused=0x00 CONFIG1H~1=CPDIV,0x3,CPU Clock Divider CONFIG1H~2=CP_0,0x4,Code Protection CONFIG1H~1~1=0x3,0x3,No divide CONFIG1H~1~2=0x3,0x2,Divide by 2 CONFIG1H~1~3=0x3,0x1,Divide by 3 CONFIG1H~1~4=0x3,0x0,Divide by 6 CONFIG1H~2~1=0x4,0x4,Disabled CONFIG1H~2~2=0x4,0x00,Enabled CONFIG2L_unused=0x00 CONFIG2L~1=FOSC,0x07,Oscillator CONFIG2L~2=FCMEN,0x40,Fail Safe Monitor Clock Enable CONFIG2L~3=IESO,0x80,Internal External Switch Over Enable CONFIG2L~1~1=0x07,0x07,EC+PLL(CLKO-RA6) USB-EC+PLL CONFIG2L~1~2=0x07,0x06,EC(CLKO-RA6) USB-EC CONFIG2L~1~3=0x07,0x05,HS+PLL USB-HS+PLL CONFIG2L~1~4=0x07,0x04,HS USB-HS CONFIG2L~1~5=0x07,0x03,INTOSC EC+PLL Osc with CLKOUT CONFIG2L~1~6=0x07,0x02,INTOSC EC Osc with CLKOUT CONFIG2L~1~7=0x07,0x01,INTOSC HS+PLL Osc CONFIG2L~1~8=0x07,0x00,INTOSC HS Osc CONFIG2L~2~1=0x40,0x40,Enabled CONFIG2L~2~2=0x40,0x00,Disabled CONFIG2L~3~1=0x80,0x80,Enabled CONFIG2L~3~2=0x80,0x00,Disabled CONFIG2H_unused=0x00 CONFIG2H~1=WDTPS,0x0f,Watchdog Timer Postscale CONFIG2H~1~1=0x000f,0x000f,1:32,768 CONFIG2H~1~2=0x000f,0x000e,1:16,384 CONFIG2H~1~3=0x000f,0x000d,1:8,192 CONFIG2H~1~4=0x000f,0x000c,1:4,096 CONFIG2H~1~5=0x000f,0x000b,1:2,048 CONFIG2H~1~6=0x000f,0x000a,1:1,024 CONFIG2H~1~7=0x000f,0x0009,1:512 CONFIG2H~1~8=0x000f,0x0008,1:256 CONFIG2H~1~9=0x000f,0x0007,1:128 CONFIG2H~1~10=0x000f,0x0006,1:64 CONFIG2H~1~11=0x000f,0x0005,1:32 CONFIG2H~1~12=0x000f,0x0004,1:16 CONFIG2H~1~13=0x000f,0x0003,1:8 CONFIG2H~1~14=0x000f,0x0002,1:4 CONFIG2H~1~15=0x000f,0x0001,1:2 CONFIG2H~1~16=0x000f,0x0000,1:1 CONFIG3L_unused=0x00 CONFIG3H_unused=0x00 CONFIG3H~1=CCP2MX,0x01,CCP2 Mux CONFIG3H~2=ECCPXM,0x02,ECCP Mux CONFIG3H~1~1=0x01,0x01,ECCP2 I/O Muxed With RC1 CONFIG3H~1~2=0x01,0x00,ECCP2 IP Muxed With RE7 CONFIG3H~2~1=0x02,0x02,P1B/P1C On RE6/RE5, P3B/P3C On RE4/RE3 CONFIG3H~2~2=0x02,0x00,P1B/P1C On RH7/RH6, P3B/P3C Onto RH5/RH4 CONFIG4L_unused=0x00 CONFIG4H_unused=0x00 erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F63J90] pgmmem=0x0 ~pgmmem=0x1fff7 cfgmem=0x1fff8 ~cfgmem=0x1ffff userid= ~userid= eedata=0x00 ~eedata=0xf5f devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x3800 configslots=8 0x1fff8=CONFIG1L 0x1fff9=CONFIG1H 0x1fffa=CONFIG2L 0x1fffb=CONFIG2H 0x1fffc=CONFIG3L 0x1fffd=CONFIG3H 0x1fffe=CONFIG4L 0x1ffff=CONFIG4H CONFIG1L_unused=0x00 CONFIG1L~1=WDTEN,0x01,Watchdog Timer Enable CONFIG1L~2=STVREN,0x0E,PLL Configuration CONFIG1L~3=ENHCPU,0x20,Stack Overflow Reset CONFIG1L~4=EXTCPU,0x40,Extended CPU CONFIG1L~5=BACKBUG,0x80,Background Debug CONFIG1L~1~1=0x01,0x01,Enabled CONFIG1L~1~2=0x01,0x00,Disabled CONFIG1L~2~1=0x0E,0x0E,No Divide (4MHz input) CONFIG1L~2~2=0x0E,0x0C,Divide by 2 (8MHz input) CONFIG1L~2~3=0x0E,0x0A,Divide by 3 (12MHz input) CONFIG1L~2~4=0x0E,0x08,Divide by 4 (16MHz input) CONFIG1L~2~5=0x0E,0x06,Divide by 5 (20MHz input) CONFIG1L~2~6=0x0E,0x04,Divide by 6 (24MHz input) CONFIG1L~2~7=0x0E,0x02,Divide by 10 (40MHz input) CONFIG1L~2~8=0x0E,0x00,Divide by 12 (48MHz input) CONFIG1L~3~1=0x20,0x20,Enabled CONFIG1L~3~2=0x20,0x00,Disabled CONFIG1L~4~1=0x40,0x40,Enabled CONFIG1L~4~2=0x40,0x00,Disabled CONFIG1L~5~1=0x80,0x80,Disabled CONFIG1L~5~2=0x80,0x00,Enabled CONFIG1H_unused=0x00 CONFIG1H~1=CPDIV,0x3,CPU Clock Divider CONFIG1H~2=CP_0,0x4,Code Protection CONFIG1H~1~1=0x3,0x3,No divide CONFIG1H~1~2=0x3,0x2,Divide by 2 CONFIG1H~1~3=0x3,0x1,Divide by 3 CONFIG1H~1~4=0x3,0x0,Divide by 6 CONFIG1H~2~1=0x4,0x4,Disabled CONFIG1H~2~2=0x4,0x00,Enabled CONFIG2L_unused=0x00 CONFIG2L~1=FOSC,0x07,Oscillator CONFIG2L~2=FCMEN,0x40,Fail Safe Monitor Clock Enable CONFIG2L~3=IESO,0x80,Internal External Switch Over Enable CONFIG2L~1~1=0x07,0x07,EC+PLL(CLKO-RA6) USB-EC+PLL CONFIG2L~1~2=0x07,0x06,EC(CLKO-RA6) USB-EC CONFIG2L~1~3=0x07,0x05,HS+PLL USB-HS+PLL CONFIG2L~1~4=0x07,0x04,HS USB-HS CONFIG2L~1~5=0x07,0x03,INTOSC EC+PLL Osc with CLKOUT CONFIG2L~1~6=0x07,0x02,INTOSC EC Osc with CLKOUT CONFIG2L~1~7=0x07,0x01,INTOSC HS+PLL Osc CONFIG2L~1~8=0x07,0x00,INTOSC HS Osc CONFIG2L~2~1=0x40,0x40,Enabled CONFIG2L~2~2=0x40,0x00,Disabled CONFIG2L~3~1=0x80,0x80,Enabled CONFIG2L~3~2=0x80,0x00,Disabled CONFIG2H_unused=0x00 CONFIG2H~1=WDTPS,0x0f,Watchdog Timer Postscale CONFIG2H~1~1=0x000f,0x000f,1:32,768 CONFIG2H~1~2=0x000f,0x000e,1:16,384 CONFIG2H~1~3=0x000f,0x000d,1:8,192 CONFIG2H~1~4=0x000f,0x000c,1:4,096 CONFIG2H~1~5=0x000f,0x000b,1:2,048 CONFIG2H~1~6=0x000f,0x000a,1:1,024 CONFIG2H~1~7=0x000f,0x0009,1:512 CONFIG2H~1~8=0x000f,0x0008,1:256 CONFIG2H~1~9=0x000f,0x0007,1:128 CONFIG2H~1~10=0x000f,0x0006,1:64 CONFIG2H~1~11=0x000f,0x0005,1:32 CONFIG2H~1~12=0x000f,0x0004,1:16 CONFIG2H~1~13=0x000f,0x0003,1:8 CONFIG2H~1~14=0x000f,0x0002,1:4 CONFIG2H~1~15=0x000f,0x0001,1:2 CONFIG2H~1~16=0x000f,0x0000,1:1 CONFIG3L_unused=0x00 CONFIG3H_unused=0x00 CONFIG3H~1=CCP2MX,0x01,CCP2 Mux CONFIG3H~2=ECCPXM,0x02,ECCP Mux CONFIG3H~1~1=0x01,0x01,ECCP2 I/O Muxed With RC1 CONFIG3H~1~2=0x01,0x00,ECCP2 IP Muxed With RE7 CONFIG3H~2~1=0x02,0x02,P1B/P1C On RE6/RE5, P3B/P3C On RE4/RE3 CONFIG3H~2~2=0x02,0x00,P1B/P1C On RH7/RH6, P3B/P3C Onto RH5/RH4 CONFIG4L_unused=0x00 CONFIG4H_unused=0x00 erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F64J11] pgmmem=0x0 ~pgmmem=0x1fff7 cfgmem=0x1fff8 ~cfgmem=0x1ffff userid= ~userid= eedata=0x00 ~eedata=0xf5f devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x3920 configslots=8 0x1fff8=CONFIG1L 0x1fff9=CONFIG1H 0x1fffa=CONFIG2L 0x1fffb=CONFIG2H 0x1fffc=CONFIG3L 0x1fffd=CONFIG3H 0x1fffe=CONFIG4L 0x1ffff=CONFIG4H CONFIG1L_unused=0x00 CONFIG1L~1=WDTEN,0x01,Watchdog Timer Enable CONFIG1L~2=STVREN,0x0E,PLL Configuration CONFIG1L~3=ENHCPU,0x20,Stack Overflow Reset CONFIG1L~4=EXTCPU,0x40,Extended CPU CONFIG1L~5=BACKBUG,0x80,Background Debug CONFIG1L~1~1=0x01,0x01,Enabled CONFIG1L~1~2=0x01,0x00,Disabled CONFIG1L~2~1=0x0E,0x0E,No Divide (4MHz input) CONFIG1L~2~2=0x0E,0x0C,Divide by 2 (8MHz input) CONFIG1L~2~3=0x0E,0x0A,Divide by 3 (12MHz input) CONFIG1L~2~4=0x0E,0x08,Divide by 4 (16MHz input) CONFIG1L~2~5=0x0E,0x06,Divide by 5 (20MHz input) CONFIG1L~2~6=0x0E,0x04,Divide by 6 (24MHz input) CONFIG1L~2~7=0x0E,0x02,Divide by 10 (40MHz input) CONFIG1L~2~8=0x0E,0x00,Divide by 12 (48MHz input) CONFIG1L~3~1=0x20,0x20,Enabled CONFIG1L~3~2=0x20,0x00,Disabled CONFIG1L~4~1=0x40,0x40,Enabled CONFIG1L~4~2=0x40,0x00,Disabled CONFIG1L~5~1=0x80,0x80,Disabled CONFIG1L~5~2=0x80,0x00,Enabled CONFIG1H_unused=0x00 CONFIG1H~1=CPDIV,0x3,CPU Clock Divider CONFIG1H~2=CP_0,0x4,Code Protection CONFIG1H~1~1=0x3,0x3,No divide CONFIG1H~1~2=0x3,0x2,Divide by 2 CONFIG1H~1~3=0x3,0x1,Divide by 3 CONFIG1H~1~4=0x3,0x0,Divide by 6 CONFIG1H~2~1=0x4,0x4,Disabled CONFIG1H~2~2=0x4,0x00,Enabled CONFIG2L_unused=0x00 CONFIG2L~1=FOSC,0x07,Oscillator CONFIG2L~2=FCMEN,0x40,Fail Safe Monitor Clock Enable CONFIG2L~3=IESO,0x80,Internal External Switch Over Enable CONFIG2L~1~1=0x07,0x07,EC+PLL(CLKO-RA6) USB-EC+PLL CONFIG2L~1~2=0x07,0x06,EC(CLKO-RA6) USB-EC CONFIG2L~1~3=0x07,0x05,HS+PLL USB-HS+PLL CONFIG2L~1~4=0x07,0x04,HS USB-HS CONFIG2L~1~5=0x07,0x03,INTOSC EC+PLL Osc with CLKOUT CONFIG2L~1~6=0x07,0x02,INTOSC EC Osc with CLKOUT CONFIG2L~1~7=0x07,0x01,INTOSC HS+PLL Osc CONFIG2L~1~8=0x07,0x00,INTOSC HS Osc CONFIG2L~2~1=0x40,0x40,Enabled CONFIG2L~2~2=0x40,0x00,Disabled CONFIG2L~3~1=0x80,0x80,Enabled CONFIG2L~3~2=0x80,0x00,Disabled CONFIG2H_unused=0x00 CONFIG2H~1=WDTPS,0x0f,Watchdog Timer Postscale CONFIG2H~1~1=0x000f,0x000f,1:32,768 CONFIG2H~1~2=0x000f,0x000e,1:16,384 CONFIG2H~1~3=0x000f,0x000d,1:8,192 CONFIG2H~1~4=0x000f,0x000c,1:4,096 CONFIG2H~1~5=0x000f,0x000b,1:2,048 CONFIG2H~1~6=0x000f,0x000a,1:1,024 CONFIG2H~1~7=0x000f,0x0009,1:512 CONFIG2H~1~8=0x000f,0x0008,1:256 CONFIG2H~1~9=0x000f,0x0007,1:128 CONFIG2H~1~10=0x000f,0x0006,1:64 CONFIG2H~1~11=0x000f,0x0005,1:32 CONFIG2H~1~12=0x000f,0x0004,1:16 CONFIG2H~1~13=0x000f,0x0003,1:8 CONFIG2H~1~14=0x000f,0x0002,1:4 CONFIG2H~1~15=0x000f,0x0001,1:2 CONFIG2H~1~16=0x000f,0x0000,1:1 CONFIG3L_unused=0x00 CONFIG3H_unused=0x00 CONFIG3H~1=CCP2MX,0x01,CCP2 Mux CONFIG3H~2=ECCPXM,0x02,ECCP Mux CONFIG3H~1~1=0x01,0x01,ECCP2 I/O Muxed With RC1 CONFIG3H~1~2=0x01,0x00,ECCP2 IP Muxed With RE7 CONFIG3H~2~1=0x02,0x02,P1B/P1C On RE6/RE5, P3B/P3C On RE4/RE3 CONFIG3H~2~2=0x02,0x00,P1B/P1C On RH7/RH6, P3B/P3C Onto RH5/RH4 CONFIG4L_unused=0x00 CONFIG4H_unused=0x00 erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F64J90] pgmmem=0x0 ~pgmmem=0x1fff7 cfgmem=0x1fff8 ~cfgmem=0x1ffff userid= ~userid= eedata=0x00 ~eedata=0xf5f devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x3820 configslots=8 0x1fff8=CONFIG1L 0x1fff9=CONFIG1H 0x1fffa=CONFIG2L 0x1fffb=CONFIG2H 0x1fffc=CONFIG3L 0x1fffd=CONFIG3H 0x1fffe=CONFIG4L 0x1ffff=CONFIG4H CONFIG1L_unused=0x00 CONFIG1L~1=WDTEN,0x01,Watchdog Timer Enable CONFIG1L~2=STVREN,0x0E,PLL Configuration CONFIG1L~3=ENHCPU,0x20,Stack Overflow Reset CONFIG1L~4=EXTCPU,0x40,Extended CPU CONFIG1L~5=BACKBUG,0x80,Background Debug CONFIG1L~1~1=0x01,0x01,Enabled CONFIG1L~1~2=0x01,0x00,Disabled CONFIG1L~2~1=0x0E,0x0E,No Divide (4MHz input) CONFIG1L~2~2=0x0E,0x0C,Divide by 2 (8MHz input) CONFIG1L~2~3=0x0E,0x0A,Divide by 3 (12MHz input) CONFIG1L~2~4=0x0E,0x08,Divide by 4 (16MHz input) CONFIG1L~2~5=0x0E,0x06,Divide by 5 (20MHz input) CONFIG1L~2~6=0x0E,0x04,Divide by 6 (24MHz input) CONFIG1L~2~7=0x0E,0x02,Divide by 10 (40MHz input) CONFIG1L~2~8=0x0E,0x00,Divide by 12 (48MHz input) CONFIG1L~3~1=0x20,0x20,Enabled CONFIG1L~3~2=0x20,0x00,Disabled CONFIG1L~4~1=0x40,0x40,Enabled CONFIG1L~4~2=0x40,0x00,Disabled CONFIG1L~5~1=0x80,0x80,Disabled CONFIG1L~5~2=0x80,0x00,Enabled CONFIG1H_unused=0x00 CONFIG1H~1=CPDIV,0x3,CPU Clock Divider CONFIG1H~2=CP_0,0x4,Code Protection CONFIG1H~1~1=0x3,0x3,No divide CONFIG1H~1~2=0x3,0x2,Divide by 2 CONFIG1H~1~3=0x3,0x1,Divide by 3 CONFIG1H~1~4=0x3,0x0,Divide by 6 CONFIG1H~2~1=0x4,0x4,Disabled CONFIG1H~2~2=0x4,0x00,Enabled CONFIG2L_unused=0x00 CONFIG2L~1=FOSC,0x07,Oscillator CONFIG2L~2=FCMEN,0x40,Fail Safe Monitor Clock Enable CONFIG2L~3=IESO,0x80,Internal External Switch Over Enable CONFIG2L~1~1=0x07,0x07,EC+PLL(CLKO-RA6) USB-EC+PLL CONFIG2L~1~2=0x07,0x06,EC(CLKO-RA6) USB-EC CONFIG2L~1~3=0x07,0x05,HS+PLL USB-HS+PLL CONFIG2L~1~4=0x07,0x04,HS USB-HS CONFIG2L~1~5=0x07,0x03,INTOSC EC+PLL Osc with CLKOUT CONFIG2L~1~6=0x07,0x02,INTOSC EC Osc with CLKOUT CONFIG2L~1~7=0x07,0x01,INTOSC HS+PLL Osc CONFIG2L~1~8=0x07,0x00,INTOSC HS Osc CONFIG2L~2~1=0x40,0x40,Enabled CONFIG2L~2~2=0x40,0x00,Disabled CONFIG2L~3~1=0x80,0x80,Enabled CONFIG2L~3~2=0x80,0x00,Disabled CONFIG2H_unused=0x00 CONFIG2H~1=WDTPS,0x0f,Watchdog Timer Postscale CONFIG2H~1~1=0x000f,0x000f,1:32,768 CONFIG2H~1~2=0x000f,0x000e,1:16,384 CONFIG2H~1~3=0x000f,0x000d,1:8,192 CONFIG2H~1~4=0x000f,0x000c,1:4,096 CONFIG2H~1~5=0x000f,0x000b,1:2,048 CONFIG2H~1~6=0x000f,0x000a,1:1,024 CONFIG2H~1~7=0x000f,0x0009,1:512 CONFIG2H~1~8=0x000f,0x0008,1:256 CONFIG2H~1~9=0x000f,0x0007,1:128 CONFIG2H~1~10=0x000f,0x0006,1:64 CONFIG2H~1~11=0x000f,0x0005,1:32 CONFIG2H~1~12=0x000f,0x0004,1:16 CONFIG2H~1~13=0x000f,0x0003,1:8 CONFIG2H~1~14=0x000f,0x0002,1:4 CONFIG2H~1~15=0x000f,0x0001,1:2 CONFIG2H~1~16=0x000f,0x0000,1:1 CONFIG3L_unused=0x00 CONFIG3H_unused=0x00 CONFIG3H~1=CCP2MX,0x01,CCP2 Mux CONFIG3H~2=ECCPXM,0x02,ECCP Mux CONFIG3H~1~1=0x01,0x01,ECCP2 I/O Muxed With RC1 CONFIG3H~1~2=0x01,0x00,ECCP2 IP Muxed With RE7 CONFIG3H~2~1=0x02,0x02,P1B/P1C On RE6/RE5, P3B/P3C On RE4/RE3 CONFIG3H~2~2=0x02,0x00,P1B/P1C On RH7/RH6, P3B/P3C Onto RH5/RH4 CONFIG4L_unused=0x00 CONFIG4H_unused=0x00 erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F65J10] pgmmem=0x0 ~pgmmem=0x1fff7 cfgmem=0x1fff8 ~cfgmem=0x1ffff userid= ~userid= eedata=0x00 ~eedata=0xf5f devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x1520 configslots=8 0x1fff8=CONFIG1L 0x1fff9=CONFIG1H 0x1fffa=CONFIG2L 0x1fffb=CONFIG2H 0x1fffc=CONFIG3L 0x1fffd=CONFIG3H 0x1fffe=CONFIG4L 0x1ffff=CONFIG4H CONFIG1L_unused=0x00 CONFIG1L~1=WDTEN,0x01,Watchdog Timer Enable CONFIG1L~2=STVREN,0x0E,PLL Configuration CONFIG1L~3=ENHCPU,0x20,Stack Overflow Reset CONFIG1L~4=EXTCPU,0x40,Extended CPU CONFIG1L~5=BACKBUG,0x80,Background Debug CONFIG1L~1~1=0x01,0x01,Enabled CONFIG1L~1~2=0x01,0x00,Disabled CONFIG1L~2~1=0x0E,0x0E,No Divide (4MHz input) CONFIG1L~2~2=0x0E,0x0C,Divide by 2 (8MHz input) CONFIG1L~2~3=0x0E,0x0A,Divide by 3 (12MHz input) CONFIG1L~2~4=0x0E,0x08,Divide by 4 (16MHz input) CONFIG1L~2~5=0x0E,0x06,Divide by 5 (20MHz input) CONFIG1L~2~6=0x0E,0x04,Divide by 6 (24MHz input) CONFIG1L~2~7=0x0E,0x02,Divide by 10 (40MHz input) CONFIG1L~2~8=0x0E,0x00,Divide by 12 (48MHz input) CONFIG1L~3~1=0x20,0x20,Enabled CONFIG1L~3~2=0x20,0x00,Disabled CONFIG1L~4~1=0x40,0x40,Enabled CONFIG1L~4~2=0x40,0x00,Disabled CONFIG1L~5~1=0x80,0x80,Disabled CONFIG1L~5~2=0x80,0x00,Enabled CONFIG1H_unused=0x00 CONFIG1H~1=CPDIV,0x3,CPU Clock Divider CONFIG1H~2=CP_0,0x4,Code Protection CONFIG1H~1~1=0x3,0x3,No divide CONFIG1H~1~2=0x3,0x2,Divide by 2 CONFIG1H~1~3=0x3,0x1,Divide by 3 CONFIG1H~1~4=0x3,0x0,Divide by 6 CONFIG1H~2~1=0x4,0x4,Disabled CONFIG1H~2~2=0x4,0x00,Enabled CONFIG2L_unused=0x00 CONFIG2L~1=FOSC,0x07,Oscillator CONFIG2L~2=FCMEN,0x40,Fail Safe Monitor Clock Enable CONFIG2L~3=IESO,0x80,Internal External Switch Over Enable CONFIG2L~1~1=0x07,0x07,EC+PLL(CLKO-RA6) USB-EC+PLL CONFIG2L~1~2=0x07,0x06,EC(CLKO-RA6) USB-EC CONFIG2L~1~3=0x07,0x05,HS+PLL USB-HS+PLL CONFIG2L~1~4=0x07,0x04,HS USB-HS CONFIG2L~1~5=0x07,0x03,INTOSC EC+PLL Osc with CLKOUT CONFIG2L~1~6=0x07,0x02,INTOSC EC Osc with CLKOUT CONFIG2L~1~7=0x07,0x01,INTOSC HS+PLL Osc CONFIG2L~1~8=0x07,0x00,INTOSC HS Osc CONFIG2L~2~1=0x40,0x40,Enabled CONFIG2L~2~2=0x40,0x00,Disabled CONFIG2L~3~1=0x80,0x80,Enabled CONFIG2L~3~2=0x80,0x00,Disabled CONFIG2H_unused=0x00 CONFIG2H~1=WDTPS,0x0f,Watchdog Timer Postscale CONFIG2H~1~1=0x000f,0x000f,1:32,768 CONFIG2H~1~2=0x000f,0x000e,1:16,384 CONFIG2H~1~3=0x000f,0x000d,1:8,192 CONFIG2H~1~4=0x000f,0x000c,1:4,096 CONFIG2H~1~5=0x000f,0x000b,1:2,048 CONFIG2H~1~6=0x000f,0x000a,1:1,024 CONFIG2H~1~7=0x000f,0x0009,1:512 CONFIG2H~1~8=0x000f,0x0008,1:256 CONFIG2H~1~9=0x000f,0x0007,1:128 CONFIG2H~1~10=0x000f,0x0006,1:64 CONFIG2H~1~11=0x000f,0x0005,1:32 CONFIG2H~1~12=0x000f,0x0004,1:16 CONFIG2H~1~13=0x000f,0x0003,1:8 CONFIG2H~1~14=0x000f,0x0002,1:4 CONFIG2H~1~15=0x000f,0x0001,1:2 CONFIG2H~1~16=0x000f,0x0000,1:1 CONFIG3L_unused=0x00 CONFIG3H_unused=0x00 CONFIG3H~1=CCP2MX,0x01,CCP2 Mux CONFIG3H~2=ECCPXM,0x02,ECCP Mux CONFIG3H~1~1=0x01,0x01,ECCP2 I/O Muxed With RC1 CONFIG3H~1~2=0x01,0x00,ECCP2 IP Muxed With RE7 CONFIG3H~2~1=0x02,0x02,P1B/P1C On RE6/RE5, P3B/P3C On RE4/RE3 CONFIG3H~2~2=0x02,0x00,P1B/P1C On RH7/RH6, P3B/P3C Onto RH5/RH4 CONFIG4L_unused=0x00 CONFIG4H_unused=0x00 erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F65J11] pgmmem=0x0 ~pgmmem=0x1fff7 cfgmem=0x1fff8 ~cfgmem=0x1ffff userid= ~userid= eedata=0x00 ~eedata=0xf5f devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x3960 configslots=8 0x1fff8=CONFIG1L 0x1fff9=CONFIG1H 0x1fffa=CONFIG2L 0x1fffb=CONFIG2H 0x1fffc=CONFIG3L 0x1fffd=CONFIG3H 0x1fffe=CONFIG4L 0x1ffff=CONFIG4H CONFIG1L_unused=0x00 CONFIG1L~1=WDTEN,0x01,Watchdog Timer Enable CONFIG1L~2=STVREN,0x0E,PLL Configuration CONFIG1L~3=ENHCPU,0x20,Stack Overflow Reset CONFIG1L~4=EXTCPU,0x40,Extended CPU CONFIG1L~5=BACKBUG,0x80,Background Debug CONFIG1L~1~1=0x01,0x01,Enabled CONFIG1L~1~2=0x01,0x00,Disabled CONFIG1L~2~1=0x0E,0x0E,No Divide (4MHz input) CONFIG1L~2~2=0x0E,0x0C,Divide by 2 (8MHz input) CONFIG1L~2~3=0x0E,0x0A,Divide by 3 (12MHz input) CONFIG1L~2~4=0x0E,0x08,Divide by 4 (16MHz input) CONFIG1L~2~5=0x0E,0x06,Divide by 5 (20MHz input) CONFIG1L~2~6=0x0E,0x04,Divide by 6 (24MHz input) CONFIG1L~2~7=0x0E,0x02,Divide by 10 (40MHz input) CONFIG1L~2~8=0x0E,0x00,Divide by 12 (48MHz input) CONFIG1L~3~1=0x20,0x20,Enabled CONFIG1L~3~2=0x20,0x00,Disabled CONFIG1L~4~1=0x40,0x40,Enabled CONFIG1L~4~2=0x40,0x00,Disabled CONFIG1L~5~1=0x80,0x80,Disabled CONFIG1L~5~2=0x80,0x00,Enabled CONFIG1H_unused=0x00 CONFIG1H~1=CPDIV,0x3,CPU Clock Divider CONFIG1H~2=CP_0,0x4,Code Protection CONFIG1H~1~1=0x3,0x3,No divide CONFIG1H~1~2=0x3,0x2,Divide by 2 CONFIG1H~1~3=0x3,0x1,Divide by 3 CONFIG1H~1~4=0x3,0x0,Divide by 6 CONFIG1H~2~1=0x4,0x4,Disabled CONFIG1H~2~2=0x4,0x00,Enabled CONFIG2L_unused=0x00 CONFIG2L~1=FOSC,0x07,Oscillator CONFIG2L~2=FCMEN,0x40,Fail Safe Monitor Clock Enable CONFIG2L~3=IESO,0x80,Internal External Switch Over Enable CONFIG2L~1~1=0x07,0x07,EC+PLL(CLKO-RA6) USB-EC+PLL CONFIG2L~1~2=0x07,0x06,EC(CLKO-RA6) USB-EC CONFIG2L~1~3=0x07,0x05,HS+PLL USB-HS+PLL CONFIG2L~1~4=0x07,0x04,HS USB-HS CONFIG2L~1~5=0x07,0x03,INTOSC EC+PLL Osc with CLKOUT CONFIG2L~1~6=0x07,0x02,INTOSC EC Osc with CLKOUT CONFIG2L~1~7=0x07,0x01,INTOSC HS+PLL Osc CONFIG2L~1~8=0x07,0x00,INTOSC HS Osc CONFIG2L~2~1=0x40,0x40,Enabled CONFIG2L~2~2=0x40,0x00,Disabled CONFIG2L~3~1=0x80,0x80,Enabled CONFIG2L~3~2=0x80,0x00,Disabled CONFIG2H_unused=0x00 CONFIG2H~1=WDTPS,0x0f,Watchdog Timer Postscale CONFIG2H~1~1=0x000f,0x000f,1:32,768 CONFIG2H~1~2=0x000f,0x000e,1:16,384 CONFIG2H~1~3=0x000f,0x000d,1:8,192 CONFIG2H~1~4=0x000f,0x000c,1:4,096 CONFIG2H~1~5=0x000f,0x000b,1:2,048 CONFIG2H~1~6=0x000f,0x000a,1:1,024 CONFIG2H~1~7=0x000f,0x0009,1:512 CONFIG2H~1~8=0x000f,0x0008,1:256 CONFIG2H~1~9=0x000f,0x0007,1:128 CONFIG2H~1~10=0x000f,0x0006,1:64 CONFIG2H~1~11=0x000f,0x0005,1:32 CONFIG2H~1~12=0x000f,0x0004,1:16 CONFIG2H~1~13=0x000f,0x0003,1:8 CONFIG2H~1~14=0x000f,0x0002,1:4 CONFIG2H~1~15=0x000f,0x0001,1:2 CONFIG2H~1~16=0x000f,0x0000,1:1 CONFIG3L_unused=0x00 CONFIG3H_unused=0x00 CONFIG3H~1=CCP2MX,0x01,CCP2 Mux CONFIG3H~2=ECCPXM,0x02,ECCP Mux CONFIG3H~1~1=0x01,0x01,ECCP2 I/O Muxed With RC1 CONFIG3H~1~2=0x01,0x00,ECCP2 IP Muxed With RE7 CONFIG3H~2~1=0x02,0x02,P1B/P1C On RE6/RE5, P3B/P3C On RE4/RE3 CONFIG3H~2~2=0x02,0x00,P1B/P1C On RH7/RH6, P3B/P3C Onto RH5/RH4 CONFIG4L_unused=0x00 CONFIG4H_unused=0x00 erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F65J15] pgmmem=0x0 ~pgmmem=0x1fff7 cfgmem=0x1fff8 ~cfgmem=0x1ffff userid= ~userid= eedata=0x00 ~eedata=0xf5f devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x1540 configslots=8 0x1fff8=CONFIG1L 0x1fff9=CONFIG1H 0x1fffa=CONFIG2L 0x1fffb=CONFIG2H 0x1fffc=CONFIG3L 0x1fffd=CONFIG3H 0x1fffe=CONFIG4L 0x1ffff=CONFIG4H CONFIG1L_unused=0x00 CONFIG1L~1=WDTEN,0x01,Watchdog Timer Enable CONFIG1L~2=STVREN,0x0E,PLL Configuration CONFIG1L~3=ENHCPU,0x20,Stack Overflow Reset CONFIG1L~4=EXTCPU,0x40,Extended CPU CONFIG1L~5=BACKBUG,0x80,Background Debug CONFIG1L~1~1=0x01,0x01,Enabled CONFIG1L~1~2=0x01,0x00,Disabled CONFIG1L~2~1=0x0E,0x0E,No Divide (4MHz input) CONFIG1L~2~2=0x0E,0x0C,Divide by 2 (8MHz input) CONFIG1L~2~3=0x0E,0x0A,Divide by 3 (12MHz input) CONFIG1L~2~4=0x0E,0x08,Divide by 4 (16MHz input) CONFIG1L~2~5=0x0E,0x06,Divide by 5 (20MHz input) CONFIG1L~2~6=0x0E,0x04,Divide by 6 (24MHz input) CONFIG1L~2~7=0x0E,0x02,Divide by 10 (40MHz input) CONFIG1L~2~8=0x0E,0x00,Divide by 12 (48MHz input) CONFIG1L~3~1=0x20,0x20,Enabled CONFIG1L~3~2=0x20,0x00,Disabled CONFIG1L~4~1=0x40,0x40,Enabled CONFIG1L~4~2=0x40,0x00,Disabled CONFIG1L~5~1=0x80,0x80,Disabled CONFIG1L~5~2=0x80,0x00,Enabled CONFIG1H_unused=0x00 CONFIG1H~1=CPDIV,0x3,CPU Clock Divider CONFIG1H~2=CP_0,0x4,Code Protection CONFIG1H~1~1=0x3,0x3,No divide CONFIG1H~1~2=0x3,0x2,Divide by 2 CONFIG1H~1~3=0x3,0x1,Divide by 3 CONFIG1H~1~4=0x3,0x0,Divide by 6 CONFIG1H~2~1=0x4,0x4,Disabled CONFIG1H~2~2=0x4,0x00,Enabled CONFIG2L_unused=0x00 CONFIG2L~1=FOSC,0x07,Oscillator CONFIG2L~2=FCMEN,0x40,Fail Safe Monitor Clock Enable CONFIG2L~3=IESO,0x80,Internal External Switch Over Enable CONFIG2L~1~1=0x07,0x07,EC+PLL(CLKO-RA6) USB-EC+PLL CONFIG2L~1~2=0x07,0x06,EC(CLKO-RA6) USB-EC CONFIG2L~1~3=0x07,0x05,HS+PLL USB-HS+PLL CONFIG2L~1~4=0x07,0x04,HS USB-HS CONFIG2L~1~5=0x07,0x03,INTOSC EC+PLL Osc with CLKOUT CONFIG2L~1~6=0x07,0x02,INTOSC EC Osc with CLKOUT CONFIG2L~1~7=0x07,0x01,INTOSC HS+PLL Osc CONFIG2L~1~8=0x07,0x00,INTOSC HS Osc CONFIG2L~2~1=0x40,0x40,Enabled CONFIG2L~2~2=0x40,0x00,Disabled CONFIG2L~3~1=0x80,0x80,Enabled CONFIG2L~3~2=0x80,0x00,Disabled CONFIG2H_unused=0x00 CONFIG2H~1=WDTPS,0x0f,Watchdog Timer Postscale CONFIG2H~1~1=0x000f,0x000f,1:32,768 CONFIG2H~1~2=0x000f,0x000e,1:16,384 CONFIG2H~1~3=0x000f,0x000d,1:8,192 CONFIG2H~1~4=0x000f,0x000c,1:4,096 CONFIG2H~1~5=0x000f,0x000b,1:2,048 CONFIG2H~1~6=0x000f,0x000a,1:1,024 CONFIG2H~1~7=0x000f,0x0009,1:512 CONFIG2H~1~8=0x000f,0x0008,1:256 CONFIG2H~1~9=0x000f,0x0007,1:128 CONFIG2H~1~10=0x000f,0x0006,1:64 CONFIG2H~1~11=0x000f,0x0005,1:32 CONFIG2H~1~12=0x000f,0x0004,1:16 CONFIG2H~1~13=0x000f,0x0003,1:8 CONFIG2H~1~14=0x000f,0x0002,1:4 CONFIG2H~1~15=0x000f,0x0001,1:2 CONFIG2H~1~16=0x000f,0x0000,1:1 CONFIG3L_unused=0x00 CONFIG3H_unused=0x00 CONFIG3H~1=CCP2MX,0x01,CCP2 Mux CONFIG3H~2=ECCPXM,0x02,ECCP Mux CONFIG3H~1~1=0x01,0x01,ECCP2 I/O Muxed With RC1 CONFIG3H~1~2=0x01,0x00,ECCP2 IP Muxed With RE7 CONFIG3H~2~1=0x02,0x02,P1B/P1C On RE6/RE5, P3B/P3C On RE4/RE3 CONFIG3H~2~2=0x02,0x00,P1B/P1C On RH7/RH6, P3B/P3C Onto RH5/RH4 CONFIG4L_unused=0x00 CONFIG4H_unused=0x00 erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F65J50] pgmmem=0x0 ~pgmmem=0x1fff7 cfgmem=0x1fff8 ~cfgmem=0x1ffff userid= ~userid= eedata=0x00 ~eedata=0xf5f devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x4100 configslots=8 0x1fff8=CONFIG1L 0x1fff9=CONFIG1H 0x1fffa=CONFIG2L 0x1fffb=CONFIG2H 0x1fffc=CONFIG3L 0x1fffd=CONFIG3H 0x1fffe=CONFIG4L 0x1ffff=CONFIG4H CONFIG1L_unused=0x00 CONFIG1L~1=WDTEN,0x01,Watchdog Timer Enable CONFIG1L~2=STVREN,0x0E,PLL Configuration CONFIG1L~3=ENHCPU,0x20,Stack Overflow Reset CONFIG1L~4=EXTCPU,0x40,Extended CPU CONFIG1L~5=BACKBUG,0x80,Background Debug CONFIG1L~1~1=0x01,0x01,Enabled CONFIG1L~1~2=0x01,0x00,Disabled CONFIG1L~2~1=0x0E,0x0E,No Divide (4MHz input) CONFIG1L~2~2=0x0E,0x0C,Divide by 2 (8MHz input) CONFIG1L~2~3=0x0E,0x0A,Divide by 3 (12MHz input) CONFIG1L~2~4=0x0E,0x08,Divide by 4 (16MHz input) CONFIG1L~2~5=0x0E,0x06,Divide by 5 (20MHz input) CONFIG1L~2~6=0x0E,0x04,Divide by 6 (24MHz input) CONFIG1L~2~7=0x0E,0x02,Divide by 10 (40MHz input) CONFIG1L~2~8=0x0E,0x00,Divide by 12 (48MHz input) CONFIG1L~3~1=0x20,0x20,Enabled CONFIG1L~3~2=0x20,0x00,Disabled CONFIG1L~4~1=0x40,0x40,Enabled CONFIG1L~4~2=0x40,0x00,Disabled CONFIG1L~5~1=0x80,0x80,Disabled CONFIG1L~5~2=0x80,0x00,Enabled CONFIG1H_unused=0x00 CONFIG1H~1=CPDIV,0x3,CPU Clock Divider CONFIG1H~2=CP_0,0x4,Code Protection CONFIG1H~1~1=0x3,0x3,No divide CONFIG1H~1~2=0x3,0x2,Divide by 2 CONFIG1H~1~3=0x3,0x1,Divide by 3 CONFIG1H~1~4=0x3,0x0,Divide by 6 CONFIG1H~2~1=0x4,0x4,Disabled CONFIG1H~2~2=0x4,0x00,Enabled CONFIG2L_unused=0x00 CONFIG2L~1=FOSC,0x07,Oscillator CONFIG2L~2=FCMEN,0x40,Fail Safe Monitor Clock Enable CONFIG2L~3=IESO,0x80,Internal External Switch Over Enable CONFIG2L~1~1=0x07,0x07,EC+PLL(CLKO-RA6) USB-EC+PLL CONFIG2L~1~2=0x07,0x06,EC(CLKO-RA6) USB-EC CONFIG2L~1~3=0x07,0x05,HS+PLL USB-HS+PLL CONFIG2L~1~4=0x07,0x04,HS USB-HS CONFIG2L~1~5=0x07,0x03,INTOSC EC+PLL Osc with CLKOUT CONFIG2L~1~6=0x07,0x02,INTOSC EC Osc with CLKOUT CONFIG2L~1~7=0x07,0x01,INTOSC HS+PLL Osc CONFIG2L~1~8=0x07,0x00,INTOSC HS Osc CONFIG2L~2~1=0x40,0x40,Enabled CONFIG2L~2~2=0x40,0x00,Disabled CONFIG2L~3~1=0x80,0x80,Enabled CONFIG2L~3~2=0x80,0x00,Disabled CONFIG2H_unused=0x00 CONFIG2H~1=WDTPS,0x0f,Watchdog Timer Postscale CONFIG2H~1~1=0x000f,0x000f,1:32,768 CONFIG2H~1~2=0x000f,0x000e,1:16,384 CONFIG2H~1~3=0x000f,0x000d,1:8,192 CONFIG2H~1~4=0x000f,0x000c,1:4,096 CONFIG2H~1~5=0x000f,0x000b,1:2,048 CONFIG2H~1~6=0x000f,0x000a,1:1,024 CONFIG2H~1~7=0x000f,0x0009,1:512 CONFIG2H~1~8=0x000f,0x0008,1:256 CONFIG2H~1~9=0x000f,0x0007,1:128 CONFIG2H~1~10=0x000f,0x0006,1:64 CONFIG2H~1~11=0x000f,0x0005,1:32 CONFIG2H~1~12=0x000f,0x0004,1:16 CONFIG2H~1~13=0x000f,0x0003,1:8 CONFIG2H~1~14=0x000f,0x0002,1:4 CONFIG2H~1~15=0x000f,0x0001,1:2 CONFIG2H~1~16=0x000f,0x0000,1:1 CONFIG3L_unused=0x00 CONFIG3H_unused=0x00 CONFIG3H~1=CCP2MX,0x01,CCP2 Mux CONFIG3H~2=ECCPXM,0x02,ECCP Mux CONFIG3H~1~1=0x01,0x01,ECCP2 I/O Muxed With RC1 CONFIG3H~1~2=0x01,0x00,ECCP2 IP Muxed With RE7 CONFIG3H~2~1=0x02,0x02,P1B/P1C On RE6/RE5, P3B/P3C On RE4/RE3 CONFIG3H~2~2=0x02,0x00,P1B/P1C On RH7/RH6, P3B/P3C Onto RH5/RH4 CONFIG4L_unused=0x00 CONFIG4H_unused=0x00 erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F65J90] pgmmem=0x0 ~pgmmem=0x1fff7 cfgmem=0x1fff8 ~cfgmem=0x1ffff userid= ~userid= eedata=0x00 ~eedata=0xf5f devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x3860 configslots=8 0x1fff8=CONFIG1L 0x1fff9=CONFIG1H 0x1fffa=CONFIG2L 0x1fffb=CONFIG2H 0x1fffc=CONFIG3L 0x1fffd=CONFIG3H 0x1fffe=CONFIG4L 0x1ffff=CONFIG4H CONFIG1L_unused=0x00 CONFIG1L~1=WDTEN,0x01,Watchdog Timer Enable CONFIG1L~2=STVREN,0x0E,PLL Configuration CONFIG1L~3=ENHCPU,0x20,Stack Overflow Reset CONFIG1L~4=EXTCPU,0x40,Extended CPU CONFIG1L~5=BACKBUG,0x80,Background Debug CONFIG1L~1~1=0x01,0x01,Enabled CONFIG1L~1~2=0x01,0x00,Disabled CONFIG1L~2~1=0x0E,0x0E,No Divide (4MHz input) CONFIG1L~2~2=0x0E,0x0C,Divide by 2 (8MHz input) CONFIG1L~2~3=0x0E,0x0A,Divide by 3 (12MHz input) CONFIG1L~2~4=0x0E,0x08,Divide by 4 (16MHz input) CONFIG1L~2~5=0x0E,0x06,Divide by 5 (20MHz input) CONFIG1L~2~6=0x0E,0x04,Divide by 6 (24MHz input) CONFIG1L~2~7=0x0E,0x02,Divide by 10 (40MHz input) CONFIG1L~2~8=0x0E,0x00,Divide by 12 (48MHz input) CONFIG1L~3~1=0x20,0x20,Enabled CONFIG1L~3~2=0x20,0x00,Disabled CONFIG1L~4~1=0x40,0x40,Enabled CONFIG1L~4~2=0x40,0x00,Disabled CONFIG1L~5~1=0x80,0x80,Disabled CONFIG1L~5~2=0x80,0x00,Enabled CONFIG1H_unused=0x00 CONFIG1H~1=CPDIV,0x3,CPU Clock Divider CONFIG1H~2=CP_0,0x4,Code Protection CONFIG1H~1~1=0x3,0x3,No divide CONFIG1H~1~2=0x3,0x2,Divide by 2 CONFIG1H~1~3=0x3,0x1,Divide by 3 CONFIG1H~1~4=0x3,0x0,Divide by 6 CONFIG1H~2~1=0x4,0x4,Disabled CONFIG1H~2~2=0x4,0x00,Enabled CONFIG2L_unused=0x00 CONFIG2L~1=FOSC,0x07,Oscillator CONFIG2L~2=FCMEN,0x40,Fail Safe Monitor Clock Enable CONFIG2L~3=IESO,0x80,Internal External Switch Over Enable CONFIG2L~1~1=0x07,0x07,EC+PLL(CLKO-RA6) USB-EC+PLL CONFIG2L~1~2=0x07,0x06,EC(CLKO-RA6) USB-EC CONFIG2L~1~3=0x07,0x05,HS+PLL USB-HS+PLL CONFIG2L~1~4=0x07,0x04,HS USB-HS CONFIG2L~1~5=0x07,0x03,INTOSC EC+PLL Osc with CLKOUT CONFIG2L~1~6=0x07,0x02,INTOSC EC Osc with CLKOUT CONFIG2L~1~7=0x07,0x01,INTOSC HS+PLL Osc CONFIG2L~1~8=0x07,0x00,INTOSC HS Osc CONFIG2L~2~1=0x40,0x40,Enabled CONFIG2L~2~2=0x40,0x00,Disabled CONFIG2L~3~1=0x80,0x80,Enabled CONFIG2L~3~2=0x80,0x00,Disabled CONFIG2H_unused=0x00 CONFIG2H~1=WDTPS,0x0f,Watchdog Timer Postscale CONFIG2H~1~1=0x000f,0x000f,1:32,768 CONFIG2H~1~2=0x000f,0x000e,1:16,384 CONFIG2H~1~3=0x000f,0x000d,1:8,192 CONFIG2H~1~4=0x000f,0x000c,1:4,096 CONFIG2H~1~5=0x000f,0x000b,1:2,048 CONFIG2H~1~6=0x000f,0x000a,1:1,024 CONFIG2H~1~7=0x000f,0x0009,1:512 CONFIG2H~1~8=0x000f,0x0008,1:256 CONFIG2H~1~9=0x000f,0x0007,1:128 CONFIG2H~1~10=0x000f,0x0006,1:64 CONFIG2H~1~11=0x000f,0x0005,1:32 CONFIG2H~1~12=0x000f,0x0004,1:16 CONFIG2H~1~13=0x000f,0x0003,1:8 CONFIG2H~1~14=0x000f,0x0002,1:4 CONFIG2H~1~15=0x000f,0x0001,1:2 CONFIG2H~1~16=0x000f,0x0000,1:1 CONFIG3L_unused=0x00 CONFIG3H_unused=0x00 CONFIG3H~1=CCP2MX,0x01,CCP2 Mux CONFIG3H~2=ECCPXM,0x02,ECCP Mux CONFIG3H~1~1=0x01,0x01,ECCP2 I/O Muxed With RC1 CONFIG3H~1~2=0x01,0x00,ECCP2 IP Muxed With RE7 CONFIG3H~2~1=0x02,0x02,P1B/P1C On RE6/RE5, P3B/P3C On RE4/RE3 CONFIG3H~2~2=0x02,0x00,P1B/P1C On RH7/RH6, P3B/P3C Onto RH5/RH4 CONFIG4L_unused=0x00 CONFIG4H_unused=0x00 erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F66J10] pgmmem=0x0 ~pgmmem=0x1fff7 cfgmem=0x1fff8 ~cfgmem=0x1ffff userid= ~userid= eedata=0x00 ~eedata=0xf5f devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x1560 configslots=8 0x1fff8=CONFIG1L 0x1fff9=CONFIG1H 0x1fffa=CONFIG2L 0x1fffb=CONFIG2H 0x1fffc=CONFIG3L 0x1fffd=CONFIG3H 0x1fffe=CONFIG4L 0x1ffff=CONFIG4H CONFIG1L_unused=0x00 CONFIG1L~1=WDTEN,0x01,Watchdog Timer Enable CONFIG1L~2=STVREN,0x0E,PLL Configuration CONFIG1L~3=ENHCPU,0x20,Stack Overflow Reset CONFIG1L~4=EXTCPU,0x40,Extended CPU CONFIG1L~5=BACKBUG,0x80,Background Debug CONFIG1L~1~1=0x01,0x01,Enabled CONFIG1L~1~2=0x01,0x00,Disabled CONFIG1L~2~1=0x0E,0x0E,No Divide (4MHz input) CONFIG1L~2~2=0x0E,0x0C,Divide by 2 (8MHz input) CONFIG1L~2~3=0x0E,0x0A,Divide by 3 (12MHz input) CONFIG1L~2~4=0x0E,0x08,Divide by 4 (16MHz input) CONFIG1L~2~5=0x0E,0x06,Divide by 5 (20MHz input) CONFIG1L~2~6=0x0E,0x04,Divide by 6 (24MHz input) CONFIG1L~2~7=0x0E,0x02,Divide by 10 (40MHz input) CONFIG1L~2~8=0x0E,0x00,Divide by 12 (48MHz input) CONFIG1L~3~1=0x20,0x20,Enabled CONFIG1L~3~2=0x20,0x00,Disabled CONFIG1L~4~1=0x40,0x40,Enabled CONFIG1L~4~2=0x40,0x00,Disabled CONFIG1L~5~1=0x80,0x80,Disabled CONFIG1L~5~2=0x80,0x00,Enabled CONFIG1H_unused=0x00 CONFIG1H~1=CPDIV,0x3,CPU Clock Divider CONFIG1H~2=CP_0,0x4,Code Protection CONFIG1H~1~1=0x3,0x3,No divide CONFIG1H~1~2=0x3,0x2,Divide by 2 CONFIG1H~1~3=0x3,0x1,Divide by 3 CONFIG1H~1~4=0x3,0x0,Divide by 6 CONFIG1H~2~1=0x4,0x4,Disabled CONFIG1H~2~2=0x4,0x00,Enabled CONFIG2L_unused=0x00 CONFIG2L~1=FOSC,0x07,Oscillator CONFIG2L~2=FCMEN,0x40,Fail Safe Monitor Clock Enable CONFIG2L~3=IESO,0x80,Internal External Switch Over Enable CONFIG2L~1~1=0x07,0x07,EC+PLL(CLKO-RA6) USB-EC+PLL CONFIG2L~1~2=0x07,0x06,EC(CLKO-RA6) USB-EC CONFIG2L~1~3=0x07,0x05,HS+PLL USB-HS+PLL CONFIG2L~1~4=0x07,0x04,HS USB-HS CONFIG2L~1~5=0x07,0x03,INTOSC EC+PLL Osc with CLKOUT CONFIG2L~1~6=0x07,0x02,INTOSC EC Osc with CLKOUT CONFIG2L~1~7=0x07,0x01,INTOSC HS+PLL Osc CONFIG2L~1~8=0x07,0x00,INTOSC HS Osc CONFIG2L~2~1=0x40,0x40,Enabled CONFIG2L~2~2=0x40,0x00,Disabled CONFIG2L~3~1=0x80,0x80,Enabled CONFIG2L~3~2=0x80,0x00,Disabled CONFIG2H_unused=0x00 CONFIG2H~1=WDTPS,0x0f,Watchdog Timer Postscale CONFIG2H~1~1=0x000f,0x000f,1:32,768 CONFIG2H~1~2=0x000f,0x000e,1:16,384 CONFIG2H~1~3=0x000f,0x000d,1:8,192 CONFIG2H~1~4=0x000f,0x000c,1:4,096 CONFIG2H~1~5=0x000f,0x000b,1:2,048 CONFIG2H~1~6=0x000f,0x000a,1:1,024 CONFIG2H~1~7=0x000f,0x0009,1:512 CONFIG2H~1~8=0x000f,0x0008,1:256 CONFIG2H~1~9=0x000f,0x0007,1:128 CONFIG2H~1~10=0x000f,0x0006,1:64 CONFIG2H~1~11=0x000f,0x0005,1:32 CONFIG2H~1~12=0x000f,0x0004,1:16 CONFIG2H~1~13=0x000f,0x0003,1:8 CONFIG2H~1~14=0x000f,0x0002,1:4 CONFIG2H~1~15=0x000f,0x0001,1:2 CONFIG2H~1~16=0x000f,0x0000,1:1 CONFIG3L_unused=0x00 CONFIG3H_unused=0x00 CONFIG3H~1=CCP2MX,0x01,CCP2 Mux CONFIG3H~2=ECCPXM,0x02,ECCP Mux CONFIG3H~1~1=0x01,0x01,ECCP2 I/O Muxed With RC1 CONFIG3H~1~2=0x01,0x00,ECCP2 IP Muxed With RE7 CONFIG3H~2~1=0x02,0x02,P1B/P1C On RE6/RE5, P3B/P3C On RE4/RE3 CONFIG3H~2~2=0x02,0x00,P1B/P1C On RH7/RH6, P3B/P3C Onto RH5/RH4 CONFIG4L_unused=0x00 CONFIG4H_unused=0x00 erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F66J11] pgmmem=0x0 ~pgmmem=0x1fff7 cfgmem=0x1fff8 ~cfgmem=0x1ffff userid= ~userid= eedata=0x00 ~eedata=0xf5f devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x4440 configslots=8 0x1fff8=CONFIG1L 0x1fff9=CONFIG1H 0x1fffa=CONFIG2L 0x1fffb=CONFIG2H 0x1fffc=CONFIG3L 0x1fffd=CONFIG3H 0x1fffe=CONFIG4L 0x1ffff=CONFIG4H CONFIG1L_unused=0x00 CONFIG1L~1=WDTEN,0x01,Watchdog Timer Enable CONFIG1L~2=STVREN,0x0E,PLL Configuration CONFIG1L~3=ENHCPU,0x20,Stack Overflow Reset CONFIG1L~4=EXTCPU,0x40,Extended CPU CONFIG1L~5=BACKBUG,0x80,Background Debug CONFIG1L~1~1=0x01,0x01,Enabled CONFIG1L~1~2=0x01,0x00,Disabled CONFIG1L~2~1=0x0E,0x0E,No Divide (4MHz input) CONFIG1L~2~2=0x0E,0x0C,Divide by 2 (8MHz input) CONFIG1L~2~3=0x0E,0x0A,Divide by 3 (12MHz input) CONFIG1L~2~4=0x0E,0x08,Divide by 4 (16MHz input) CONFIG1L~2~5=0x0E,0x06,Divide by 5 (20MHz input) CONFIG1L~2~6=0x0E,0x04,Divide by 6 (24MHz input) CONFIG1L~2~7=0x0E,0x02,Divide by 10 (40MHz input) CONFIG1L~2~8=0x0E,0x00,Divide by 12 (48MHz input) CONFIG1L~3~1=0x20,0x20,Enabled CONFIG1L~3~2=0x20,0x00,Disabled CONFIG1L~4~1=0x40,0x40,Enabled CONFIG1L~4~2=0x40,0x00,Disabled CONFIG1L~5~1=0x80,0x80,Disabled CONFIG1L~5~2=0x80,0x00,Enabled CONFIG1H_unused=0x00 CONFIG1H~1=CPDIV,0x3,CPU Clock Divider CONFIG1H~2=CP_0,0x4,Code Protection CONFIG1H~1~1=0x3,0x3,No divide CONFIG1H~1~2=0x3,0x2,Divide by 2 CONFIG1H~1~3=0x3,0x1,Divide by 3 CONFIG1H~1~4=0x3,0x0,Divide by 6 CONFIG1H~2~1=0x4,0x4,Disabled CONFIG1H~2~2=0x4,0x00,Enabled CONFIG2L_unused=0x00 CONFIG2L~1=FOSC,0x07,Oscillator CONFIG2L~2=FCMEN,0x40,Fail Safe Monitor Clock Enable CONFIG2L~3=IESO,0x80,Internal External Switch Over Enable CONFIG2L~1~1=0x07,0x07,EC+PLL(CLKO-RA6) USB-EC+PLL CONFIG2L~1~2=0x07,0x06,EC(CLKO-RA6) USB-EC CONFIG2L~1~3=0x07,0x05,HS+PLL USB-HS+PLL CONFIG2L~1~4=0x07,0x04,HS USB-HS CONFIG2L~1~5=0x07,0x03,INTOSC EC+PLL Osc with CLKOUT CONFIG2L~1~6=0x07,0x02,INTOSC EC Osc with CLKOUT CONFIG2L~1~7=0x07,0x01,INTOSC HS+PLL Osc CONFIG2L~1~8=0x07,0x00,INTOSC HS Osc CONFIG2L~2~1=0x40,0x40,Enabled CONFIG2L~2~2=0x40,0x00,Disabled CONFIG2L~3~1=0x80,0x80,Enabled CONFIG2L~3~2=0x80,0x00,Disabled CONFIG2H_unused=0x00 CONFIG2H~1=WDTPS,0x0f,Watchdog Timer Postscale CONFIG2H~1~1=0x000f,0x000f,1:32,768 CONFIG2H~1~2=0x000f,0x000e,1:16,384 CONFIG2H~1~3=0x000f,0x000d,1:8,192 CONFIG2H~1~4=0x000f,0x000c,1:4,096 CONFIG2H~1~5=0x000f,0x000b,1:2,048 CONFIG2H~1~6=0x000f,0x000a,1:1,024 CONFIG2H~1~7=0x000f,0x0009,1:512 CONFIG2H~1~8=0x000f,0x0008,1:256 CONFIG2H~1~9=0x000f,0x0007,1:128 CONFIG2H~1~10=0x000f,0x0006,1:64 CONFIG2H~1~11=0x000f,0x0005,1:32 CONFIG2H~1~12=0x000f,0x0004,1:16 CONFIG2H~1~13=0x000f,0x0003,1:8 CONFIG2H~1~14=0x000f,0x0002,1:4 CONFIG2H~1~15=0x000f,0x0001,1:2 CONFIG2H~1~16=0x000f,0x0000,1:1 CONFIG3L_unused=0x00 CONFIG3H_unused=0x00 CONFIG3H~1=CCP2MX,0x01,CCP2 Mux CONFIG3H~2=ECCPXM,0x02,ECCP Mux CONFIG3H~1~1=0x01,0x01,ECCP2 I/O Muxed With RC1 CONFIG3H~1~2=0x01,0x00,ECCP2 IP Muxed With RE7 CONFIG3H~2~1=0x02,0x02,P1B/P1C On RE6/RE5, P3B/P3C On RE4/RE3 CONFIG3H~2~2=0x02,0x00,P1B/P1C On RH7/RH6, P3B/P3C Onto RH5/RH4 CONFIG4L_unused=0x00 CONFIG4H_unused=0x00 erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F66J15] pgmmem=0x0 ~pgmmem=0x1fff7 cfgmem=0x1fff8 ~cfgmem=0x1ffff userid= ~userid= eedata=0x00 ~eedata=0xf5f devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x1580 configslots=8 0x1fff8=CONFIG1L 0x1fff9=CONFIG1H 0x1fffa=CONFIG2L 0x1fffb=CONFIG2H 0x1fffc=CONFIG3L 0x1fffd=CONFIG3H 0x1fffe=CONFIG4L 0x1ffff=CONFIG4H CONFIG1L_unused=0x00 CONFIG1L~1=WDTEN,0x01,Watchdog Timer Enable CONFIG1L~2=STVREN,0x0E,PLL Configuration CONFIG1L~3=ENHCPU,0x20,Stack Overflow Reset CONFIG1L~4=EXTCPU,0x40,Extended CPU CONFIG1L~5=BACKBUG,0x80,Background Debug CONFIG1L~1~1=0x01,0x01,Enabled CONFIG1L~1~2=0x01,0x00,Disabled CONFIG1L~2~1=0x0E,0x0E,No Divide (4MHz input) CONFIG1L~2~2=0x0E,0x0C,Divide by 2 (8MHz input) CONFIG1L~2~3=0x0E,0x0A,Divide by 3 (12MHz input) CONFIG1L~2~4=0x0E,0x08,Divide by 4 (16MHz input) CONFIG1L~2~5=0x0E,0x06,Divide by 5 (20MHz input) CONFIG1L~2~6=0x0E,0x04,Divide by 6 (24MHz input) CONFIG1L~2~7=0x0E,0x02,Divide by 10 (40MHz input) CONFIG1L~2~8=0x0E,0x00,Divide by 12 (48MHz input) CONFIG1L~3~1=0x20,0x20,Enabled CONFIG1L~3~2=0x20,0x00,Disabled CONFIG1L~4~1=0x40,0x40,Enabled CONFIG1L~4~2=0x40,0x00,Disabled CONFIG1L~5~1=0x80,0x80,Disabled CONFIG1L~5~2=0x80,0x00,Enabled CONFIG1H_unused=0x00 CONFIG1H~1=CPDIV,0x3,CPU Clock Divider CONFIG1H~2=CP_0,0x4,Code Protection CONFIG1H~1~1=0x3,0x3,No divide CONFIG1H~1~2=0x3,0x2,Divide by 2 CONFIG1H~1~3=0x3,0x1,Divide by 3 CONFIG1H~1~4=0x3,0x0,Divide by 6 CONFIG1H~2~1=0x4,0x4,Disabled CONFIG1H~2~2=0x4,0x00,Enabled CONFIG2L_unused=0x00 CONFIG2L~1=FOSC,0x07,Oscillator CONFIG2L~2=FCMEN,0x40,Fail Safe Monitor Clock Enable CONFIG2L~3=IESO,0x80,Internal External Switch Over Enable CONFIG2L~1~1=0x07,0x07,EC+PLL(CLKO-RA6) USB-EC+PLL CONFIG2L~1~2=0x07,0x06,EC(CLKO-RA6) USB-EC CONFIG2L~1~3=0x07,0x05,HS+PLL USB-HS+PLL CONFIG2L~1~4=0x07,0x04,HS USB-HS CONFIG2L~1~5=0x07,0x03,INTOSC EC+PLL Osc with CLKOUT CONFIG2L~1~6=0x07,0x02,INTOSC EC Osc with CLKOUT CONFIG2L~1~7=0x07,0x01,INTOSC HS+PLL Osc CONFIG2L~1~8=0x07,0x00,INTOSC HS Osc CONFIG2L~2~1=0x40,0x40,Enabled CONFIG2L~2~2=0x40,0x00,Disabled CONFIG2L~3~1=0x80,0x80,Enabled CONFIG2L~3~2=0x80,0x00,Disabled CONFIG2H_unused=0x00 CONFIG2H~1=WDTPS,0x0f,Watchdog Timer Postscale CONFIG2H~1~1=0x000f,0x000f,1:32,768 CONFIG2H~1~2=0x000f,0x000e,1:16,384 CONFIG2H~1~3=0x000f,0x000d,1:8,192 CONFIG2H~1~4=0x000f,0x000c,1:4,096 CONFIG2H~1~5=0x000f,0x000b,1:2,048 CONFIG2H~1~6=0x000f,0x000a,1:1,024 CONFIG2H~1~7=0x000f,0x0009,1:512 CONFIG2H~1~8=0x000f,0x0008,1:256 CONFIG2H~1~9=0x000f,0x0007,1:128 CONFIG2H~1~10=0x000f,0x0006,1:64 CONFIG2H~1~11=0x000f,0x0005,1:32 CONFIG2H~1~12=0x000f,0x0004,1:16 CONFIG2H~1~13=0x000f,0x0003,1:8 CONFIG2H~1~14=0x000f,0x0002,1:4 CONFIG2H~1~15=0x000f,0x0001,1:2 CONFIG2H~1~16=0x000f,0x0000,1:1 CONFIG3L_unused=0x00 CONFIG3H_unused=0x00 CONFIG3H~1=CCP2MX,0x01,CCP2 Mux CONFIG3H~2=ECCPXM,0x02,ECCP Mux CONFIG3H~1~1=0x01,0x01,ECCP2 I/O Muxed With RC1 CONFIG3H~1~2=0x01,0x00,ECCP2 IP Muxed With RE7 CONFIG3H~2~1=0x02,0x02,P1B/P1C On RE6/RE5, P3B/P3C On RE4/RE3 CONFIG3H~2~2=0x02,0x00,P1B/P1C On RH7/RH6, P3B/P3C Onto RH5/RH4 CONFIG4L_unused=0x00 CONFIG4H_unused=0x00 erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F66J16] pgmmem=0x0 ~pgmmem=0x1fff7 cfgmem=0x1fff8 ~cfgmem=0x1ffff userid= ~userid= eedata=0x00 ~eedata=0xf5f devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x4460 configslots=8 0x1fff8=CONFIG1L 0x1fff9=CONFIG1H 0x1fffa=CONFIG2L 0x1fffb=CONFIG2H 0x1fffc=CONFIG3L 0x1fffd=CONFIG3H 0x1fffe=CONFIG4L 0x1ffff=CONFIG4H CONFIG1L_unused=0x00 CONFIG1L~1=WDTEN,0x01,Watchdog Timer Enable CONFIG1L~2=STVREN,0x0E,PLL Configuration CONFIG1L~3=ENHCPU,0x20,Stack Overflow Reset CONFIG1L~4=EXTCPU,0x40,Extended CPU CONFIG1L~5=BACKBUG,0x80,Background Debug CONFIG1L~1~1=0x01,0x01,Enabled CONFIG1L~1~2=0x01,0x00,Disabled CONFIG1L~2~1=0x0E,0x0E,No Divide (4MHz input) CONFIG1L~2~2=0x0E,0x0C,Divide by 2 (8MHz input) CONFIG1L~2~3=0x0E,0x0A,Divide by 3 (12MHz input) CONFIG1L~2~4=0x0E,0x08,Divide by 4 (16MHz input) CONFIG1L~2~5=0x0E,0x06,Divide by 5 (20MHz input) CONFIG1L~2~6=0x0E,0x04,Divide by 6 (24MHz input) CONFIG1L~2~7=0x0E,0x02,Divide by 10 (40MHz input) CONFIG1L~2~8=0x0E,0x00,Divide by 12 (48MHz input) CONFIG1L~3~1=0x20,0x20,Enabled CONFIG1L~3~2=0x20,0x00,Disabled CONFIG1L~4~1=0x40,0x40,Enabled CONFIG1L~4~2=0x40,0x00,Disabled CONFIG1L~5~1=0x80,0x80,Disabled CONFIG1L~5~2=0x80,0x00,Enabled CONFIG1H_unused=0x00 CONFIG1H~1=CPDIV,0x3,CPU Clock Divider CONFIG1H~2=CP_0,0x4,Code Protection CONFIG1H~1~1=0x3,0x3,No divide CONFIG1H~1~2=0x3,0x2,Divide by 2 CONFIG1H~1~3=0x3,0x1,Divide by 3 CONFIG1H~1~4=0x3,0x0,Divide by 6 CONFIG1H~2~1=0x4,0x4,Disabled CONFIG1H~2~2=0x4,0x00,Enabled CONFIG2L_unused=0x00 CONFIG2L~1=FOSC,0x07,Oscillator CONFIG2L~2=FCMEN,0x40,Fail Safe Monitor Clock Enable CONFIG2L~3=IESO,0x80,Internal External Switch Over Enable CONFIG2L~1~1=0x07,0x07,EC+PLL(CLKO-RA6) USB-EC+PLL CONFIG2L~1~2=0x07,0x06,EC(CLKO-RA6) USB-EC CONFIG2L~1~3=0x07,0x05,HS+PLL USB-HS+PLL CONFIG2L~1~4=0x07,0x04,HS USB-HS CONFIG2L~1~5=0x07,0x03,INTOSC EC+PLL Osc with CLKOUT CONFIG2L~1~6=0x07,0x02,INTOSC EC Osc with CLKOUT CONFIG2L~1~7=0x07,0x01,INTOSC HS+PLL Osc CONFIG2L~1~8=0x07,0x00,INTOSC HS Osc CONFIG2L~2~1=0x40,0x40,Enabled CONFIG2L~2~2=0x40,0x00,Disabled CONFIG2L~3~1=0x80,0x80,Enabled CONFIG2L~3~2=0x80,0x00,Disabled CONFIG2H_unused=0x00 CONFIG2H~1=WDTPS,0x0f,Watchdog Timer Postscale CONFIG2H~1~1=0x000f,0x000f,1:32,768 CONFIG2H~1~2=0x000f,0x000e,1:16,384 CONFIG2H~1~3=0x000f,0x000d,1:8,192 CONFIG2H~1~4=0x000f,0x000c,1:4,096 CONFIG2H~1~5=0x000f,0x000b,1:2,048 CONFIG2H~1~6=0x000f,0x000a,1:1,024 CONFIG2H~1~7=0x000f,0x0009,1:512 CONFIG2H~1~8=0x000f,0x0008,1:256 CONFIG2H~1~9=0x000f,0x0007,1:128 CONFIG2H~1~10=0x000f,0x0006,1:64 CONFIG2H~1~11=0x000f,0x0005,1:32 CONFIG2H~1~12=0x000f,0x0004,1:16 CONFIG2H~1~13=0x000f,0x0003,1:8 CONFIG2H~1~14=0x000f,0x0002,1:4 CONFIG2H~1~15=0x000f,0x0001,1:2 CONFIG2H~1~16=0x000f,0x0000,1:1 CONFIG3L_unused=0x00 CONFIG3H_unused=0x00 CONFIG3H~1=CCP2MX,0x01,CCP2 Mux CONFIG3H~2=ECCPXM,0x02,ECCP Mux CONFIG3H~1~1=0x01,0x01,ECCP2 I/O Muxed With RC1 CONFIG3H~1~2=0x01,0x00,ECCP2 IP Muxed With RE7 CONFIG3H~2~1=0x02,0x02,P1B/P1C On RE6/RE5, P3B/P3C On RE4/RE3 CONFIG3H~2~2=0x02,0x00,P1B/P1C On RH7/RH6, P3B/P3C Onto RH5/RH4 CONFIG4L_unused=0x00 CONFIG4H_unused=0x00 erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F66J50] pgmmem=0x0 ~pgmmem=0x1fff7 cfgmem=0x1fff8 ~cfgmem=0x1ffff userid= ~userid= eedata=0x00 ~eedata=0xf5f devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x4140 configslots=8 0x1fff8=CONFIG1L 0x1fff9=CONFIG1H 0x1fffa=CONFIG2L 0x1fffb=CONFIG2H 0x1fffc=CONFIG3L 0x1fffd=CONFIG3H 0x1fffe=CONFIG4L 0x1ffff=CONFIG4H CONFIG1L_unused=0x00 CONFIG1L~1=WDTEN,0x01,Watchdog Timer Enable CONFIG1L~2=STVREN,0x0E,PLL Configuration CONFIG1L~3=ENHCPU,0x20,Stack Overflow Reset CONFIG1L~4=EXTCPU,0x40,Extended CPU CONFIG1L~5=BACKBUG,0x80,Background Debug CONFIG1L~1~1=0x01,0x01,Enabled CONFIG1L~1~2=0x01,0x00,Disabled CONFIG1L~2~1=0x0E,0x0E,No Divide (4MHz input) CONFIG1L~2~2=0x0E,0x0C,Divide by 2 (8MHz input) CONFIG1L~2~3=0x0E,0x0A,Divide by 3 (12MHz input) CONFIG1L~2~4=0x0E,0x08,Divide by 4 (16MHz input) CONFIG1L~2~5=0x0E,0x06,Divide by 5 (20MHz input) CONFIG1L~2~6=0x0E,0x04,Divide by 6 (24MHz input) CONFIG1L~2~7=0x0E,0x02,Divide by 10 (40MHz input) CONFIG1L~2~8=0x0E,0x00,Divide by 12 (48MHz input) CONFIG1L~3~1=0x20,0x20,Enabled CONFIG1L~3~2=0x20,0x00,Disabled CONFIG1L~4~1=0x40,0x40,Enabled CONFIG1L~4~2=0x40,0x00,Disabled CONFIG1L~5~1=0x80,0x80,Disabled CONFIG1L~5~2=0x80,0x00,Enabled CONFIG1H_unused=0x00 CONFIG1H~1=CPDIV,0x3,CPU Clock Divider CONFIG1H~2=CP_0,0x4,Code Protection CONFIG1H~1~1=0x3,0x3,No divide CONFIG1H~1~2=0x3,0x2,Divide by 2 CONFIG1H~1~3=0x3,0x1,Divide by 3 CONFIG1H~1~4=0x3,0x0,Divide by 6 CONFIG1H~2~1=0x4,0x4,Disabled CONFIG1H~2~2=0x4,0x00,Enabled CONFIG2L_unused=0x00 CONFIG2L~1=FOSC,0x07,Oscillator CONFIG2L~2=FCMEN,0x40,Fail Safe Monitor Clock Enable CONFIG2L~3=IESO,0x80,Internal External Switch Over Enable CONFIG2L~1~1=0x07,0x07,EC+PLL(CLKO-RA6) USB-EC+PLL CONFIG2L~1~2=0x07,0x06,EC(CLKO-RA6) USB-EC CONFIG2L~1~3=0x07,0x05,HS+PLL USB-HS+PLL CONFIG2L~1~4=0x07,0x04,HS USB-HS CONFIG2L~1~5=0x07,0x03,INTOSC EC+PLL Osc with CLKOUT CONFIG2L~1~6=0x07,0x02,INTOSC EC Osc with CLKOUT CONFIG2L~1~7=0x07,0x01,INTOSC HS+PLL Osc CONFIG2L~1~8=0x07,0x00,INTOSC HS Osc CONFIG2L~2~1=0x40,0x40,Enabled CONFIG2L~2~2=0x40,0x00,Disabled CONFIG2L~3~1=0x80,0x80,Enabled CONFIG2L~3~2=0x80,0x00,Disabled CONFIG2H_unused=0x00 CONFIG2H~1=WDTPS,0x0f,Watchdog Timer Postscale CONFIG2H~1~1=0x000f,0x000f,1:32,768 CONFIG2H~1~2=0x000f,0x000e,1:16,384 CONFIG2H~1~3=0x000f,0x000d,1:8,192 CONFIG2H~1~4=0x000f,0x000c,1:4,096 CONFIG2H~1~5=0x000f,0x000b,1:2,048 CONFIG2H~1~6=0x000f,0x000a,1:1,024 CONFIG2H~1~7=0x000f,0x0009,1:512 CONFIG2H~1~8=0x000f,0x0008,1:256 CONFIG2H~1~9=0x000f,0x0007,1:128 CONFIG2H~1~10=0x000f,0x0006,1:64 CONFIG2H~1~11=0x000f,0x0005,1:32 CONFIG2H~1~12=0x000f,0x0004,1:16 CONFIG2H~1~13=0x000f,0x0003,1:8 CONFIG2H~1~14=0x000f,0x0002,1:4 CONFIG2H~1~15=0x000f,0x0001,1:2 CONFIG2H~1~16=0x000f,0x0000,1:1 CONFIG3L_unused=0x00 CONFIG3H_unused=0x00 CONFIG3H~1=CCP2MX,0x01,CCP2 Mux CONFIG3H~2=ECCPXM,0x02,ECCP Mux CONFIG3H~1~1=0x01,0x01,ECCP2 I/O Muxed With RC1 CONFIG3H~1~2=0x01,0x00,ECCP2 IP Muxed With RE7 CONFIG3H~2~1=0x02,0x02,P1B/P1C On RE6/RE5, P3B/P3C On RE4/RE3 CONFIG3H~2~2=0x02,0x00,P1B/P1C On RH7/RH6, P3B/P3C Onto RH5/RH4 CONFIG4L_unused=0x00 CONFIG4H_unused=0x00 erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F66J55] pgmmem=0x0 ~pgmmem=0x1fff7 cfgmem=0x1fff8 ~cfgmem=0x1ffff userid= ~userid= eedata=0x00 ~eedata=0xf5f devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x4160 configslots=8 0x1fff8=CONFIG1L 0x1fff9=CONFIG1H 0x1fffa=CONFIG2L 0x1fffb=CONFIG2H 0x1fffc=CONFIG3L 0x1fffd=CONFIG3H 0x1fffe=CONFIG4L 0x1ffff=CONFIG4H CONFIG1L_unused=0x00 CONFIG1L~1=WDTEN,0x01,Watchdog Timer Enable CONFIG1L~2=STVREN,0x0E,PLL Configuration CONFIG1L~3=ENHCPU,0x20,Stack Overflow Reset CONFIG1L~4=EXTCPU,0x40,Extended CPU CONFIG1L~5=BACKBUG,0x80,Background Debug CONFIG1L~1~1=0x01,0x01,Enabled CONFIG1L~1~2=0x01,0x00,Disabled CONFIG1L~2~1=0x0E,0x0E,No Divide (4MHz input) CONFIG1L~2~2=0x0E,0x0C,Divide by 2 (8MHz input) CONFIG1L~2~3=0x0E,0x0A,Divide by 3 (12MHz input) CONFIG1L~2~4=0x0E,0x08,Divide by 4 (16MHz input) CONFIG1L~2~5=0x0E,0x06,Divide by 5 (20MHz input) CONFIG1L~2~6=0x0E,0x04,Divide by 6 (24MHz input) CONFIG1L~2~7=0x0E,0x02,Divide by 10 (40MHz input) CONFIG1L~2~8=0x0E,0x00,Divide by 12 (48MHz input) CONFIG1L~3~1=0x20,0x20,Enabled CONFIG1L~3~2=0x20,0x00,Disabled CONFIG1L~4~1=0x40,0x40,Enabled CONFIG1L~4~2=0x40,0x00,Disabled CONFIG1L~5~1=0x80,0x80,Disabled CONFIG1L~5~2=0x80,0x00,Enabled CONFIG1H_unused=0x00 CONFIG1H~1=CPDIV,0x3,CPU Clock Divider CONFIG1H~2=CP_0,0x4,Code Protection CONFIG1H~1~1=0x3,0x3,No divide CONFIG1H~1~2=0x3,0x2,Divide by 2 CONFIG1H~1~3=0x3,0x1,Divide by 3 CONFIG1H~1~4=0x3,0x0,Divide by 6 CONFIG1H~2~1=0x4,0x4,Disabled CONFIG1H~2~2=0x4,0x00,Enabled CONFIG2L_unused=0x00 CONFIG2L~1=FOSC,0x07,Oscillator CONFIG2L~2=FCMEN,0x40,Fail Safe Monitor Clock Enable CONFIG2L~3=IESO,0x80,Internal External Switch Over Enable CONFIG2L~1~1=0x07,0x07,EC+PLL(CLKO-RA6) USB-EC+PLL CONFIG2L~1~2=0x07,0x06,EC(CLKO-RA6) USB-EC CONFIG2L~1~3=0x07,0x05,HS+PLL USB-HS+PLL CONFIG2L~1~4=0x07,0x04,HS USB-HS CONFIG2L~1~5=0x07,0x03,INTOSC EC+PLL Osc with CLKOUT CONFIG2L~1~6=0x07,0x02,INTOSC EC Osc with CLKOUT CONFIG2L~1~7=0x07,0x01,INTOSC HS+PLL Osc CONFIG2L~1~8=0x07,0x00,INTOSC HS Osc CONFIG2L~2~1=0x40,0x40,Enabled CONFIG2L~2~2=0x40,0x00,Disabled CONFIG2L~3~1=0x80,0x80,Enabled CONFIG2L~3~2=0x80,0x00,Disabled CONFIG2H_unused=0x00 CONFIG2H~1=WDTPS,0x0f,Watchdog Timer Postscale CONFIG2H~1~1=0x000f,0x000f,1:32,768 CONFIG2H~1~2=0x000f,0x000e,1:16,384 CONFIG2H~1~3=0x000f,0x000d,1:8,192 CONFIG2H~1~4=0x000f,0x000c,1:4,096 CONFIG2H~1~5=0x000f,0x000b,1:2,048 CONFIG2H~1~6=0x000f,0x000a,1:1,024 CONFIG2H~1~7=0x000f,0x0009,1:512 CONFIG2H~1~8=0x000f,0x0008,1:256 CONFIG2H~1~9=0x000f,0x0007,1:128 CONFIG2H~1~10=0x000f,0x0006,1:64 CONFIG2H~1~11=0x000f,0x0005,1:32 CONFIG2H~1~12=0x000f,0x0004,1:16 CONFIG2H~1~13=0x000f,0x0003,1:8 CONFIG2H~1~14=0x000f,0x0002,1:4 CONFIG2H~1~15=0x000f,0x0001,1:2 CONFIG2H~1~16=0x000f,0x0000,1:1 CONFIG3L_unused=0x00 CONFIG3H_unused=0x00 CONFIG3H~1=CCP2MX,0x01,CCP2 Mux CONFIG3H~2=ECCPXM,0x02,ECCP Mux CONFIG3H~1~1=0x01,0x01,ECCP2 I/O Muxed With RC1 CONFIG3H~1~2=0x01,0x00,ECCP2 IP Muxed With RE7 CONFIG3H~2~1=0x02,0x02,P1B/P1C On RE6/RE5, P3B/P3C On RE4/RE3 CONFIG3H~2~2=0x02,0x00,P1B/P1C On RH7/RH6, P3B/P3C Onto RH5/RH4 CONFIG4L_unused=0x00 CONFIG4H_unused=0x00 erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F66J90] pgmmem=0x0 ~pgmmem=0x1fff7 cfgmem=0x1fff8 ~cfgmem=0x1ffff userid= ~userid= eedata=0x00 ~eedata=0xf5f devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x5000 configslots=8 0x1fff8=CONFIG1L 0x1fff9=CONFIG1H 0x1fffa=CONFIG2L 0x1fffb=CONFIG2H 0x1fffc=CONFIG3L 0x1fffd=CONFIG3H 0x1fffe=CONFIG4L 0x1ffff=CONFIG4H CONFIG1L_unused=0x00 CONFIG1L~1=WDTEN,0x01,Watchdog Timer Enable CONFIG1L~2=STVREN,0x0E,PLL Configuration CONFIG1L~3=ENHCPU,0x20,Stack Overflow Reset CONFIG1L~4=EXTCPU,0x40,Extended CPU CONFIG1L~5=BACKBUG,0x80,Background Debug CONFIG1L~1~1=0x01,0x01,Enabled CONFIG1L~1~2=0x01,0x00,Disabled CONFIG1L~2~1=0x0E,0x0E,No Divide (4MHz input) CONFIG1L~2~2=0x0E,0x0C,Divide by 2 (8MHz input) CONFIG1L~2~3=0x0E,0x0A,Divide by 3 (12MHz input) CONFIG1L~2~4=0x0E,0x08,Divide by 4 (16MHz input) CONFIG1L~2~5=0x0E,0x06,Divide by 5 (20MHz input) CONFIG1L~2~6=0x0E,0x04,Divide by 6 (24MHz input) CONFIG1L~2~7=0x0E,0x02,Divide by 10 (40MHz input) CONFIG1L~2~8=0x0E,0x00,Divide by 12 (48MHz input) CONFIG1L~3~1=0x20,0x20,Enabled CONFIG1L~3~2=0x20,0x00,Disabled CONFIG1L~4~1=0x40,0x40,Enabled CONFIG1L~4~2=0x40,0x00,Disabled CONFIG1L~5~1=0x80,0x80,Disabled CONFIG1L~5~2=0x80,0x00,Enabled CONFIG1H_unused=0x00 CONFIG1H~1=CPDIV,0x3,CPU Clock Divider CONFIG1H~2=CP_0,0x4,Code Protection CONFIG1H~1~1=0x3,0x3,No divide CONFIG1H~1~2=0x3,0x2,Divide by 2 CONFIG1H~1~3=0x3,0x1,Divide by 3 CONFIG1H~1~4=0x3,0x0,Divide by 6 CONFIG1H~2~1=0x4,0x4,Disabled CONFIG1H~2~2=0x4,0x00,Enabled CONFIG2L_unused=0x00 CONFIG2L~1=FOSC,0x07,Oscillator CONFIG2L~2=FCMEN,0x40,Fail Safe Monitor Clock Enable CONFIG2L~3=IESO,0x80,Internal External Switch Over Enable CONFIG2L~1~1=0x07,0x07,EC+PLL(CLKO-RA6) USB-EC+PLL CONFIG2L~1~2=0x07,0x06,EC(CLKO-RA6) USB-EC CONFIG2L~1~3=0x07,0x05,HS+PLL USB-HS+PLL CONFIG2L~1~4=0x07,0x04,HS USB-HS CONFIG2L~1~5=0x07,0x03,INTOSC EC+PLL Osc with CLKOUT CONFIG2L~1~6=0x07,0x02,INTOSC EC Osc with CLKOUT CONFIG2L~1~7=0x07,0x01,INTOSC HS+PLL Osc CONFIG2L~1~8=0x07,0x00,INTOSC HS Osc CONFIG2L~2~1=0x40,0x40,Enabled CONFIG2L~2~2=0x40,0x00,Disabled CONFIG2L~3~1=0x80,0x80,Enabled CONFIG2L~3~2=0x80,0x00,Disabled CONFIG2H_unused=0x00 CONFIG2H~1=WDTPS,0x0f,Watchdog Timer Postscale CONFIG2H~1~1=0x000f,0x000f,1:32,768 CONFIG2H~1~2=0x000f,0x000e,1:16,384 CONFIG2H~1~3=0x000f,0x000d,1:8,192 CONFIG2H~1~4=0x000f,0x000c,1:4,096 CONFIG2H~1~5=0x000f,0x000b,1:2,048 CONFIG2H~1~6=0x000f,0x000a,1:1,024 CONFIG2H~1~7=0x000f,0x0009,1:512 CONFIG2H~1~8=0x000f,0x0008,1:256 CONFIG2H~1~9=0x000f,0x0007,1:128 CONFIG2H~1~10=0x000f,0x0006,1:64 CONFIG2H~1~11=0x000f,0x0005,1:32 CONFIG2H~1~12=0x000f,0x0004,1:16 CONFIG2H~1~13=0x000f,0x0003,1:8 CONFIG2H~1~14=0x000f,0x0002,1:4 CONFIG2H~1~15=0x000f,0x0001,1:2 CONFIG2H~1~16=0x000f,0x0000,1:1 CONFIG3L_unused=0x00 CONFIG3H_unused=0x00 CONFIG3H~1=CCP2MX,0x01,CCP2 Mux CONFIG3H~2=ECCPXM,0x02,ECCP Mux CONFIG3H~1~1=0x01,0x01,ECCP2 I/O Muxed With RC1 CONFIG3H~1~2=0x01,0x00,ECCP2 IP Muxed With RE7 CONFIG3H~2~1=0x02,0x02,P1B/P1C On RE6/RE5, P3B/P3C On RE4/RE3 CONFIG3H~2~2=0x02,0x00,P1B/P1C On RH7/RH6, P3B/P3C Onto RH5/RH4 CONFIG4L_unused=0x00 CONFIG4H_unused=0x00 erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F66J93] pgmmem=0x0 ~pgmmem=0x1fff7 cfgmem=0x1fff8 ~cfgmem=0x1ffff userid= ~userid= eedata=0x00 ~eedata=0xf5f devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x5040 configslots=8 0x1fff8=CONFIG1L 0x1fff9=CONFIG1H 0x1fffa=CONFIG2L 0x1fffb=CONFIG2H 0x1fffc=CONFIG3L 0x1fffd=CONFIG3H 0x1fffe=CONFIG4L 0x1ffff=CONFIG4H CONFIG1L_unused=0x00 CONFIG1L~1=WDTEN,0x01,Watchdog Timer Enable CONFIG1L~2=STVREN,0x0E,PLL Configuration CONFIG1L~3=ENHCPU,0x20,Stack Overflow Reset CONFIG1L~4=EXTCPU,0x40,Extended CPU CONFIG1L~5=BACKBUG,0x80,Background Debug CONFIG1L~1~1=0x01,0x01,Enabled CONFIG1L~1~2=0x01,0x00,Disabled CONFIG1L~2~1=0x0E,0x0E,No Divide (4MHz input) CONFIG1L~2~2=0x0E,0x0C,Divide by 2 (8MHz input) CONFIG1L~2~3=0x0E,0x0A,Divide by 3 (12MHz input) CONFIG1L~2~4=0x0E,0x08,Divide by 4 (16MHz input) CONFIG1L~2~5=0x0E,0x06,Divide by 5 (20MHz input) CONFIG1L~2~6=0x0E,0x04,Divide by 6 (24MHz input) CONFIG1L~2~7=0x0E,0x02,Divide by 10 (40MHz input) CONFIG1L~2~8=0x0E,0x00,Divide by 12 (48MHz input) CONFIG1L~3~1=0x20,0x20,Enabled CONFIG1L~3~2=0x20,0x00,Disabled CONFIG1L~4~1=0x40,0x40,Enabled CONFIG1L~4~2=0x40,0x00,Disabled CONFIG1L~5~1=0x80,0x80,Disabled CONFIG1L~5~2=0x80,0x00,Enabled CONFIG1H_unused=0x00 CONFIG1H~1=CPDIV,0x3,CPU Clock Divider CONFIG1H~2=CP_0,0x4,Code Protection CONFIG1H~1~1=0x3,0x3,No divide CONFIG1H~1~2=0x3,0x2,Divide by 2 CONFIG1H~1~3=0x3,0x1,Divide by 3 CONFIG1H~1~4=0x3,0x0,Divide by 6 CONFIG1H~2~1=0x4,0x4,Disabled CONFIG1H~2~2=0x4,0x00,Enabled CONFIG2L_unused=0x00 CONFIG2L~1=FOSC,0x07,Oscillator CONFIG2L~2=FCMEN,0x40,Fail Safe Monitor Clock Enable CONFIG2L~3=IESO,0x80,Internal External Switch Over Enable CONFIG2L~1~1=0x07,0x07,EC+PLL(CLKO-RA6) USB-EC+PLL CONFIG2L~1~2=0x07,0x06,EC(CLKO-RA6) USB-EC CONFIG2L~1~3=0x07,0x05,HS+PLL USB-HS+PLL CONFIG2L~1~4=0x07,0x04,HS USB-HS CONFIG2L~1~5=0x07,0x03,INTOSC EC+PLL Osc with CLKOUT CONFIG2L~1~6=0x07,0x02,INTOSC EC Osc with CLKOUT CONFIG2L~1~7=0x07,0x01,INTOSC HS+PLL Osc CONFIG2L~1~8=0x07,0x00,INTOSC HS Osc CONFIG2L~2~1=0x40,0x40,Enabled CONFIG2L~2~2=0x40,0x00,Disabled CONFIG2L~3~1=0x80,0x80,Enabled CONFIG2L~3~2=0x80,0x00,Disabled CONFIG2H_unused=0x00 CONFIG2H~1=WDTPS,0x0f,Watchdog Timer Postscale CONFIG2H~1~1=0x000f,0x000f,1:32,768 CONFIG2H~1~2=0x000f,0x000e,1:16,384 CONFIG2H~1~3=0x000f,0x000d,1:8,192 CONFIG2H~1~4=0x000f,0x000c,1:4,096 CONFIG2H~1~5=0x000f,0x000b,1:2,048 CONFIG2H~1~6=0x000f,0x000a,1:1,024 CONFIG2H~1~7=0x000f,0x0009,1:512 CONFIG2H~1~8=0x000f,0x0008,1:256 CONFIG2H~1~9=0x000f,0x0007,1:128 CONFIG2H~1~10=0x000f,0x0006,1:64 CONFIG2H~1~11=0x000f,0x0005,1:32 CONFIG2H~1~12=0x000f,0x0004,1:16 CONFIG2H~1~13=0x000f,0x0003,1:8 CONFIG2H~1~14=0x000f,0x0002,1:4 CONFIG2H~1~15=0x000f,0x0001,1:2 CONFIG2H~1~16=0x000f,0x0000,1:1 CONFIG3L_unused=0x00 CONFIG3H_unused=0x00 CONFIG3H~1=CCP2MX,0x01,CCP2 Mux CONFIG3H~2=ECCPXM,0x02,ECCP Mux CONFIG3H~1~1=0x01,0x01,ECCP2 I/O Muxed With RC1 CONFIG3H~1~2=0x01,0x00,ECCP2 IP Muxed With RE7 CONFIG3H~2~1=0x02,0x02,P1B/P1C On RE6/RE5, P3B/P3C On RE4/RE3 CONFIG3H~2~2=0x02,0x00,P1B/P1C On RH7/RH6, P3B/P3C Onto RH5/RH4 CONFIG4L_unused=0x00 CONFIG4H_unused=0x00 erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F67J10] pgmmem=0x0 ~pgmmem=0x1fff7 cfgmem=0x1fff8 ~cfgmem=0x1ffff userid= ~userid= eedata=0x00 ~eedata=0xf5f devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x15A0 configslots=8 0x1fff8=CONFIG1L 0x1fff9=CONFIG1H 0x1fffa=CONFIG2L 0x1fffb=CONFIG2H 0x1fffc=CONFIG3L 0x1fffd=CONFIG3H 0x1fffe=CONFIG4L 0x1ffff=CONFIG4H CONFIG1L_unused=0x00 CONFIG1L~1=WDTEN,0x01,Watchdog Timer Enable CONFIG1L~2=STVREN,0x0E,PLL Configuration CONFIG1L~3=ENHCPU,0x20,Stack Overflow Reset CONFIG1L~4=EXTCPU,0x40,Extended CPU CONFIG1L~5=BACKBUG,0x80,Background Debug CONFIG1L~1~1=0x01,0x01,Enabled CONFIG1L~1~2=0x01,0x00,Disabled CONFIG1L~2~1=0x0E,0x0E,No Divide (4MHz input) CONFIG1L~2~2=0x0E,0x0C,Divide by 2 (8MHz input) CONFIG1L~2~3=0x0E,0x0A,Divide by 3 (12MHz input) CONFIG1L~2~4=0x0E,0x08,Divide by 4 (16MHz input) CONFIG1L~2~5=0x0E,0x06,Divide by 5 (20MHz input) CONFIG1L~2~6=0x0E,0x04,Divide by 6 (24MHz input) CONFIG1L~2~7=0x0E,0x02,Divide by 10 (40MHz input) CONFIG1L~2~8=0x0E,0x00,Divide by 12 (48MHz input) CONFIG1L~3~1=0x20,0x20,Enabled CONFIG1L~3~2=0x20,0x00,Disabled CONFIG1L~4~1=0x40,0x40,Enabled CONFIG1L~4~2=0x40,0x00,Disabled CONFIG1L~5~1=0x80,0x80,Disabled CONFIG1L~5~2=0x80,0x00,Enabled CONFIG1H_unused=0x00 CONFIG1H~1=CPDIV,0x3,CPU Clock Divider CONFIG1H~2=CP_0,0x4,Code Protection CONFIG1H~1~1=0x3,0x3,No divide CONFIG1H~1~2=0x3,0x2,Divide by 2 CONFIG1H~1~3=0x3,0x1,Divide by 3 CONFIG1H~1~4=0x3,0x0,Divide by 6 CONFIG1H~2~1=0x4,0x4,Disabled CONFIG1H~2~2=0x4,0x00,Enabled CONFIG2L_unused=0x00 CONFIG2L~1=FOSC,0x07,Oscillator CONFIG2L~2=FCMEN,0x40,Fail Safe Monitor Clock Enable CONFIG2L~3=IESO,0x80,Internal External Switch Over Enable CONFIG2L~1~1=0x07,0x07,EC+PLL(CLKO-RA6) USB-EC+PLL CONFIG2L~1~2=0x07,0x06,EC(CLKO-RA6) USB-EC CONFIG2L~1~3=0x07,0x05,HS+PLL USB-HS+PLL CONFIG2L~1~4=0x07,0x04,HS USB-HS CONFIG2L~1~5=0x07,0x03,INTOSC EC+PLL Osc with CLKOUT CONFIG2L~1~6=0x07,0x02,INTOSC EC Osc with CLKOUT CONFIG2L~1~7=0x07,0x01,INTOSC HS+PLL Osc CONFIG2L~1~8=0x07,0x00,INTOSC HS Osc CONFIG2L~2~1=0x40,0x40,Enabled CONFIG2L~2~2=0x40,0x00,Disabled CONFIG2L~3~1=0x80,0x80,Enabled CONFIG2L~3~2=0x80,0x00,Disabled CONFIG2H_unused=0x00 CONFIG2H~1=WDTPS,0x0f,Watchdog Timer Postscale CONFIG2H~1~1=0x000f,0x000f,1:32,768 CONFIG2H~1~2=0x000f,0x000e,1:16,384 CONFIG2H~1~3=0x000f,0x000d,1:8,192 CONFIG2H~1~4=0x000f,0x000c,1:4,096 CONFIG2H~1~5=0x000f,0x000b,1:2,048 CONFIG2H~1~6=0x000f,0x000a,1:1,024 CONFIG2H~1~7=0x000f,0x0009,1:512 CONFIG2H~1~8=0x000f,0x0008,1:256 CONFIG2H~1~9=0x000f,0x0007,1:128 CONFIG2H~1~10=0x000f,0x0006,1:64 CONFIG2H~1~11=0x000f,0x0005,1:32 CONFIG2H~1~12=0x000f,0x0004,1:16 CONFIG2H~1~13=0x000f,0x0003,1:8 CONFIG2H~1~14=0x000f,0x0002,1:4 CONFIG2H~1~15=0x000f,0x0001,1:2 CONFIG2H~1~16=0x000f,0x0000,1:1 CONFIG3L_unused=0x00 CONFIG3H_unused=0x00 CONFIG3H~1=CCP2MX,0x01,CCP2 Mux CONFIG3H~2=ECCPXM,0x02,ECCP Mux CONFIG3H~1~1=0x01,0x01,ECCP2 I/O Muxed With RC1 CONFIG3H~1~2=0x01,0x00,ECCP2 IP Muxed With RE7 CONFIG3H~2~1=0x02,0x02,P1B/P1C On RE6/RE5, P3B/P3C On RE4/RE3 CONFIG3H~2~2=0x02,0x00,P1B/P1C On RH7/RH6, P3B/P3C Onto RH5/RH4 CONFIG4L_unused=0x00 CONFIG4H_unused=0x00 erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F67J11] pgmmem=0x0 ~pgmmem=0x1fff7 cfgmem=0x1fff8 ~cfgmem=0x1ffff userid= ~userid= eedata=0x00 ~eedata=0xf5f devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x4480 configslots=8 0x1fff8=CONFIG1L 0x1fff9=CONFIG1H 0x1fffa=CONFIG2L 0x1fffb=CONFIG2H 0x1fffc=CONFIG3L 0x1fffd=CONFIG3H 0x1fffe=CONFIG4L 0x1ffff=CONFIG4H CONFIG1L_unused=0x00 CONFIG1L~1=WDTEN,0x01,Watchdog Timer Enable CONFIG1L~2=STVREN,0x0E,PLL Configuration CONFIG1L~3=ENHCPU,0x20,Stack Overflow Reset CONFIG1L~4=EXTCPU,0x40,Extended CPU CONFIG1L~5=BACKBUG,0x80,Background Debug CONFIG1L~1~1=0x01,0x01,Enabled CONFIG1L~1~2=0x01,0x00,Disabled CONFIG1L~2~1=0x0E,0x0E,No Divide (4MHz input) CONFIG1L~2~2=0x0E,0x0C,Divide by 2 (8MHz input) CONFIG1L~2~3=0x0E,0x0A,Divide by 3 (12MHz input) CONFIG1L~2~4=0x0E,0x08,Divide by 4 (16MHz input) CONFIG1L~2~5=0x0E,0x06,Divide by 5 (20MHz input) CONFIG1L~2~6=0x0E,0x04,Divide by 6 (24MHz input) CONFIG1L~2~7=0x0E,0x02,Divide by 10 (40MHz input) CONFIG1L~2~8=0x0E,0x00,Divide by 12 (48MHz input) CONFIG1L~3~1=0x20,0x20,Enabled CONFIG1L~3~2=0x20,0x00,Disabled CONFIG1L~4~1=0x40,0x40,Enabled CONFIG1L~4~2=0x40,0x00,Disabled CONFIG1L~5~1=0x80,0x80,Disabled CONFIG1L~5~2=0x80,0x00,Enabled CONFIG1H_unused=0x00 CONFIG1H~1=CPDIV,0x3,CPU Clock Divider CONFIG1H~2=CP_0,0x4,Code Protection CONFIG1H~1~1=0x3,0x3,No divide CONFIG1H~1~2=0x3,0x2,Divide by 2 CONFIG1H~1~3=0x3,0x1,Divide by 3 CONFIG1H~1~4=0x3,0x0,Divide by 6 CONFIG1H~2~1=0x4,0x4,Disabled CONFIG1H~2~2=0x4,0x00,Enabled CONFIG2L_unused=0x00 CONFIG2L~1=FOSC,0x07,Oscillator CONFIG2L~2=FCMEN,0x40,Fail Safe Monitor Clock Enable CONFIG2L~3=IESO,0x80,Internal External Switch Over Enable CONFIG2L~1~1=0x07,0x07,EC+PLL(CLKO-RA6) USB-EC+PLL CONFIG2L~1~2=0x07,0x06,EC(CLKO-RA6) USB-EC CONFIG2L~1~3=0x07,0x05,HS+PLL USB-HS+PLL CONFIG2L~1~4=0x07,0x04,HS USB-HS CONFIG2L~1~5=0x07,0x03,INTOSC EC+PLL Osc with CLKOUT CONFIG2L~1~6=0x07,0x02,INTOSC EC Osc with CLKOUT CONFIG2L~1~7=0x07,0x01,INTOSC HS+PLL Osc CONFIG2L~1~8=0x07,0x00,INTOSC HS Osc CONFIG2L~2~1=0x40,0x40,Enabled CONFIG2L~2~2=0x40,0x00,Disabled CONFIG2L~3~1=0x80,0x80,Enabled CONFIG2L~3~2=0x80,0x00,Disabled CONFIG2H_unused=0x00 CONFIG2H~1=WDTPS,0x0f,Watchdog Timer Postscale CONFIG2H~1~1=0x000f,0x000f,1:32,768 CONFIG2H~1~2=0x000f,0x000e,1:16,384 CONFIG2H~1~3=0x000f,0x000d,1:8,192 CONFIG2H~1~4=0x000f,0x000c,1:4,096 CONFIG2H~1~5=0x000f,0x000b,1:2,048 CONFIG2H~1~6=0x000f,0x000a,1:1,024 CONFIG2H~1~7=0x000f,0x0009,1:512 CONFIG2H~1~8=0x000f,0x0008,1:256 CONFIG2H~1~9=0x000f,0x0007,1:128 CONFIG2H~1~10=0x000f,0x0006,1:64 CONFIG2H~1~11=0x000f,0x0005,1:32 CONFIG2H~1~12=0x000f,0x0004,1:16 CONFIG2H~1~13=0x000f,0x0003,1:8 CONFIG2H~1~14=0x000f,0x0002,1:4 CONFIG2H~1~15=0x000f,0x0001,1:2 CONFIG2H~1~16=0x000f,0x0000,1:1 CONFIG3L_unused=0x00 CONFIG3H_unused=0x00 CONFIG3H~1=CCP2MX,0x01,CCP2 Mux CONFIG3H~2=ECCPXM,0x02,ECCP Mux CONFIG3H~1~1=0x01,0x01,ECCP2 I/O Muxed With RC1 CONFIG3H~1~2=0x01,0x00,ECCP2 IP Muxed With RE7 CONFIG3H~2~1=0x02,0x02,P1B/P1C On RE6/RE5, P3B/P3C On RE4/RE3 CONFIG3H~2~2=0x02,0x00,P1B/P1C On RH7/RH6, P3B/P3C Onto RH5/RH4 CONFIG4L_unused=0x00 CONFIG4H_unused=0x00 erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F67J50] pgmmem=0x0 ~pgmmem=0x1fff7 cfgmem=0x1fff8 ~cfgmem=0x1ffff userid= ~userid= eedata=0x00 ~eedata=0xf5f devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x4180 configslots=8 0x1fff8=CONFIG1L 0x1fff9=CONFIG1H 0x1fffa=CONFIG2L 0x1fffb=CONFIG2H 0x1fffc=CONFIG3L 0x1fffd=CONFIG3H 0x1fffe=CONFIG4L 0x1ffff=CONFIG4H CONFIG1L_unused=0x00 CONFIG1L~1=WDTEN,0x01,Watchdog Timer Enable CONFIG1L~2=STVREN,0x0E,PLL Configuration CONFIG1L~3=ENHCPU,0x20,Stack Overflow Reset CONFIG1L~4=EXTCPU,0x40,Extended CPU CONFIG1L~5=BACKBUG,0x80,Background Debug CONFIG1L~1~1=0x01,0x01,Enabled CONFIG1L~1~2=0x01,0x00,Disabled CONFIG1L~2~1=0x0E,0x0E,No Divide (4MHz input) CONFIG1L~2~2=0x0E,0x0C,Divide by 2 (8MHz input) CONFIG1L~2~3=0x0E,0x0A,Divide by 3 (12MHz input) CONFIG1L~2~4=0x0E,0x08,Divide by 4 (16MHz input) CONFIG1L~2~5=0x0E,0x06,Divide by 5 (20MHz input) CONFIG1L~2~6=0x0E,0x04,Divide by 6 (24MHz input) CONFIG1L~2~7=0x0E,0x02,Divide by 10 (40MHz input) CONFIG1L~2~8=0x0E,0x00,Divide by 12 (48MHz input) CONFIG1L~3~1=0x20,0x20,Enabled CONFIG1L~3~2=0x20,0x00,Disabled CONFIG1L~4~1=0x40,0x40,Enabled CONFIG1L~4~2=0x40,0x00,Disabled CONFIG1L~5~1=0x80,0x80,Disabled CONFIG1L~5~2=0x80,0x00,Enabled CONFIG1H_unused=0x00 CONFIG1H~1=CPDIV,0x3,CPU Clock Divider CONFIG1H~2=CP_0,0x4,Code Protection CONFIG1H~1~1=0x3,0x3,No divide CONFIG1H~1~2=0x3,0x2,Divide by 2 CONFIG1H~1~3=0x3,0x1,Divide by 3 CONFIG1H~1~4=0x3,0x0,Divide by 6 CONFIG1H~2~1=0x4,0x4,Disabled CONFIG1H~2~2=0x4,0x00,Enabled CONFIG2L_unused=0x00 CONFIG2L~1=FOSC,0x07,Oscillator CONFIG2L~2=FCMEN,0x40,Fail Safe Monitor Clock Enable CONFIG2L~3=IESO,0x80,Internal External Switch Over Enable CONFIG2L~1~1=0x07,0x07,EC+PLL(CLKO-RA6) USB-EC+PLL CONFIG2L~1~2=0x07,0x06,EC(CLKO-RA6) USB-EC CONFIG2L~1~3=0x07,0x05,HS+PLL USB-HS+PLL CONFIG2L~1~4=0x07,0x04,HS USB-HS CONFIG2L~1~5=0x07,0x03,INTOSC EC+PLL Osc with CLKOUT CONFIG2L~1~6=0x07,0x02,INTOSC EC Osc with CLKOUT CONFIG2L~1~7=0x07,0x01,INTOSC HS+PLL Osc CONFIG2L~1~8=0x07,0x00,INTOSC HS Osc CONFIG2L~2~1=0x40,0x40,Enabled CONFIG2L~2~2=0x40,0x00,Disabled CONFIG2L~3~1=0x80,0x80,Enabled CONFIG2L~3~2=0x80,0x00,Disabled CONFIG2H_unused=0x00 CONFIG2H~1=WDTPS,0x0f,Watchdog Timer Postscale CONFIG2H~1~1=0x000f,0x000f,1:32,768 CONFIG2H~1~2=0x000f,0x000e,1:16,384 CONFIG2H~1~3=0x000f,0x000d,1:8,192 CONFIG2H~1~4=0x000f,0x000c,1:4,096 CONFIG2H~1~5=0x000f,0x000b,1:2,048 CONFIG2H~1~6=0x000f,0x000a,1:1,024 CONFIG2H~1~7=0x000f,0x0009,1:512 CONFIG2H~1~8=0x000f,0x0008,1:256 CONFIG2H~1~9=0x000f,0x0007,1:128 CONFIG2H~1~10=0x000f,0x0006,1:64 CONFIG2H~1~11=0x000f,0x0005,1:32 CONFIG2H~1~12=0x000f,0x0004,1:16 CONFIG2H~1~13=0x000f,0x0003,1:8 CONFIG2H~1~14=0x000f,0x0002,1:4 CONFIG2H~1~15=0x000f,0x0001,1:2 CONFIG2H~1~16=0x000f,0x0000,1:1 CONFIG3L_unused=0x00 CONFIG3H_unused=0x00 CONFIG3H~1=CCP2MX,0x01,CCP2 Mux CONFIG3H~2=ECCPXM,0x02,ECCP Mux CONFIG3H~1~1=0x01,0x01,ECCP2 I/O Muxed With RC1 CONFIG3H~1~2=0x01,0x00,ECCP2 IP Muxed With RE7 CONFIG3H~2~1=0x02,0x02,P1B/P1C On RE6/RE5, P3B/P3C On RE4/RE3 CONFIG3H~2~2=0x02,0x00,P1B/P1C On RH7/RH6, P3B/P3C Onto RH5/RH4 CONFIG4L_unused=0x00 CONFIG4H_unused=0x00 erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F67J90] pgmmem=0x0 ~pgmmem=0x1fff7 cfgmem=0x1fff8 ~cfgmem=0x1ffff userid= ~userid= eedata=0x00 ~eedata=0xf5f devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x5020 configslots=8 0x1fff8=CONFIG1L 0x1fff9=CONFIG1H 0x1fffa=CONFIG2L 0x1fffb=CONFIG2H 0x1fffc=CONFIG3L 0x1fffd=CONFIG3H 0x1fffe=CONFIG4L 0x1ffff=CONFIG4H CONFIG1L_unused=0x00 CONFIG1L~1=WDTEN,0x01,Watchdog Timer Enable CONFIG1L~2=STVREN,0x0E,PLL Configuration CONFIG1L~3=ENHCPU,0x20,Stack Overflow Reset CONFIG1L~4=EXTCPU,0x40,Extended CPU CONFIG1L~5=BACKBUG,0x80,Background Debug CONFIG1L~1~1=0x01,0x01,Enabled CONFIG1L~1~2=0x01,0x00,Disabled CONFIG1L~2~1=0x0E,0x0E,No Divide (4MHz input) CONFIG1L~2~2=0x0E,0x0C,Divide by 2 (8MHz input) CONFIG1L~2~3=0x0E,0x0A,Divide by 3 (12MHz input) CONFIG1L~2~4=0x0E,0x08,Divide by 4 (16MHz input) CONFIG1L~2~5=0x0E,0x06,Divide by 5 (20MHz input) CONFIG1L~2~6=0x0E,0x04,Divide by 6 (24MHz input) CONFIG1L~2~7=0x0E,0x02,Divide by 10 (40MHz input) CONFIG1L~2~8=0x0E,0x00,Divide by 12 (48MHz input) CONFIG1L~3~1=0x20,0x20,Enabled CONFIG1L~3~2=0x20,0x00,Disabled CONFIG1L~4~1=0x40,0x40,Enabled CONFIG1L~4~2=0x40,0x00,Disabled CONFIG1L~5~1=0x80,0x80,Disabled CONFIG1L~5~2=0x80,0x00,Enabled CONFIG1H_unused=0x00 CONFIG1H~1=CPDIV,0x3,CPU Clock Divider CONFIG1H~2=CP_0,0x4,Code Protection CONFIG1H~1~1=0x3,0x3,No divide CONFIG1H~1~2=0x3,0x2,Divide by 2 CONFIG1H~1~3=0x3,0x1,Divide by 3 CONFIG1H~1~4=0x3,0x0,Divide by 6 CONFIG1H~2~1=0x4,0x4,Disabled CONFIG1H~2~2=0x4,0x00,Enabled CONFIG2L_unused=0x00 CONFIG2L~1=FOSC,0x07,Oscillator CONFIG2L~2=FCMEN,0x40,Fail Safe Monitor Clock Enable CONFIG2L~3=IESO,0x80,Internal External Switch Over Enable CONFIG2L~1~1=0x07,0x07,EC+PLL(CLKO-RA6) USB-EC+PLL CONFIG2L~1~2=0x07,0x06,EC(CLKO-RA6) USB-EC CONFIG2L~1~3=0x07,0x05,HS+PLL USB-HS+PLL CONFIG2L~1~4=0x07,0x04,HS USB-HS CONFIG2L~1~5=0x07,0x03,INTOSC EC+PLL Osc with CLKOUT CONFIG2L~1~6=0x07,0x02,INTOSC EC Osc with CLKOUT CONFIG2L~1~7=0x07,0x01,INTOSC HS+PLL Osc CONFIG2L~1~8=0x07,0x00,INTOSC HS Osc CONFIG2L~2~1=0x40,0x40,Enabled CONFIG2L~2~2=0x40,0x00,Disabled CONFIG2L~3~1=0x80,0x80,Enabled CONFIG2L~3~2=0x80,0x00,Disabled CONFIG2H_unused=0x00 CONFIG2H~1=WDTPS,0x0f,Watchdog Timer Postscale CONFIG2H~1~1=0x000f,0x000f,1:32,768 CONFIG2H~1~2=0x000f,0x000e,1:16,384 CONFIG2H~1~3=0x000f,0x000d,1:8,192 CONFIG2H~1~4=0x000f,0x000c,1:4,096 CONFIG2H~1~5=0x000f,0x000b,1:2,048 CONFIG2H~1~6=0x000f,0x000a,1:1,024 CONFIG2H~1~7=0x000f,0x0009,1:512 CONFIG2H~1~8=0x000f,0x0008,1:256 CONFIG2H~1~9=0x000f,0x0007,1:128 CONFIG2H~1~10=0x000f,0x0006,1:64 CONFIG2H~1~11=0x000f,0x0005,1:32 CONFIG2H~1~12=0x000f,0x0004,1:16 CONFIG2H~1~13=0x000f,0x0003,1:8 CONFIG2H~1~14=0x000f,0x0002,1:4 CONFIG2H~1~15=0x000f,0x0001,1:2 CONFIG2H~1~16=0x000f,0x0000,1:1 CONFIG3L_unused=0x00 CONFIG3H_unused=0x00 CONFIG3H~1=CCP2MX,0x01,CCP2 Mux CONFIG3H~2=ECCPXM,0x02,ECCP Mux CONFIG3H~1~1=0x01,0x01,ECCP2 I/O Muxed With RC1 CONFIG3H~1~2=0x01,0x00,ECCP2 IP Muxed With RE7 CONFIG3H~2~1=0x02,0x02,P1B/P1C On RE6/RE5, P3B/P3C On RE4/RE3 CONFIG3H~2~2=0x02,0x00,P1B/P1C On RH7/RH6, P3B/P3C Onto RH5/RH4 CONFIG4L_unused=0x00 CONFIG4H_unused=0x00 erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F67J93] pgmmem=0x0 ~pgmmem=0x1fff7 cfgmem=0x1fff8 ~cfgmem=0x1ffff userid= ~userid= eedata=0x00 ~eedata=0xf5f devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x5060 configslots=8 0x1fff8=CONFIG1L 0x1fff9=CONFIG1H 0x1fffa=CONFIG2L 0x1fffb=CONFIG2H 0x1fffc=CONFIG3L 0x1fffd=CONFIG3H 0x1fffe=CONFIG4L 0x1ffff=CONFIG4H CONFIG1L_unused=0x00 CONFIG1L~1=WDTEN,0x01,Watchdog Timer Enable CONFIG1L~2=STVREN,0x0E,PLL Configuration CONFIG1L~3=ENHCPU,0x20,Stack Overflow Reset CONFIG1L~4=EXTCPU,0x40,Extended CPU CONFIG1L~5=BACKBUG,0x80,Background Debug CONFIG1L~1~1=0x01,0x01,Enabled CONFIG1L~1~2=0x01,0x00,Disabled CONFIG1L~2~1=0x0E,0x0E,No Divide (4MHz input) CONFIG1L~2~2=0x0E,0x0C,Divide by 2 (8MHz input) CONFIG1L~2~3=0x0E,0x0A,Divide by 3 (12MHz input) CONFIG1L~2~4=0x0E,0x08,Divide by 4 (16MHz input) CONFIG1L~2~5=0x0E,0x06,Divide by 5 (20MHz input) CONFIG1L~2~6=0x0E,0x04,Divide by 6 (24MHz input) CONFIG1L~2~7=0x0E,0x02,Divide by 10 (40MHz input) CONFIG1L~2~8=0x0E,0x00,Divide by 12 (48MHz input) CONFIG1L~3~1=0x20,0x20,Enabled CONFIG1L~3~2=0x20,0x00,Disabled CONFIG1L~4~1=0x40,0x40,Enabled CONFIG1L~4~2=0x40,0x00,Disabled CONFIG1L~5~1=0x80,0x80,Disabled CONFIG1L~5~2=0x80,0x00,Enabled CONFIG1H_unused=0x00 CONFIG1H~1=CPDIV,0x3,CPU Clock Divider CONFIG1H~2=CP_0,0x4,Code Protection CONFIG1H~1~1=0x3,0x3,No divide CONFIG1H~1~2=0x3,0x2,Divide by 2 CONFIG1H~1~3=0x3,0x1,Divide by 3 CONFIG1H~1~4=0x3,0x0,Divide by 6 CONFIG1H~2~1=0x4,0x4,Disabled CONFIG1H~2~2=0x4,0x00,Enabled CONFIG2L_unused=0x00 CONFIG2L~1=FOSC,0x07,Oscillator CONFIG2L~2=FCMEN,0x40,Fail Safe Monitor Clock Enable CONFIG2L~3=IESO,0x80,Internal External Switch Over Enable CONFIG2L~1~1=0x07,0x07,EC+PLL(CLKO-RA6) USB-EC+PLL CONFIG2L~1~2=0x07,0x06,EC(CLKO-RA6) USB-EC CONFIG2L~1~3=0x07,0x05,HS+PLL USB-HS+PLL CONFIG2L~1~4=0x07,0x04,HS USB-HS CONFIG2L~1~5=0x07,0x03,INTOSC EC+PLL Osc with CLKOUT CONFIG2L~1~6=0x07,0x02,INTOSC EC Osc with CLKOUT CONFIG2L~1~7=0x07,0x01,INTOSC HS+PLL Osc CONFIG2L~1~8=0x07,0x00,INTOSC HS Osc CONFIG2L~2~1=0x40,0x40,Enabled CONFIG2L~2~2=0x40,0x00,Disabled CONFIG2L~3~1=0x80,0x80,Enabled CONFIG2L~3~2=0x80,0x00,Disabled CONFIG2H_unused=0x00 CONFIG2H~1=WDTPS,0x0f,Watchdog Timer Postscale CONFIG2H~1~1=0x000f,0x000f,1:32,768 CONFIG2H~1~2=0x000f,0x000e,1:16,384 CONFIG2H~1~3=0x000f,0x000d,1:8,192 CONFIG2H~1~4=0x000f,0x000c,1:4,096 CONFIG2H~1~5=0x000f,0x000b,1:2,048 CONFIG2H~1~6=0x000f,0x000a,1:1,024 CONFIG2H~1~7=0x000f,0x0009,1:512 CONFIG2H~1~8=0x000f,0x0008,1:256 CONFIG2H~1~9=0x000f,0x0007,1:128 CONFIG2H~1~10=0x000f,0x0006,1:64 CONFIG2H~1~11=0x000f,0x0005,1:32 CONFIG2H~1~12=0x000f,0x0004,1:16 CONFIG2H~1~13=0x000f,0x0003,1:8 CONFIG2H~1~14=0x000f,0x0002,1:4 CONFIG2H~1~15=0x000f,0x0001,1:2 CONFIG2H~1~16=0x000f,0x0000,1:1 CONFIG3L_unused=0x00 CONFIG3H_unused=0x00 CONFIG3H~1=CCP2MX,0x01,CCP2 Mux CONFIG3H~2=ECCPXM,0x02,ECCP Mux CONFIG3H~1~1=0x01,0x01,ECCP2 I/O Muxed With RC1 CONFIG3H~1~2=0x01,0x00,ECCP2 IP Muxed With RE7 CONFIG3H~2~1=0x02,0x02,P1B/P1C On RE6/RE5, P3B/P3C On RE4/RE3 CONFIG3H~2~2=0x02,0x00,P1B/P1C On RH7/RH6, P3B/P3C Onto RH5/RH4 CONFIG4L_unused=0x00 CONFIG4H_unused=0x00 erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F83J11] pgmmem=0x0 ~pgmmem=0x1fff7 cfgmem=0x1fff8 ~cfgmem=0x1ffff userid= ~userid= eedata=0x00 ~eedata=0xf5f devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x3980 configslots=8 0x1fff8=CONFIG1L 0x1fff9=CONFIG1H 0x1fffa=CONFIG2L 0x1fffb=CONFIG2H 0x1fffc=CONFIG3L 0x1fffd=CONFIG3H 0x1fffe=CONFIG4L 0x1ffff=CONFIG4H CONFIG1L_unused=0x00 CONFIG1L~1=WDTEN,0x01,Watchdog Timer Enable CONFIG1L~2=STVREN,0x0E,PLL Configuration CONFIG1L~3=ENHCPU,0x20,Stack Overflow Reset CONFIG1L~4=EXTCPU,0x40,Extended CPU CONFIG1L~5=BACKBUG,0x80,Background Debug CONFIG1L~1~1=0x01,0x01,Enabled CONFIG1L~1~2=0x01,0x00,Disabled CONFIG1L~2~1=0x0E,0x0E,No Divide (4MHz input) CONFIG1L~2~2=0x0E,0x0C,Divide by 2 (8MHz input) CONFIG1L~2~3=0x0E,0x0A,Divide by 3 (12MHz input) CONFIG1L~2~4=0x0E,0x08,Divide by 4 (16MHz input) CONFIG1L~2~5=0x0E,0x06,Divide by 5 (20MHz input) CONFIG1L~2~6=0x0E,0x04,Divide by 6 (24MHz input) CONFIG1L~2~7=0x0E,0x02,Divide by 10 (40MHz input) CONFIG1L~2~8=0x0E,0x00,Divide by 12 (48MHz input) CONFIG1L~3~1=0x20,0x20,Enabled CONFIG1L~3~2=0x20,0x00,Disabled CONFIG1L~4~1=0x40,0x40,Enabled CONFIG1L~4~2=0x40,0x00,Disabled CONFIG1L~5~1=0x80,0x80,Disabled CONFIG1L~5~2=0x80,0x00,Enabled CONFIG1H_unused=0x00 CONFIG1H~1=CPDIV,0x3,CPU Clock Divider CONFIG1H~2=CP_0,0x4,Code Protection CONFIG1H~1~1=0x3,0x3,No divide CONFIG1H~1~2=0x3,0x2,Divide by 2 CONFIG1H~1~3=0x3,0x1,Divide by 3 CONFIG1H~1~4=0x3,0x0,Divide by 6 CONFIG1H~2~1=0x4,0x4,Disabled CONFIG1H~2~2=0x4,0x00,Enabled CONFIG2L_unused=0x00 CONFIG2L~1=FOSC,0x07,Oscillator CONFIG2L~2=FCMEN,0x40,Fail Safe Monitor Clock Enable CONFIG2L~3=IESO,0x80,Internal External Switch Over Enable CONFIG2L~1~1=0x07,0x07,EC+PLL(CLKO-RA6) USB-EC+PLL CONFIG2L~1~2=0x07,0x06,EC(CLKO-RA6) USB-EC CONFIG2L~1~3=0x07,0x05,HS+PLL USB-HS+PLL CONFIG2L~1~4=0x07,0x04,HS USB-HS CONFIG2L~1~5=0x07,0x03,INTOSC EC+PLL Osc with CLKOUT CONFIG2L~1~6=0x07,0x02,INTOSC EC Osc with CLKOUT CONFIG2L~1~7=0x07,0x01,INTOSC HS+PLL Osc CONFIG2L~1~8=0x07,0x00,INTOSC HS Osc CONFIG2L~2~1=0x40,0x40,Enabled CONFIG2L~2~2=0x40,0x00,Disabled CONFIG2L~3~1=0x80,0x80,Enabled CONFIG2L~3~2=0x80,0x00,Disabled CONFIG2H_unused=0x00 CONFIG2H~1=WDTPS,0x0f,Watchdog Timer Postscale CONFIG2H~1~1=0x000f,0x000f,1:32,768 CONFIG2H~1~2=0x000f,0x000e,1:16,384 CONFIG2H~1~3=0x000f,0x000d,1:8,192 CONFIG2H~1~4=0x000f,0x000c,1:4,096 CONFIG2H~1~5=0x000f,0x000b,1:2,048 CONFIG2H~1~6=0x000f,0x000a,1:1,024 CONFIG2H~1~7=0x000f,0x0009,1:512 CONFIG2H~1~8=0x000f,0x0008,1:256 CONFIG2H~1~9=0x000f,0x0007,1:128 CONFIG2H~1~10=0x000f,0x0006,1:64 CONFIG2H~1~11=0x000f,0x0005,1:32 CONFIG2H~1~12=0x000f,0x0004,1:16 CONFIG2H~1~13=0x000f,0x0003,1:8 CONFIG2H~1~14=0x000f,0x0002,1:4 CONFIG2H~1~15=0x000f,0x0001,1:2 CONFIG2H~1~16=0x000f,0x0000,1:1 CONFIG3L_unused=0x00 CONFIG3H_unused=0x00 CONFIG3H~1=CCP2MX,0x01,CCP2 Mux CONFIG3H~2=ECCPXM,0x02,ECCP Mux CONFIG3H~1~1=0x01,0x01,ECCP2 I/O Muxed With RC1 CONFIG3H~1~2=0x01,0x00,ECCP2 IP Muxed With RE7 CONFIG3H~2~1=0x02,0x02,P1B/P1C On RE6/RE5, P3B/P3C On RE4/RE3 CONFIG3H~2~2=0x02,0x00,P1B/P1C On RH7/RH6, P3B/P3C Onto RH5/RH4 CONFIG4L_unused=0x00 CONFIG4H_unused=0x00 erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F83J90] pgmmem=0x0 ~pgmmem=0x1fff7 cfgmem=0x1fff8 ~cfgmem=0x1ffff userid= ~userid= eedata=0x00 ~eedata=0xf5f devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x3880 configslots=8 0x1fff8=CONFIG1L 0x1fff9=CONFIG1H 0x1fffa=CONFIG2L 0x1fffb=CONFIG2H 0x1fffc=CONFIG3L 0x1fffd=CONFIG3H 0x1fffe=CONFIG4L 0x1ffff=CONFIG4H CONFIG1L_unused=0x00 CONFIG1L~1=WDTEN,0x01,Watchdog Timer Enable CONFIG1L~2=STVREN,0x0E,PLL Configuration CONFIG1L~3=ENHCPU,0x20,Stack Overflow Reset CONFIG1L~4=EXTCPU,0x40,Extended CPU CONFIG1L~5=BACKBUG,0x80,Background Debug CONFIG1L~1~1=0x01,0x01,Enabled CONFIG1L~1~2=0x01,0x00,Disabled CONFIG1L~2~1=0x0E,0x0E,No Divide (4MHz input) CONFIG1L~2~2=0x0E,0x0C,Divide by 2 (8MHz input) CONFIG1L~2~3=0x0E,0x0A,Divide by 3 (12MHz input) CONFIG1L~2~4=0x0E,0x08,Divide by 4 (16MHz input) CONFIG1L~2~5=0x0E,0x06,Divide by 5 (20MHz input) CONFIG1L~2~6=0x0E,0x04,Divide by 6 (24MHz input) CONFIG1L~2~7=0x0E,0x02,Divide by 10 (40MHz input) CONFIG1L~2~8=0x0E,0x00,Divide by 12 (48MHz input) CONFIG1L~3~1=0x20,0x20,Enabled CONFIG1L~3~2=0x20,0x00,Disabled CONFIG1L~4~1=0x40,0x40,Enabled CONFIG1L~4~2=0x40,0x00,Disabled CONFIG1L~5~1=0x80,0x80,Disabled CONFIG1L~5~2=0x80,0x00,Enabled CONFIG1H_unused=0x00 CONFIG1H~1=CPDIV,0x3,CPU Clock Divider CONFIG1H~2=CP_0,0x4,Code Protection CONFIG1H~1~1=0x3,0x3,No divide CONFIG1H~1~2=0x3,0x2,Divide by 2 CONFIG1H~1~3=0x3,0x1,Divide by 3 CONFIG1H~1~4=0x3,0x0,Divide by 6 CONFIG1H~2~1=0x4,0x4,Disabled CONFIG1H~2~2=0x4,0x00,Enabled CONFIG2L_unused=0x00 CONFIG2L~1=FOSC,0x07,Oscillator CONFIG2L~2=FCMEN,0x40,Fail Safe Monitor Clock Enable CONFIG2L~3=IESO,0x80,Internal External Switch Over Enable CONFIG2L~1~1=0x07,0x07,EC+PLL(CLKO-RA6) USB-EC+PLL CONFIG2L~1~2=0x07,0x06,EC(CLKO-RA6) USB-EC CONFIG2L~1~3=0x07,0x05,HS+PLL USB-HS+PLL CONFIG2L~1~4=0x07,0x04,HS USB-HS CONFIG2L~1~5=0x07,0x03,INTOSC EC+PLL Osc with CLKOUT CONFIG2L~1~6=0x07,0x02,INTOSC EC Osc with CLKOUT CONFIG2L~1~7=0x07,0x01,INTOSC HS+PLL Osc CONFIG2L~1~8=0x07,0x00,INTOSC HS Osc CONFIG2L~2~1=0x40,0x40,Enabled CONFIG2L~2~2=0x40,0x00,Disabled CONFIG2L~3~1=0x80,0x80,Enabled CONFIG2L~3~2=0x80,0x00,Disabled CONFIG2H_unused=0x00 CONFIG2H~1=WDTPS,0x0f,Watchdog Timer Postscale CONFIG2H~1~1=0x000f,0x000f,1:32,768 CONFIG2H~1~2=0x000f,0x000e,1:16,384 CONFIG2H~1~3=0x000f,0x000d,1:8,192 CONFIG2H~1~4=0x000f,0x000c,1:4,096 CONFIG2H~1~5=0x000f,0x000b,1:2,048 CONFIG2H~1~6=0x000f,0x000a,1:1,024 CONFIG2H~1~7=0x000f,0x0009,1:512 CONFIG2H~1~8=0x000f,0x0008,1:256 CONFIG2H~1~9=0x000f,0x0007,1:128 CONFIG2H~1~10=0x000f,0x0006,1:64 CONFIG2H~1~11=0x000f,0x0005,1:32 CONFIG2H~1~12=0x000f,0x0004,1:16 CONFIG2H~1~13=0x000f,0x0003,1:8 CONFIG2H~1~14=0x000f,0x0002,1:4 CONFIG2H~1~15=0x000f,0x0001,1:2 CONFIG2H~1~16=0x000f,0x0000,1:1 CONFIG3L_unused=0x00 CONFIG3H_unused=0x00 CONFIG3H~1=CCP2MX,0x01,CCP2 Mux CONFIG3H~2=ECCPXM,0x02,ECCP Mux CONFIG3H~1~1=0x01,0x01,ECCP2 I/O Muxed With RC1 CONFIG3H~1~2=0x01,0x00,ECCP2 IP Muxed With RE7 CONFIG3H~2~1=0x02,0x02,P1B/P1C On RE6/RE5, P3B/P3C On RE4/RE3 CONFIG3H~2~2=0x02,0x00,P1B/P1C On RH7/RH6, P3B/P3C Onto RH5/RH4 CONFIG4L_unused=0x00 CONFIG4H_unused=0x00 erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F84J11] pgmmem=0x0 ~pgmmem=0x1fff7 cfgmem=0x1fff8 ~cfgmem=0x1ffff userid= ~userid= eedata=0x00 ~eedata=0xf5f devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x39A0 configslots=8 0x1fff8=CONFIG1L 0x1fff9=CONFIG1H 0x1fffa=CONFIG2L 0x1fffb=CONFIG2H 0x1fffc=CONFIG3L 0x1fffd=CONFIG3H 0x1fffe=CONFIG4L 0x1ffff=CONFIG4H CONFIG1L_unused=0x00 CONFIG1L~1=WDTEN,0x01,Watchdog Timer Enable CONFIG1L~2=STVREN,0x0E,PLL Configuration CONFIG1L~3=ENHCPU,0x20,Stack Overflow Reset CONFIG1L~4=EXTCPU,0x40,Extended CPU CONFIG1L~5=BACKBUG,0x80,Background Debug CONFIG1L~1~1=0x01,0x01,Enabled CONFIG1L~1~2=0x01,0x00,Disabled CONFIG1L~2~1=0x0E,0x0E,No Divide (4MHz input) CONFIG1L~2~2=0x0E,0x0C,Divide by 2 (8MHz input) CONFIG1L~2~3=0x0E,0x0A,Divide by 3 (12MHz input) CONFIG1L~2~4=0x0E,0x08,Divide by 4 (16MHz input) CONFIG1L~2~5=0x0E,0x06,Divide by 5 (20MHz input) CONFIG1L~2~6=0x0E,0x04,Divide by 6 (24MHz input) CONFIG1L~2~7=0x0E,0x02,Divide by 10 (40MHz input) CONFIG1L~2~8=0x0E,0x00,Divide by 12 (48MHz input) CONFIG1L~3~1=0x20,0x20,Enabled CONFIG1L~3~2=0x20,0x00,Disabled CONFIG1L~4~1=0x40,0x40,Enabled CONFIG1L~4~2=0x40,0x00,Disabled CONFIG1L~5~1=0x80,0x80,Disabled CONFIG1L~5~2=0x80,0x00,Enabled CONFIG1H_unused=0x00 CONFIG1H~1=CPDIV,0x3,CPU Clock Divider CONFIG1H~2=CP_0,0x4,Code Protection CONFIG1H~1~1=0x3,0x3,No divide CONFIG1H~1~2=0x3,0x2,Divide by 2 CONFIG1H~1~3=0x3,0x1,Divide by 3 CONFIG1H~1~4=0x3,0x0,Divide by 6 CONFIG1H~2~1=0x4,0x4,Disabled CONFIG1H~2~2=0x4,0x00,Enabled CONFIG2L_unused=0x00 CONFIG2L~1=FOSC,0x07,Oscillator CONFIG2L~2=FCMEN,0x40,Fail Safe Monitor Clock Enable CONFIG2L~3=IESO,0x80,Internal External Switch Over Enable CONFIG2L~1~1=0x07,0x07,EC+PLL(CLKO-RA6) USB-EC+PLL CONFIG2L~1~2=0x07,0x06,EC(CLKO-RA6) USB-EC CONFIG2L~1~3=0x07,0x05,HS+PLL USB-HS+PLL CONFIG2L~1~4=0x07,0x04,HS USB-HS CONFIG2L~1~5=0x07,0x03,INTOSC EC+PLL Osc with CLKOUT CONFIG2L~1~6=0x07,0x02,INTOSC EC Osc with CLKOUT CONFIG2L~1~7=0x07,0x01,INTOSC HS+PLL Osc CONFIG2L~1~8=0x07,0x00,INTOSC HS Osc CONFIG2L~2~1=0x40,0x40,Enabled CONFIG2L~2~2=0x40,0x00,Disabled CONFIG2L~3~1=0x80,0x80,Enabled CONFIG2L~3~2=0x80,0x00,Disabled CONFIG2H_unused=0x00 CONFIG2H~1=WDTPS,0x0f,Watchdog Timer Postscale CONFIG2H~1~1=0x000f,0x000f,1:32,768 CONFIG2H~1~2=0x000f,0x000e,1:16,384 CONFIG2H~1~3=0x000f,0x000d,1:8,192 CONFIG2H~1~4=0x000f,0x000c,1:4,096 CONFIG2H~1~5=0x000f,0x000b,1:2,048 CONFIG2H~1~6=0x000f,0x000a,1:1,024 CONFIG2H~1~7=0x000f,0x0009,1:512 CONFIG2H~1~8=0x000f,0x0008,1:256 CONFIG2H~1~9=0x000f,0x0007,1:128 CONFIG2H~1~10=0x000f,0x0006,1:64 CONFIG2H~1~11=0x000f,0x0005,1:32 CONFIG2H~1~12=0x000f,0x0004,1:16 CONFIG2H~1~13=0x000f,0x0003,1:8 CONFIG2H~1~14=0x000f,0x0002,1:4 CONFIG2H~1~15=0x000f,0x0001,1:2 CONFIG2H~1~16=0x000f,0x0000,1:1 CONFIG3L_unused=0x00 CONFIG3H_unused=0x00 CONFIG3H~1=CCP2MX,0x01,CCP2 Mux CONFIG3H~2=ECCPXM,0x02,ECCP Mux CONFIG3H~1~1=0x01,0x01,ECCP2 I/O Muxed With RC1 CONFIG3H~1~2=0x01,0x00,ECCP2 IP Muxed With RE7 CONFIG3H~2~1=0x02,0x02,P1B/P1C On RE6/RE5, P3B/P3C On RE4/RE3 CONFIG3H~2~2=0x02,0x00,P1B/P1C On RH7/RH6, P3B/P3C Onto RH5/RH4 CONFIG4L_unused=0x00 CONFIG4H_unused=0x00 erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F84J90] pgmmem=0x0 ~pgmmem=0x1fff7 cfgmem=0x1fff8 ~cfgmem=0x1ffff userid= ~userid= eedata=0x00 ~eedata=0xf5f devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x38A0 configslots=8 0x1fff8=CONFIG1L 0x1fff9=CONFIG1H 0x1fffa=CONFIG2L 0x1fffb=CONFIG2H 0x1fffc=CONFIG3L 0x1fffd=CONFIG3H 0x1fffe=CONFIG4L 0x1ffff=CONFIG4H CONFIG1L_unused=0x00 CONFIG1L~1=WDTEN,0x01,Watchdog Timer Enable CONFIG1L~2=STVREN,0x0E,PLL Configuration CONFIG1L~3=ENHCPU,0x20,Stack Overflow Reset CONFIG1L~4=EXTCPU,0x40,Extended CPU CONFIG1L~5=BACKBUG,0x80,Background Debug CONFIG1L~1~1=0x01,0x01,Enabled CONFIG1L~1~2=0x01,0x00,Disabled CONFIG1L~2~1=0x0E,0x0E,No Divide (4MHz input) CONFIG1L~2~2=0x0E,0x0C,Divide by 2 (8MHz input) CONFIG1L~2~3=0x0E,0x0A,Divide by 3 (12MHz input) CONFIG1L~2~4=0x0E,0x08,Divide by 4 (16MHz input) CONFIG1L~2~5=0x0E,0x06,Divide by 5 (20MHz input) CONFIG1L~2~6=0x0E,0x04,Divide by 6 (24MHz input) CONFIG1L~2~7=0x0E,0x02,Divide by 10 (40MHz input) CONFIG1L~2~8=0x0E,0x00,Divide by 12 (48MHz input) CONFIG1L~3~1=0x20,0x20,Enabled CONFIG1L~3~2=0x20,0x00,Disabled CONFIG1L~4~1=0x40,0x40,Enabled CONFIG1L~4~2=0x40,0x00,Disabled CONFIG1L~5~1=0x80,0x80,Disabled CONFIG1L~5~2=0x80,0x00,Enabled CONFIG1H_unused=0x00 CONFIG1H~1=CPDIV,0x3,CPU Clock Divider CONFIG1H~2=CP_0,0x4,Code Protection CONFIG1H~1~1=0x3,0x3,No divide CONFIG1H~1~2=0x3,0x2,Divide by 2 CONFIG1H~1~3=0x3,0x1,Divide by 3 CONFIG1H~1~4=0x3,0x0,Divide by 6 CONFIG1H~2~1=0x4,0x4,Disabled CONFIG1H~2~2=0x4,0x00,Enabled CONFIG2L_unused=0x00 CONFIG2L~1=FOSC,0x07,Oscillator CONFIG2L~2=FCMEN,0x40,Fail Safe Monitor Clock Enable CONFIG2L~3=IESO,0x80,Internal External Switch Over Enable CONFIG2L~1~1=0x07,0x07,EC+PLL(CLKO-RA6) USB-EC+PLL CONFIG2L~1~2=0x07,0x06,EC(CLKO-RA6) USB-EC CONFIG2L~1~3=0x07,0x05,HS+PLL USB-HS+PLL CONFIG2L~1~4=0x07,0x04,HS USB-HS CONFIG2L~1~5=0x07,0x03,INTOSC EC+PLL Osc with CLKOUT CONFIG2L~1~6=0x07,0x02,INTOSC EC Osc with CLKOUT CONFIG2L~1~7=0x07,0x01,INTOSC HS+PLL Osc CONFIG2L~1~8=0x07,0x00,INTOSC HS Osc CONFIG2L~2~1=0x40,0x40,Enabled CONFIG2L~2~2=0x40,0x00,Disabled CONFIG2L~3~1=0x80,0x80,Enabled CONFIG2L~3~2=0x80,0x00,Disabled CONFIG2H_unused=0x00 CONFIG2H~1=WDTPS,0x0f,Watchdog Timer Postscale CONFIG2H~1~1=0x000f,0x000f,1:32,768 CONFIG2H~1~2=0x000f,0x000e,1:16,384 CONFIG2H~1~3=0x000f,0x000d,1:8,192 CONFIG2H~1~4=0x000f,0x000c,1:4,096 CONFIG2H~1~5=0x000f,0x000b,1:2,048 CONFIG2H~1~6=0x000f,0x000a,1:1,024 CONFIG2H~1~7=0x000f,0x0009,1:512 CONFIG2H~1~8=0x000f,0x0008,1:256 CONFIG2H~1~9=0x000f,0x0007,1:128 CONFIG2H~1~10=0x000f,0x0006,1:64 CONFIG2H~1~11=0x000f,0x0005,1:32 CONFIG2H~1~12=0x000f,0x0004,1:16 CONFIG2H~1~13=0x000f,0x0003,1:8 CONFIG2H~1~14=0x000f,0x0002,1:4 CONFIG2H~1~15=0x000f,0x0001,1:2 CONFIG2H~1~16=0x000f,0x0000,1:1 CONFIG3L_unused=0x00 CONFIG3H_unused=0x00 CONFIG3H~1=CCP2MX,0x01,CCP2 Mux CONFIG3H~2=ECCPXM,0x02,ECCP Mux CONFIG3H~1~1=0x01,0x01,ECCP2 I/O Muxed With RC1 CONFIG3H~1~2=0x01,0x00,ECCP2 IP Muxed With RE7 CONFIG3H~2~1=0x02,0x02,P1B/P1C On RE6/RE5, P3B/P3C On RE4/RE3 CONFIG3H~2~2=0x02,0x00,P1B/P1C On RH7/RH6, P3B/P3C Onto RH5/RH4 CONFIG4L_unused=0x00 CONFIG4H_unused=0x00 erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F85J10] pgmmem=0x0 ~pgmmem=0x1fff7 cfgmem=0x1fff8 ~cfgmem=0x1ffff userid= ~userid= eedata=0x00 ~eedata=0xf5f devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x15E0 configslots=8 0x1fff8=CONFIG1L 0x1fff9=CONFIG1H 0x1fffa=CONFIG2L 0x1fffb=CONFIG2H 0x1fffc=CONFIG3L 0x1fffd=CONFIG3H 0x1fffe=CONFIG4L 0x1ffff=CONFIG4H CONFIG1L_unused=0x00 CONFIG1L~1=WDTEN,0x01,Watchdog Timer Enable CONFIG1L~2=STVREN,0x0E,PLL Configuration CONFIG1L~3=ENHCPU,0x20,Stack Overflow Reset CONFIG1L~4=EXTCPU,0x40,Extended CPU CONFIG1L~5=BACKBUG,0x80,Background Debug CONFIG1L~1~1=0x01,0x01,Enabled CONFIG1L~1~2=0x01,0x00,Disabled CONFIG1L~2~1=0x0E,0x0E,No Divide (4MHz input) CONFIG1L~2~2=0x0E,0x0C,Divide by 2 (8MHz input) CONFIG1L~2~3=0x0E,0x0A,Divide by 3 (12MHz input) CONFIG1L~2~4=0x0E,0x08,Divide by 4 (16MHz input) CONFIG1L~2~5=0x0E,0x06,Divide by 5 (20MHz input) CONFIG1L~2~6=0x0E,0x04,Divide by 6 (24MHz input) CONFIG1L~2~7=0x0E,0x02,Divide by 10 (40MHz input) CONFIG1L~2~8=0x0E,0x00,Divide by 12 (48MHz input) CONFIG1L~3~1=0x20,0x20,Enabled CONFIG1L~3~2=0x20,0x00,Disabled CONFIG1L~4~1=0x40,0x40,Enabled CONFIG1L~4~2=0x40,0x00,Disabled CONFIG1L~5~1=0x80,0x80,Disabled CONFIG1L~5~2=0x80,0x00,Enabled CONFIG1H_unused=0x00 CONFIG1H~1=CPDIV,0x3,CPU Clock Divider CONFIG1H~2=CP_0,0x4,Code Protection CONFIG1H~1~1=0x3,0x3,No divide CONFIG1H~1~2=0x3,0x2,Divide by 2 CONFIG1H~1~3=0x3,0x1,Divide by 3 CONFIG1H~1~4=0x3,0x0,Divide by 6 CONFIG1H~2~1=0x4,0x4,Disabled CONFIG1H~2~2=0x4,0x00,Enabled CONFIG2L_unused=0x00 CONFIG2L~1=FOSC,0x07,Oscillator CONFIG2L~2=FCMEN,0x40,Fail Safe Monitor Clock Enable CONFIG2L~3=IESO,0x80,Internal External Switch Over Enable CONFIG2L~1~1=0x07,0x07,EC+PLL(CLKO-RA6) USB-EC+PLL CONFIG2L~1~2=0x07,0x06,EC(CLKO-RA6) USB-EC CONFIG2L~1~3=0x07,0x05,HS+PLL USB-HS+PLL CONFIG2L~1~4=0x07,0x04,HS USB-HS CONFIG2L~1~5=0x07,0x03,INTOSC EC+PLL Osc with CLKOUT CONFIG2L~1~6=0x07,0x02,INTOSC EC Osc with CLKOUT CONFIG2L~1~7=0x07,0x01,INTOSC HS+PLL Osc CONFIG2L~1~8=0x07,0x00,INTOSC HS Osc CONFIG2L~2~1=0x40,0x40,Enabled CONFIG2L~2~2=0x40,0x00,Disabled CONFIG2L~3~1=0x80,0x80,Enabled CONFIG2L~3~2=0x80,0x00,Disabled CONFIG2H_unused=0x00 CONFIG2H~1=WDTPS,0x0f,Watchdog Timer Postscale CONFIG2H~1~1=0x000f,0x000f,1:32,768 CONFIG2H~1~2=0x000f,0x000e,1:16,384 CONFIG2H~1~3=0x000f,0x000d,1:8,192 CONFIG2H~1~4=0x000f,0x000c,1:4,096 CONFIG2H~1~5=0x000f,0x000b,1:2,048 CONFIG2H~1~6=0x000f,0x000a,1:1,024 CONFIG2H~1~7=0x000f,0x0009,1:512 CONFIG2H~1~8=0x000f,0x0008,1:256 CONFIG2H~1~9=0x000f,0x0007,1:128 CONFIG2H~1~10=0x000f,0x0006,1:64 CONFIG2H~1~11=0x000f,0x0005,1:32 CONFIG2H~1~12=0x000f,0x0004,1:16 CONFIG2H~1~13=0x000f,0x0003,1:8 CONFIG2H~1~14=0x000f,0x0002,1:4 CONFIG2H~1~15=0x000f,0x0001,1:2 CONFIG2H~1~16=0x000f,0x0000,1:1 CONFIG3L_unused=0x00 CONFIG3H_unused=0x00 CONFIG3H~1=CCP2MX,0x01,CCP2 Mux CONFIG3H~2=ECCPXM,0x02,ECCP Mux CONFIG3H~1~1=0x01,0x01,ECCP2 I/O Muxed With RC1 CONFIG3H~1~2=0x01,0x00,ECCP2 IP Muxed With RE7 CONFIG3H~2~1=0x02,0x02,P1B/P1C On RE6/RE5, P3B/P3C On RE4/RE3 CONFIG3H~2~2=0x02,0x00,P1B/P1C On RH7/RH6, P3B/P3C Onto RH5/RH4 CONFIG4L_unused=0x00 CONFIG4H_unused=0x00 erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F85J11] pgmmem=0x0 ~pgmmem=0x1fff7 cfgmem=0x1fff8 ~cfgmem=0x1ffff userid= ~userid= eedata=0x00 ~eedata=0xf5f devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x39E0 configslots=8 0x1fff8=CONFIG1L 0x1fff9=CONFIG1H 0x1fffa=CONFIG2L 0x1fffb=CONFIG2H 0x1fffc=CONFIG3L 0x1fffd=CONFIG3H 0x1fffe=CONFIG4L 0x1ffff=CONFIG4H CONFIG1L_unused=0x00 CONFIG1L~1=WDTEN,0x01,Watchdog Timer Enable CONFIG1L~2=STVREN,0x0E,PLL Configuration CONFIG1L~3=ENHCPU,0x20,Stack Overflow Reset CONFIG1L~4=EXTCPU,0x40,Extended CPU CONFIG1L~5=BACKBUG,0x80,Background Debug CONFIG1L~1~1=0x01,0x01,Enabled CONFIG1L~1~2=0x01,0x00,Disabled CONFIG1L~2~1=0x0E,0x0E,No Divide (4MHz input) CONFIG1L~2~2=0x0E,0x0C,Divide by 2 (8MHz input) CONFIG1L~2~3=0x0E,0x0A,Divide by 3 (12MHz input) CONFIG1L~2~4=0x0E,0x08,Divide by 4 (16MHz input) CONFIG1L~2~5=0x0E,0x06,Divide by 5 (20MHz input) CONFIG1L~2~6=0x0E,0x04,Divide by 6 (24MHz input) CONFIG1L~2~7=0x0E,0x02,Divide by 10 (40MHz input) CONFIG1L~2~8=0x0E,0x00,Divide by 12 (48MHz input) CONFIG1L~3~1=0x20,0x20,Enabled CONFIG1L~3~2=0x20,0x00,Disabled CONFIG1L~4~1=0x40,0x40,Enabled CONFIG1L~4~2=0x40,0x00,Disabled CONFIG1L~5~1=0x80,0x80,Disabled CONFIG1L~5~2=0x80,0x00,Enabled CONFIG1H_unused=0x00 CONFIG1H~1=CPDIV,0x3,CPU Clock Divider CONFIG1H~2=CP_0,0x4,Code Protection CONFIG1H~1~1=0x3,0x3,No divide CONFIG1H~1~2=0x3,0x2,Divide by 2 CONFIG1H~1~3=0x3,0x1,Divide by 3 CONFIG1H~1~4=0x3,0x0,Divide by 6 CONFIG1H~2~1=0x4,0x4,Disabled CONFIG1H~2~2=0x4,0x00,Enabled CONFIG2L_unused=0x00 CONFIG2L~1=FOSC,0x07,Oscillator CONFIG2L~2=FCMEN,0x40,Fail Safe Monitor Clock Enable CONFIG2L~3=IESO,0x80,Internal External Switch Over Enable CONFIG2L~1~1=0x07,0x07,EC+PLL(CLKO-RA6) USB-EC+PLL CONFIG2L~1~2=0x07,0x06,EC(CLKO-RA6) USB-EC CONFIG2L~1~3=0x07,0x05,HS+PLL USB-HS+PLL CONFIG2L~1~4=0x07,0x04,HS USB-HS CONFIG2L~1~5=0x07,0x03,INTOSC EC+PLL Osc with CLKOUT CONFIG2L~1~6=0x07,0x02,INTOSC EC Osc with CLKOUT CONFIG2L~1~7=0x07,0x01,INTOSC HS+PLL Osc CONFIG2L~1~8=0x07,0x00,INTOSC HS Osc CONFIG2L~2~1=0x40,0x40,Enabled CONFIG2L~2~2=0x40,0x00,Disabled CONFIG2L~3~1=0x80,0x80,Enabled CONFIG2L~3~2=0x80,0x00,Disabled CONFIG2H_unused=0x00 CONFIG2H~1=WDTPS,0x0f,Watchdog Timer Postscale CONFIG2H~1~1=0x000f,0x000f,1:32,768 CONFIG2H~1~2=0x000f,0x000e,1:16,384 CONFIG2H~1~3=0x000f,0x000d,1:8,192 CONFIG2H~1~4=0x000f,0x000c,1:4,096 CONFIG2H~1~5=0x000f,0x000b,1:2,048 CONFIG2H~1~6=0x000f,0x000a,1:1,024 CONFIG2H~1~7=0x000f,0x0009,1:512 CONFIG2H~1~8=0x000f,0x0008,1:256 CONFIG2H~1~9=0x000f,0x0007,1:128 CONFIG2H~1~10=0x000f,0x0006,1:64 CONFIG2H~1~11=0x000f,0x0005,1:32 CONFIG2H~1~12=0x000f,0x0004,1:16 CONFIG2H~1~13=0x000f,0x0003,1:8 CONFIG2H~1~14=0x000f,0x0002,1:4 CONFIG2H~1~15=0x000f,0x0001,1:2 CONFIG2H~1~16=0x000f,0x0000,1:1 CONFIG3L_unused=0x00 CONFIG3H_unused=0x00 CONFIG3H~1=CCP2MX,0x01,CCP2 Mux CONFIG3H~2=ECCPXM,0x02,ECCP Mux CONFIG3H~1~1=0x01,0x01,ECCP2 I/O Muxed With RC1 CONFIG3H~1~2=0x01,0x00,ECCP2 IP Muxed With RE7 CONFIG3H~2~1=0x02,0x02,P1B/P1C On RE6/RE5, P3B/P3C On RE4/RE3 CONFIG3H~2~2=0x02,0x00,P1B/P1C On RH7/RH6, P3B/P3C Onto RH5/RH4 CONFIG4L_unused=0x00 CONFIG4H_unused=0x00 erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F85J15] pgmmem=0x0 ~pgmmem=0x1fff7 cfgmem=0x1fff8 ~cfgmem=0x1ffff userid= ~userid= eedata=0x00 ~eedata=0xf5f devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x1700 configslots=8 0x1fff8=CONFIG1L 0x1fff9=CONFIG1H 0x1fffa=CONFIG2L 0x1fffb=CONFIG2H 0x1fffc=CONFIG3L 0x1fffd=CONFIG3H 0x1fffe=CONFIG4L 0x1ffff=CONFIG4H CONFIG1L_unused=0x00 CONFIG1L~1=WDTEN,0x01,Watchdog Timer Enable CONFIG1L~2=STVREN,0x0E,PLL Configuration CONFIG1L~3=ENHCPU,0x20,Stack Overflow Reset CONFIG1L~4=EXTCPU,0x40,Extended CPU CONFIG1L~5=BACKBUG,0x80,Background Debug CONFIG1L~1~1=0x01,0x01,Enabled CONFIG1L~1~2=0x01,0x00,Disabled CONFIG1L~2~1=0x0E,0x0E,No Divide (4MHz input) CONFIG1L~2~2=0x0E,0x0C,Divide by 2 (8MHz input) CONFIG1L~2~3=0x0E,0x0A,Divide by 3 (12MHz input) CONFIG1L~2~4=0x0E,0x08,Divide by 4 (16MHz input) CONFIG1L~2~5=0x0E,0x06,Divide by 5 (20MHz input) CONFIG1L~2~6=0x0E,0x04,Divide by 6 (24MHz input) CONFIG1L~2~7=0x0E,0x02,Divide by 10 (40MHz input) CONFIG1L~2~8=0x0E,0x00,Divide by 12 (48MHz input) CONFIG1L~3~1=0x20,0x20,Enabled CONFIG1L~3~2=0x20,0x00,Disabled CONFIG1L~4~1=0x40,0x40,Enabled CONFIG1L~4~2=0x40,0x00,Disabled CONFIG1L~5~1=0x80,0x80,Disabled CONFIG1L~5~2=0x80,0x00,Enabled CONFIG1H_unused=0x00 CONFIG1H~1=CPDIV,0x3,CPU Clock Divider CONFIG1H~2=CP_0,0x4,Code Protection CONFIG1H~1~1=0x3,0x3,No divide CONFIG1H~1~2=0x3,0x2,Divide by 2 CONFIG1H~1~3=0x3,0x1,Divide by 3 CONFIG1H~1~4=0x3,0x0,Divide by 6 CONFIG1H~2~1=0x4,0x4,Disabled CONFIG1H~2~2=0x4,0x00,Enabled CONFIG2L_unused=0x00 CONFIG2L~1=FOSC,0x07,Oscillator CONFIG2L~2=FCMEN,0x40,Fail Safe Monitor Clock Enable CONFIG2L~3=IESO,0x80,Internal External Switch Over Enable CONFIG2L~1~1=0x07,0x07,EC+PLL(CLKO-RA6) USB-EC+PLL CONFIG2L~1~2=0x07,0x06,EC(CLKO-RA6) USB-EC CONFIG2L~1~3=0x07,0x05,HS+PLL USB-HS+PLL CONFIG2L~1~4=0x07,0x04,HS USB-HS CONFIG2L~1~5=0x07,0x03,INTOSC EC+PLL Osc with CLKOUT CONFIG2L~1~6=0x07,0x02,INTOSC EC Osc with CLKOUT CONFIG2L~1~7=0x07,0x01,INTOSC HS+PLL Osc CONFIG2L~1~8=0x07,0x00,INTOSC HS Osc CONFIG2L~2~1=0x40,0x40,Enabled CONFIG2L~2~2=0x40,0x00,Disabled CONFIG2L~3~1=0x80,0x80,Enabled CONFIG2L~3~2=0x80,0x00,Disabled CONFIG2H_unused=0x00 CONFIG2H~1=WDTPS,0x0f,Watchdog Timer Postscale CONFIG2H~1~1=0x000f,0x000f,1:32,768 CONFIG2H~1~2=0x000f,0x000e,1:16,384 CONFIG2H~1~3=0x000f,0x000d,1:8,192 CONFIG2H~1~4=0x000f,0x000c,1:4,096 CONFIG2H~1~5=0x000f,0x000b,1:2,048 CONFIG2H~1~6=0x000f,0x000a,1:1,024 CONFIG2H~1~7=0x000f,0x0009,1:512 CONFIG2H~1~8=0x000f,0x0008,1:256 CONFIG2H~1~9=0x000f,0x0007,1:128 CONFIG2H~1~10=0x000f,0x0006,1:64 CONFIG2H~1~11=0x000f,0x0005,1:32 CONFIG2H~1~12=0x000f,0x0004,1:16 CONFIG2H~1~13=0x000f,0x0003,1:8 CONFIG2H~1~14=0x000f,0x0002,1:4 CONFIG2H~1~15=0x000f,0x0001,1:2 CONFIG2H~1~16=0x000f,0x0000,1:1 CONFIG3L_unused=0x00 CONFIG3H_unused=0x00 CONFIG3H~1=CCP2MX,0x01,CCP2 Mux CONFIG3H~2=ECCPXM,0x02,ECCP Mux CONFIG3H~1~1=0x01,0x01,ECCP2 I/O Muxed With RC1 CONFIG3H~1~2=0x01,0x00,ECCP2 IP Muxed With RE7 CONFIG3H~2~1=0x02,0x02,P1B/P1C On RE6/RE5, P3B/P3C On RE4/RE3 CONFIG3H~2~2=0x02,0x00,P1B/P1C On RH7/RH6, P3B/P3C Onto RH5/RH4 CONFIG4L_unused=0x00 CONFIG4H_unused=0x00 erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F85J50] pgmmem=0x0 ~pgmmem=0x1fff7 cfgmem=0x1fff8 ~cfgmem=0x1ffff userid= ~userid= eedata=0x00 ~eedata=0xf5f devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x41A0 configslots=8 0x1fff8=CONFIG1L 0x1fff9=CONFIG1H 0x1fffa=CONFIG2L 0x1fffb=CONFIG2H 0x1fffc=CONFIG3L 0x1fffd=CONFIG3H 0x1fffe=CONFIG4L 0x1ffff=CONFIG4H CONFIG1L_unused=0x00 CONFIG1L~1=WDTEN,0x01,Watchdog Timer Enable CONFIG1L~2=STVREN,0x0E,PLL Configuration CONFIG1L~3=ENHCPU,0x20,Stack Overflow Reset CONFIG1L~4=EXTCPU,0x40,Extended CPU CONFIG1L~5=BACKBUG,0x80,Background Debug CONFIG1L~1~1=0x01,0x01,Enabled CONFIG1L~1~2=0x01,0x00,Disabled CONFIG1L~2~1=0x0E,0x0E,No Divide (4MHz input) CONFIG1L~2~2=0x0E,0x0C,Divide by 2 (8MHz input) CONFIG1L~2~3=0x0E,0x0A,Divide by 3 (12MHz input) CONFIG1L~2~4=0x0E,0x08,Divide by 4 (16MHz input) CONFIG1L~2~5=0x0E,0x06,Divide by 5 (20MHz input) CONFIG1L~2~6=0x0E,0x04,Divide by 6 (24MHz input) CONFIG1L~2~7=0x0E,0x02,Divide by 10 (40MHz input) CONFIG1L~2~8=0x0E,0x00,Divide by 12 (48MHz input) CONFIG1L~3~1=0x20,0x20,Enabled CONFIG1L~3~2=0x20,0x00,Disabled CONFIG1L~4~1=0x40,0x40,Enabled CONFIG1L~4~2=0x40,0x00,Disabled CONFIG1L~5~1=0x80,0x80,Disabled CONFIG1L~5~2=0x80,0x00,Enabled CONFIG1H_unused=0x00 CONFIG1H~1=CPDIV,0x3,CPU Clock Divider CONFIG1H~2=CP_0,0x4,Code Protection CONFIG1H~1~1=0x3,0x3,No divide CONFIG1H~1~2=0x3,0x2,Divide by 2 CONFIG1H~1~3=0x3,0x1,Divide by 3 CONFIG1H~1~4=0x3,0x0,Divide by 6 CONFIG1H~2~1=0x4,0x4,Disabled CONFIG1H~2~2=0x4,0x00,Enabled CONFIG2L_unused=0x00 CONFIG2L~1=FOSC,0x07,Oscillator CONFIG2L~2=FCMEN,0x40,Fail Safe Monitor Clock Enable CONFIG2L~3=IESO,0x80,Internal External Switch Over Enable CONFIG2L~1~1=0x07,0x07,EC+PLL(CLKO-RA6) USB-EC+PLL CONFIG2L~1~2=0x07,0x06,EC(CLKO-RA6) USB-EC CONFIG2L~1~3=0x07,0x05,HS+PLL USB-HS+PLL CONFIG2L~1~4=0x07,0x04,HS USB-HS CONFIG2L~1~5=0x07,0x03,INTOSC EC+PLL Osc with CLKOUT CONFIG2L~1~6=0x07,0x02,INTOSC EC Osc with CLKOUT CONFIG2L~1~7=0x07,0x01,INTOSC HS+PLL Osc CONFIG2L~1~8=0x07,0x00,INTOSC HS Osc CONFIG2L~2~1=0x40,0x40,Enabled CONFIG2L~2~2=0x40,0x00,Disabled CONFIG2L~3~1=0x80,0x80,Enabled CONFIG2L~3~2=0x80,0x00,Disabled CONFIG2H_unused=0x00 CONFIG2H~1=WDTPS,0x0f,Watchdog Timer Postscale CONFIG2H~1~1=0x000f,0x000f,1:32,768 CONFIG2H~1~2=0x000f,0x000e,1:16,384 CONFIG2H~1~3=0x000f,0x000d,1:8,192 CONFIG2H~1~4=0x000f,0x000c,1:4,096 CONFIG2H~1~5=0x000f,0x000b,1:2,048 CONFIG2H~1~6=0x000f,0x000a,1:1,024 CONFIG2H~1~7=0x000f,0x0009,1:512 CONFIG2H~1~8=0x000f,0x0008,1:256 CONFIG2H~1~9=0x000f,0x0007,1:128 CONFIG2H~1~10=0x000f,0x0006,1:64 CONFIG2H~1~11=0x000f,0x0005,1:32 CONFIG2H~1~12=0x000f,0x0004,1:16 CONFIG2H~1~13=0x000f,0x0003,1:8 CONFIG2H~1~14=0x000f,0x0002,1:4 CONFIG2H~1~15=0x000f,0x0001,1:2 CONFIG2H~1~16=0x000f,0x0000,1:1 CONFIG3L_unused=0x00 CONFIG3H_unused=0x00 CONFIG3H~1=CCP2MX,0x01,CCP2 Mux CONFIG3H~2=ECCPXM,0x02,ECCP Mux CONFIG3H~1~1=0x01,0x01,ECCP2 I/O Muxed With RC1 CONFIG3H~1~2=0x01,0x00,ECCP2 IP Muxed With RE7 CONFIG3H~2~1=0x02,0x02,P1B/P1C On RE6/RE5, P3B/P3C On RE4/RE3 CONFIG3H~2~2=0x02,0x00,P1B/P1C On RH7/RH6, P3B/P3C Onto RH5/RH4 CONFIG4L_unused=0x00 CONFIG4H_unused=0x00 erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F85J90] pgmmem=0x0 ~pgmmem=0x1fff7 cfgmem=0x1fff8 ~cfgmem=0x1ffff userid= ~userid= eedata=0x00 ~eedata=0xf5f devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x38E0 configslots=8 0x1fff8=CONFIG1L 0x1fff9=CONFIG1H 0x1fffa=CONFIG2L 0x1fffb=CONFIG2H 0x1fffc=CONFIG3L 0x1fffd=CONFIG3H 0x1fffe=CONFIG4L 0x1ffff=CONFIG4H CONFIG1L_unused=0x00 CONFIG1L~1=WDTEN,0x01,Watchdog Timer Enable CONFIG1L~2=STVREN,0x0E,PLL Configuration CONFIG1L~3=ENHCPU,0x20,Stack Overflow Reset CONFIG1L~4=EXTCPU,0x40,Extended CPU CONFIG1L~5=BACKBUG,0x80,Background Debug CONFIG1L~1~1=0x01,0x01,Enabled CONFIG1L~1~2=0x01,0x00,Disabled CONFIG1L~2~1=0x0E,0x0E,No Divide (4MHz input) CONFIG1L~2~2=0x0E,0x0C,Divide by 2 (8MHz input) CONFIG1L~2~3=0x0E,0x0A,Divide by 3 (12MHz input) CONFIG1L~2~4=0x0E,0x08,Divide by 4 (16MHz input) CONFIG1L~2~5=0x0E,0x06,Divide by 5 (20MHz input) CONFIG1L~2~6=0x0E,0x04,Divide by 6 (24MHz input) CONFIG1L~2~7=0x0E,0x02,Divide by 10 (40MHz input) CONFIG1L~2~8=0x0E,0x00,Divide by 12 (48MHz input) CONFIG1L~3~1=0x20,0x20,Enabled CONFIG1L~3~2=0x20,0x00,Disabled CONFIG1L~4~1=0x40,0x40,Enabled CONFIG1L~4~2=0x40,0x00,Disabled CONFIG1L~5~1=0x80,0x80,Disabled CONFIG1L~5~2=0x80,0x00,Enabled CONFIG1H_unused=0x00 CONFIG1H~1=CPDIV,0x3,CPU Clock Divider CONFIG1H~2=CP_0,0x4,Code Protection CONFIG1H~1~1=0x3,0x3,No divide CONFIG1H~1~2=0x3,0x2,Divide by 2 CONFIG1H~1~3=0x3,0x1,Divide by 3 CONFIG1H~1~4=0x3,0x0,Divide by 6 CONFIG1H~2~1=0x4,0x4,Disabled CONFIG1H~2~2=0x4,0x00,Enabled CONFIG2L_unused=0x00 CONFIG2L~1=FOSC,0x07,Oscillator CONFIG2L~2=FCMEN,0x40,Fail Safe Monitor Clock Enable CONFIG2L~3=IESO,0x80,Internal External Switch Over Enable CONFIG2L~1~1=0x07,0x07,EC+PLL(CLKO-RA6) USB-EC+PLL CONFIG2L~1~2=0x07,0x06,EC(CLKO-RA6) USB-EC CONFIG2L~1~3=0x07,0x05,HS+PLL USB-HS+PLL CONFIG2L~1~4=0x07,0x04,HS USB-HS CONFIG2L~1~5=0x07,0x03,INTOSC EC+PLL Osc with CLKOUT CONFIG2L~1~6=0x07,0x02,INTOSC EC Osc with CLKOUT CONFIG2L~1~7=0x07,0x01,INTOSC HS+PLL Osc CONFIG2L~1~8=0x07,0x00,INTOSC HS Osc CONFIG2L~2~1=0x40,0x40,Enabled CONFIG2L~2~2=0x40,0x00,Disabled CONFIG2L~3~1=0x80,0x80,Enabled CONFIG2L~3~2=0x80,0x00,Disabled CONFIG2H_unused=0x00 CONFIG2H~1=WDTPS,0x0f,Watchdog Timer Postscale CONFIG2H~1~1=0x000f,0x000f,1:32,768 CONFIG2H~1~2=0x000f,0x000e,1:16,384 CONFIG2H~1~3=0x000f,0x000d,1:8,192 CONFIG2H~1~4=0x000f,0x000c,1:4,096 CONFIG2H~1~5=0x000f,0x000b,1:2,048 CONFIG2H~1~6=0x000f,0x000a,1:1,024 CONFIG2H~1~7=0x000f,0x0009,1:512 CONFIG2H~1~8=0x000f,0x0008,1:256 CONFIG2H~1~9=0x000f,0x0007,1:128 CONFIG2H~1~10=0x000f,0x0006,1:64 CONFIG2H~1~11=0x000f,0x0005,1:32 CONFIG2H~1~12=0x000f,0x0004,1:16 CONFIG2H~1~13=0x000f,0x0003,1:8 CONFIG2H~1~14=0x000f,0x0002,1:4 CONFIG2H~1~15=0x000f,0x0001,1:2 CONFIG2H~1~16=0x000f,0x0000,1:1 CONFIG3L_unused=0x00 CONFIG3H_unused=0x00 CONFIG3H~1=CCP2MX,0x01,CCP2 Mux CONFIG3H~2=ECCPXM,0x02,ECCP Mux CONFIG3H~1~1=0x01,0x01,ECCP2 I/O Muxed With RC1 CONFIG3H~1~2=0x01,0x00,ECCP2 IP Muxed With RE7 CONFIG3H~2~1=0x02,0x02,P1B/P1C On RE6/RE5, P3B/P3C On RE4/RE3 CONFIG3H~2~2=0x02,0x00,P1B/P1C On RH7/RH6, P3B/P3C Onto RH5/RH4 CONFIG4L_unused=0x00 CONFIG4H_unused=0x00 erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F86J10] pgmmem=0x0 ~pgmmem=0x1fff7 cfgmem=0x1fff8 ~cfgmem=0x1ffff userid= ~userid= eedata=0x00 ~eedata=0xf5f devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x1720 configslots=8 0x1fff8=CONFIG1L 0x1fff9=CONFIG1H 0x1fffa=CONFIG2L 0x1fffb=CONFIG2H 0x1fffc=CONFIG3L 0x1fffd=CONFIG3H 0x1fffe=CONFIG4L 0x1ffff=CONFIG4H CONFIG1L_unused=0x00 CONFIG1L~1=WDTEN,0x01,Watchdog Timer Enable CONFIG1L~2=STVREN,0x0E,PLL Configuration CONFIG1L~3=ENHCPU,0x20,Stack Overflow Reset CONFIG1L~4=EXTCPU,0x40,Extended CPU CONFIG1L~5=BACKBUG,0x80,Background Debug CONFIG1L~1~1=0x01,0x01,Enabled CONFIG1L~1~2=0x01,0x00,Disabled CONFIG1L~2~1=0x0E,0x0E,No Divide (4MHz input) CONFIG1L~2~2=0x0E,0x0C,Divide by 2 (8MHz input) CONFIG1L~2~3=0x0E,0x0A,Divide by 3 (12MHz input) CONFIG1L~2~4=0x0E,0x08,Divide by 4 (16MHz input) CONFIG1L~2~5=0x0E,0x06,Divide by 5 (20MHz input) CONFIG1L~2~6=0x0E,0x04,Divide by 6 (24MHz input) CONFIG1L~2~7=0x0E,0x02,Divide by 10 (40MHz input) CONFIG1L~2~8=0x0E,0x00,Divide by 12 (48MHz input) CONFIG1L~3~1=0x20,0x20,Enabled CONFIG1L~3~2=0x20,0x00,Disabled CONFIG1L~4~1=0x40,0x40,Enabled CONFIG1L~4~2=0x40,0x00,Disabled CONFIG1L~5~1=0x80,0x80,Disabled CONFIG1L~5~2=0x80,0x00,Enabled CONFIG1H_unused=0x00 CONFIG1H~1=CPDIV,0x3,CPU Clock Divider CONFIG1H~2=CP_0,0x4,Code Protection CONFIG1H~1~1=0x3,0x3,No divide CONFIG1H~1~2=0x3,0x2,Divide by 2 CONFIG1H~1~3=0x3,0x1,Divide by 3 CONFIG1H~1~4=0x3,0x0,Divide by 6 CONFIG1H~2~1=0x4,0x4,Disabled CONFIG1H~2~2=0x4,0x00,Enabled CONFIG2L_unused=0x00 CONFIG2L~1=FOSC,0x07,Oscillator CONFIG2L~2=FCMEN,0x40,Fail Safe Monitor Clock Enable CONFIG2L~3=IESO,0x80,Internal External Switch Over Enable CONFIG2L~1~1=0x07,0x07,EC+PLL(CLKO-RA6) USB-EC+PLL CONFIG2L~1~2=0x07,0x06,EC(CLKO-RA6) USB-EC CONFIG2L~1~3=0x07,0x05,HS+PLL USB-HS+PLL CONFIG2L~1~4=0x07,0x04,HS USB-HS CONFIG2L~1~5=0x07,0x03,INTOSC EC+PLL Osc with CLKOUT CONFIG2L~1~6=0x07,0x02,INTOSC EC Osc with CLKOUT CONFIG2L~1~7=0x07,0x01,INTOSC HS+PLL Osc CONFIG2L~1~8=0x07,0x00,INTOSC HS Osc CONFIG2L~2~1=0x40,0x40,Enabled CONFIG2L~2~2=0x40,0x00,Disabled CONFIG2L~3~1=0x80,0x80,Enabled CONFIG2L~3~2=0x80,0x00,Disabled CONFIG2H_unused=0x00 CONFIG2H~1=WDTPS,0x0f,Watchdog Timer Postscale CONFIG2H~1~1=0x000f,0x000f,1:32,768 CONFIG2H~1~2=0x000f,0x000e,1:16,384 CONFIG2H~1~3=0x000f,0x000d,1:8,192 CONFIG2H~1~4=0x000f,0x000c,1:4,096 CONFIG2H~1~5=0x000f,0x000b,1:2,048 CONFIG2H~1~6=0x000f,0x000a,1:1,024 CONFIG2H~1~7=0x000f,0x0009,1:512 CONFIG2H~1~8=0x000f,0x0008,1:256 CONFIG2H~1~9=0x000f,0x0007,1:128 CONFIG2H~1~10=0x000f,0x0006,1:64 CONFIG2H~1~11=0x000f,0x0005,1:32 CONFIG2H~1~12=0x000f,0x0004,1:16 CONFIG2H~1~13=0x000f,0x0003,1:8 CONFIG2H~1~14=0x000f,0x0002,1:4 CONFIG2H~1~15=0x000f,0x0001,1:2 CONFIG2H~1~16=0x000f,0x0000,1:1 CONFIG3L_unused=0x00 CONFIG3H_unused=0x00 CONFIG3H~1=CCP2MX,0x01,CCP2 Mux CONFIG3H~2=ECCPXM,0x02,ECCP Mux CONFIG3H~1~1=0x01,0x01,ECCP2 I/O Muxed With RC1 CONFIG3H~1~2=0x01,0x00,ECCP2 IP Muxed With RE7 CONFIG3H~2~1=0x02,0x02,P1B/P1C On RE6/RE5, P3B/P3C On RE4/RE3 CONFIG3H~2~2=0x02,0x00,P1B/P1C On RH7/RH6, P3B/P3C Onto RH5/RH4 CONFIG4L_unused=0x00 CONFIG4H_unused=0x00 erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F86J11] pgmmem=0x0 ~pgmmem=0x1fff7 cfgmem=0x1fff8 ~cfgmem=0x1ffff userid= ~userid= eedata=0x00 ~eedata=0xf5f devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x44E0 configslots=8 0x1fff8=CONFIG1L 0x1fff9=CONFIG1H 0x1fffa=CONFIG2L 0x1fffb=CONFIG2H 0x1fffc=CONFIG3L 0x1fffd=CONFIG3H 0x1fffe=CONFIG4L 0x1ffff=CONFIG4H CONFIG1L_unused=0x00 CONFIG1L~1=WDTEN,0x01,Watchdog Timer Enable CONFIG1L~2=STVREN,0x0E,PLL Configuration CONFIG1L~3=ENHCPU,0x20,Stack Overflow Reset CONFIG1L~4=EXTCPU,0x40,Extended CPU CONFIG1L~5=BACKBUG,0x80,Background Debug CONFIG1L~1~1=0x01,0x01,Enabled CONFIG1L~1~2=0x01,0x00,Disabled CONFIG1L~2~1=0x0E,0x0E,No Divide (4MHz input) CONFIG1L~2~2=0x0E,0x0C,Divide by 2 (8MHz input) CONFIG1L~2~3=0x0E,0x0A,Divide by 3 (12MHz input) CONFIG1L~2~4=0x0E,0x08,Divide by 4 (16MHz input) CONFIG1L~2~5=0x0E,0x06,Divide by 5 (20MHz input) CONFIG1L~2~6=0x0E,0x04,Divide by 6 (24MHz input) CONFIG1L~2~7=0x0E,0x02,Divide by 10 (40MHz input) CONFIG1L~2~8=0x0E,0x00,Divide by 12 (48MHz input) CONFIG1L~3~1=0x20,0x20,Enabled CONFIG1L~3~2=0x20,0x00,Disabled CONFIG1L~4~1=0x40,0x40,Enabled CONFIG1L~4~2=0x40,0x00,Disabled CONFIG1L~5~1=0x80,0x80,Disabled CONFIG1L~5~2=0x80,0x00,Enabled CONFIG1H_unused=0x00 CONFIG1H~1=CPDIV,0x3,CPU Clock Divider CONFIG1H~2=CP_0,0x4,Code Protection CONFIG1H~1~1=0x3,0x3,No divide CONFIG1H~1~2=0x3,0x2,Divide by 2 CONFIG1H~1~3=0x3,0x1,Divide by 3 CONFIG1H~1~4=0x3,0x0,Divide by 6 CONFIG1H~2~1=0x4,0x4,Disabled CONFIG1H~2~2=0x4,0x00,Enabled CONFIG2L_unused=0x00 CONFIG2L~1=FOSC,0x07,Oscillator CONFIG2L~2=FCMEN,0x40,Fail Safe Monitor Clock Enable CONFIG2L~3=IESO,0x80,Internal External Switch Over Enable CONFIG2L~1~1=0x07,0x07,EC+PLL(CLKO-RA6) USB-EC+PLL CONFIG2L~1~2=0x07,0x06,EC(CLKO-RA6) USB-EC CONFIG2L~1~3=0x07,0x05,HS+PLL USB-HS+PLL CONFIG2L~1~4=0x07,0x04,HS USB-HS CONFIG2L~1~5=0x07,0x03,INTOSC EC+PLL Osc with CLKOUT CONFIG2L~1~6=0x07,0x02,INTOSC EC Osc with CLKOUT CONFIG2L~1~7=0x07,0x01,INTOSC HS+PLL Osc CONFIG2L~1~8=0x07,0x00,INTOSC HS Osc CONFIG2L~2~1=0x40,0x40,Enabled CONFIG2L~2~2=0x40,0x00,Disabled CONFIG2L~3~1=0x80,0x80,Enabled CONFIG2L~3~2=0x80,0x00,Disabled CONFIG2H_unused=0x00 CONFIG2H~1=WDTPS,0x0f,Watchdog Timer Postscale CONFIG2H~1~1=0x000f,0x000f,1:32,768 CONFIG2H~1~2=0x000f,0x000e,1:16,384 CONFIG2H~1~3=0x000f,0x000d,1:8,192 CONFIG2H~1~4=0x000f,0x000c,1:4,096 CONFIG2H~1~5=0x000f,0x000b,1:2,048 CONFIG2H~1~6=0x000f,0x000a,1:1,024 CONFIG2H~1~7=0x000f,0x0009,1:512 CONFIG2H~1~8=0x000f,0x0008,1:256 CONFIG2H~1~9=0x000f,0x0007,1:128 CONFIG2H~1~10=0x000f,0x0006,1:64 CONFIG2H~1~11=0x000f,0x0005,1:32 CONFIG2H~1~12=0x000f,0x0004,1:16 CONFIG2H~1~13=0x000f,0x0003,1:8 CONFIG2H~1~14=0x000f,0x0002,1:4 CONFIG2H~1~15=0x000f,0x0001,1:2 CONFIG2H~1~16=0x000f,0x0000,1:1 CONFIG3L_unused=0x00 CONFIG3H_unused=0x00 CONFIG3H~1=CCP2MX,0x01,CCP2 Mux CONFIG3H~2=ECCPXM,0x02,ECCP Mux CONFIG3H~1~1=0x01,0x01,ECCP2 I/O Muxed With RC1 CONFIG3H~1~2=0x01,0x00,ECCP2 IP Muxed With RE7 CONFIG3H~2~1=0x02,0x02,P1B/P1C On RE6/RE5, P3B/P3C On RE4/RE3 CONFIG3H~2~2=0x02,0x00,P1B/P1C On RH7/RH6, P3B/P3C Onto RH5/RH4 CONFIG4L_unused=0x00 CONFIG4H_unused=0x00 erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F86J15] pgmmem=0x0 ~pgmmem=0x1fff7 cfgmem=0x1fff8 ~cfgmem=0x1ffff userid= ~userid= eedata=0x00 ~eedata=0xf5f devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x1740 configslots=8 0x1fff8=CONFIG1L 0x1fff9=CONFIG1H 0x1fffa=CONFIG2L 0x1fffb=CONFIG2H 0x1fffc=CONFIG3L 0x1fffd=CONFIG3H 0x1fffe=CONFIG4L 0x1ffff=CONFIG4H CONFIG1L_unused=0x00 CONFIG1L~1=WDTEN,0x01,Watchdog Timer Enable CONFIG1L~2=STVREN,0x0E,PLL Configuration CONFIG1L~3=ENHCPU,0x20,Stack Overflow Reset CONFIG1L~4=EXTCPU,0x40,Extended CPU CONFIG1L~5=BACKBUG,0x80,Background Debug CONFIG1L~1~1=0x01,0x01,Enabled CONFIG1L~1~2=0x01,0x00,Disabled CONFIG1L~2~1=0x0E,0x0E,No Divide (4MHz input) CONFIG1L~2~2=0x0E,0x0C,Divide by 2 (8MHz input) CONFIG1L~2~3=0x0E,0x0A,Divide by 3 (12MHz input) CONFIG1L~2~4=0x0E,0x08,Divide by 4 (16MHz input) CONFIG1L~2~5=0x0E,0x06,Divide by 5 (20MHz input) CONFIG1L~2~6=0x0E,0x04,Divide by 6 (24MHz input) CONFIG1L~2~7=0x0E,0x02,Divide by 10 (40MHz input) CONFIG1L~2~8=0x0E,0x00,Divide by 12 (48MHz input) CONFIG1L~3~1=0x20,0x20,Enabled CONFIG1L~3~2=0x20,0x00,Disabled CONFIG1L~4~1=0x40,0x40,Enabled CONFIG1L~4~2=0x40,0x00,Disabled CONFIG1L~5~1=0x80,0x80,Disabled CONFIG1L~5~2=0x80,0x00,Enabled CONFIG1H_unused=0x00 CONFIG1H~1=CPDIV,0x3,CPU Clock Divider CONFIG1H~2=CP_0,0x4,Code Protection CONFIG1H~1~1=0x3,0x3,No divide CONFIG1H~1~2=0x3,0x2,Divide by 2 CONFIG1H~1~3=0x3,0x1,Divide by 3 CONFIG1H~1~4=0x3,0x0,Divide by 6 CONFIG1H~2~1=0x4,0x4,Disabled CONFIG1H~2~2=0x4,0x00,Enabled CONFIG2L_unused=0x00 CONFIG2L~1=FOSC,0x07,Oscillator CONFIG2L~2=FCMEN,0x40,Fail Safe Monitor Clock Enable CONFIG2L~3=IESO,0x80,Internal External Switch Over Enable CONFIG2L~1~1=0x07,0x07,EC+PLL(CLKO-RA6) USB-EC+PLL CONFIG2L~1~2=0x07,0x06,EC(CLKO-RA6) USB-EC CONFIG2L~1~3=0x07,0x05,HS+PLL USB-HS+PLL CONFIG2L~1~4=0x07,0x04,HS USB-HS CONFIG2L~1~5=0x07,0x03,INTOSC EC+PLL Osc with CLKOUT CONFIG2L~1~6=0x07,0x02,INTOSC EC Osc with CLKOUT CONFIG2L~1~7=0x07,0x01,INTOSC HS+PLL Osc CONFIG2L~1~8=0x07,0x00,INTOSC HS Osc CONFIG2L~2~1=0x40,0x40,Enabled CONFIG2L~2~2=0x40,0x00,Disabled CONFIG2L~3~1=0x80,0x80,Enabled CONFIG2L~3~2=0x80,0x00,Disabled CONFIG2H_unused=0x00 CONFIG2H~1=WDTPS,0x0f,Watchdog Timer Postscale CONFIG2H~1~1=0x000f,0x000f,1:32,768 CONFIG2H~1~2=0x000f,0x000e,1:16,384 CONFIG2H~1~3=0x000f,0x000d,1:8,192 CONFIG2H~1~4=0x000f,0x000c,1:4,096 CONFIG2H~1~5=0x000f,0x000b,1:2,048 CONFIG2H~1~6=0x000f,0x000a,1:1,024 CONFIG2H~1~7=0x000f,0x0009,1:512 CONFIG2H~1~8=0x000f,0x0008,1:256 CONFIG2H~1~9=0x000f,0x0007,1:128 CONFIG2H~1~10=0x000f,0x0006,1:64 CONFIG2H~1~11=0x000f,0x0005,1:32 CONFIG2H~1~12=0x000f,0x0004,1:16 CONFIG2H~1~13=0x000f,0x0003,1:8 CONFIG2H~1~14=0x000f,0x0002,1:4 CONFIG2H~1~15=0x000f,0x0001,1:2 CONFIG2H~1~16=0x000f,0x0000,1:1 CONFIG3L_unused=0x00 CONFIG3H_unused=0x00 CONFIG3H~1=CCP2MX,0x01,CCP2 Mux CONFIG3H~2=ECCPXM,0x02,ECCP Mux CONFIG3H~1~1=0x01,0x01,ECCP2 I/O Muxed With RC1 CONFIG3H~1~2=0x01,0x00,ECCP2 IP Muxed With RE7 CONFIG3H~2~1=0x02,0x02,P1B/P1C On RE6/RE5, P3B/P3C On RE4/RE3 CONFIG3H~2~2=0x02,0x00,P1B/P1C On RH7/RH6, P3B/P3C Onto RH5/RH4 CONFIG4L_unused=0x00 CONFIG4H_unused=0x00 erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F86J16] pgmmem=0x0 ~pgmmem=0x1fff7 cfgmem=0x1fff8 ~cfgmem=0x1ffff userid= ~userid= eedata=0x00 ~eedata=0xf5f devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x4500 configslots=8 0x1fff8=CONFIG1L 0x1fff9=CONFIG1H 0x1fffa=CONFIG2L 0x1fffb=CONFIG2H 0x1fffc=CONFIG3L 0x1fffd=CONFIG3H 0x1fffe=CONFIG4L 0x1ffff=CONFIG4H CONFIG1L_unused=0x00 CONFIG1L~1=WDTEN,0x01,Watchdog Timer Enable CONFIG1L~2=STVREN,0x0E,PLL Configuration CONFIG1L~3=ENHCPU,0x20,Stack Overflow Reset CONFIG1L~4=EXTCPU,0x40,Extended CPU CONFIG1L~5=BACKBUG,0x80,Background Debug CONFIG1L~1~1=0x01,0x01,Enabled CONFIG1L~1~2=0x01,0x00,Disabled CONFIG1L~2~1=0x0E,0x0E,No Divide (4MHz input) CONFIG1L~2~2=0x0E,0x0C,Divide by 2 (8MHz input) CONFIG1L~2~3=0x0E,0x0A,Divide by 3 (12MHz input) CONFIG1L~2~4=0x0E,0x08,Divide by 4 (16MHz input) CONFIG1L~2~5=0x0E,0x06,Divide by 5 (20MHz input) CONFIG1L~2~6=0x0E,0x04,Divide by 6 (24MHz input) CONFIG1L~2~7=0x0E,0x02,Divide by 10 (40MHz input) CONFIG1L~2~8=0x0E,0x00,Divide by 12 (48MHz input) CONFIG1L~3~1=0x20,0x20,Enabled CONFIG1L~3~2=0x20,0x00,Disabled CONFIG1L~4~1=0x40,0x40,Enabled CONFIG1L~4~2=0x40,0x00,Disabled CONFIG1L~5~1=0x80,0x80,Disabled CONFIG1L~5~2=0x80,0x00,Enabled CONFIG1H_unused=0x00 CONFIG1H~1=CPDIV,0x3,CPU Clock Divider CONFIG1H~2=CP_0,0x4,Code Protection CONFIG1H~1~1=0x3,0x3,No divide CONFIG1H~1~2=0x3,0x2,Divide by 2 CONFIG1H~1~3=0x3,0x1,Divide by 3 CONFIG1H~1~4=0x3,0x0,Divide by 6 CONFIG1H~2~1=0x4,0x4,Disabled CONFIG1H~2~2=0x4,0x00,Enabled CONFIG2L_unused=0x00 CONFIG2L~1=FOSC,0x07,Oscillator CONFIG2L~2=FCMEN,0x40,Fail Safe Monitor Clock Enable CONFIG2L~3=IESO,0x80,Internal External Switch Over Enable CONFIG2L~1~1=0x07,0x07,EC+PLL(CLKO-RA6) USB-EC+PLL CONFIG2L~1~2=0x07,0x06,EC(CLKO-RA6) USB-EC CONFIG2L~1~3=0x07,0x05,HS+PLL USB-HS+PLL CONFIG2L~1~4=0x07,0x04,HS USB-HS CONFIG2L~1~5=0x07,0x03,INTOSC EC+PLL Osc with CLKOUT CONFIG2L~1~6=0x07,0x02,INTOSC EC Osc with CLKOUT CONFIG2L~1~7=0x07,0x01,INTOSC HS+PLL Osc CONFIG2L~1~8=0x07,0x00,INTOSC HS Osc CONFIG2L~2~1=0x40,0x40,Enabled CONFIG2L~2~2=0x40,0x00,Disabled CONFIG2L~3~1=0x80,0x80,Enabled CONFIG2L~3~2=0x80,0x00,Disabled CONFIG2H_unused=0x00 CONFIG2H~1=WDTPS,0x0f,Watchdog Timer Postscale CONFIG2H~1~1=0x000f,0x000f,1:32,768 CONFIG2H~1~2=0x000f,0x000e,1:16,384 CONFIG2H~1~3=0x000f,0x000d,1:8,192 CONFIG2H~1~4=0x000f,0x000c,1:4,096 CONFIG2H~1~5=0x000f,0x000b,1:2,048 CONFIG2H~1~6=0x000f,0x000a,1:1,024 CONFIG2H~1~7=0x000f,0x0009,1:512 CONFIG2H~1~8=0x000f,0x0008,1:256 CONFIG2H~1~9=0x000f,0x0007,1:128 CONFIG2H~1~10=0x000f,0x0006,1:64 CONFIG2H~1~11=0x000f,0x0005,1:32 CONFIG2H~1~12=0x000f,0x0004,1:16 CONFIG2H~1~13=0x000f,0x0003,1:8 CONFIG2H~1~14=0x000f,0x0002,1:4 CONFIG2H~1~15=0x000f,0x0001,1:2 CONFIG2H~1~16=0x000f,0x0000,1:1 CONFIG3L_unused=0x00 CONFIG3H_unused=0x00 CONFIG3H~1=CCP2MX,0x01,CCP2 Mux CONFIG3H~2=ECCPXM,0x02,ECCP Mux CONFIG3H~1~1=0x01,0x01,ECCP2 I/O Muxed With RC1 CONFIG3H~1~2=0x01,0x00,ECCP2 IP Muxed With RE7 CONFIG3H~2~1=0x02,0x02,P1B/P1C On RE6/RE5, P3B/P3C On RE4/RE3 CONFIG3H~2~2=0x02,0x00,P1B/P1C On RH7/RH6, P3B/P3C Onto RH5/RH4 CONFIG4L_unused=0x00 CONFIG4H_unused=0x00 erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F86J50] pgmmem=0x0 ~pgmmem=0x1fff7 cfgmem=0x1fff8 ~cfgmem=0x1ffff userid= ~userid= eedata=0x00 ~eedata=0xf5f devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x41E0 configslots=8 0x1fff8=CONFIG1L 0x1fff9=CONFIG1H 0x1fffa=CONFIG2L 0x1fffb=CONFIG2H 0x1fffc=CONFIG3L 0x1fffd=CONFIG3H 0x1fffe=CONFIG4L 0x1ffff=CONFIG4H CONFIG1L_unused=0x00 CONFIG1L~1=WDTEN,0x01,Watchdog Timer Enable CONFIG1L~2=STVREN,0x0E,PLL Configuration CONFIG1L~3=ENHCPU,0x20,Stack Overflow Reset CONFIG1L~4=EXTCPU,0x40,Extended CPU CONFIG1L~5=BACKBUG,0x80,Background Debug CONFIG1L~1~1=0x01,0x01,Enabled CONFIG1L~1~2=0x01,0x00,Disabled CONFIG1L~2~1=0x0E,0x0E,No Divide (4MHz input) CONFIG1L~2~2=0x0E,0x0C,Divide by 2 (8MHz input) CONFIG1L~2~3=0x0E,0x0A,Divide by 3 (12MHz input) CONFIG1L~2~4=0x0E,0x08,Divide by 4 (16MHz input) CONFIG1L~2~5=0x0E,0x06,Divide by 5 (20MHz input) CONFIG1L~2~6=0x0E,0x04,Divide by 6 (24MHz input) CONFIG1L~2~7=0x0E,0x02,Divide by 10 (40MHz input) CONFIG1L~2~8=0x0E,0x00,Divide by 12 (48MHz input) CONFIG1L~3~1=0x20,0x20,Enabled CONFIG1L~3~2=0x20,0x00,Disabled CONFIG1L~4~1=0x40,0x40,Enabled CONFIG1L~4~2=0x40,0x00,Disabled CONFIG1L~5~1=0x80,0x80,Disabled CONFIG1L~5~2=0x80,0x00,Enabled CONFIG1H_unused=0x00 CONFIG1H~1=CPDIV,0x3,CPU Clock Divider CONFIG1H~2=CP_0,0x4,Code Protection CONFIG1H~1~1=0x3,0x3,No divide CONFIG1H~1~2=0x3,0x2,Divide by 2 CONFIG1H~1~3=0x3,0x1,Divide by 3 CONFIG1H~1~4=0x3,0x0,Divide by 6 CONFIG1H~2~1=0x4,0x4,Disabled CONFIG1H~2~2=0x4,0x00,Enabled CONFIG2L_unused=0x00 CONFIG2L~1=FOSC,0x07,Oscillator CONFIG2L~2=FCMEN,0x40,Fail Safe Monitor Clock Enable CONFIG2L~3=IESO,0x80,Internal External Switch Over Enable CONFIG2L~1~1=0x07,0x07,EC+PLL(CLKO-RA6) USB-EC+PLL CONFIG2L~1~2=0x07,0x06,EC(CLKO-RA6) USB-EC CONFIG2L~1~3=0x07,0x05,HS+PLL USB-HS+PLL CONFIG2L~1~4=0x07,0x04,HS USB-HS CONFIG2L~1~5=0x07,0x03,INTOSC EC+PLL Osc with CLKOUT CONFIG2L~1~6=0x07,0x02,INTOSC EC Osc with CLKOUT CONFIG2L~1~7=0x07,0x01,INTOSC HS+PLL Osc CONFIG2L~1~8=0x07,0x00,INTOSC HS Osc CONFIG2L~2~1=0x40,0x40,Enabled CONFIG2L~2~2=0x40,0x00,Disabled CONFIG2L~3~1=0x80,0x80,Enabled CONFIG2L~3~2=0x80,0x00,Disabled CONFIG2H_unused=0x00 CONFIG2H~1=WDTPS,0x0f,Watchdog Timer Postscale CONFIG2H~1~1=0x000f,0x000f,1:32,768 CONFIG2H~1~2=0x000f,0x000e,1:16,384 CONFIG2H~1~3=0x000f,0x000d,1:8,192 CONFIG2H~1~4=0x000f,0x000c,1:4,096 CONFIG2H~1~5=0x000f,0x000b,1:2,048 CONFIG2H~1~6=0x000f,0x000a,1:1,024 CONFIG2H~1~7=0x000f,0x0009,1:512 CONFIG2H~1~8=0x000f,0x0008,1:256 CONFIG2H~1~9=0x000f,0x0007,1:128 CONFIG2H~1~10=0x000f,0x0006,1:64 CONFIG2H~1~11=0x000f,0x0005,1:32 CONFIG2H~1~12=0x000f,0x0004,1:16 CONFIG2H~1~13=0x000f,0x0003,1:8 CONFIG2H~1~14=0x000f,0x0002,1:4 CONFIG2H~1~15=0x000f,0x0001,1:2 CONFIG2H~1~16=0x000f,0x0000,1:1 CONFIG3L_unused=0x00 CONFIG3H_unused=0x00 CONFIG3H~1=CCP2MX,0x01,CCP2 Mux CONFIG3H~2=ECCPXM,0x02,ECCP Mux CONFIG3H~1~1=0x01,0x01,ECCP2 I/O Muxed With RC1 CONFIG3H~1~2=0x01,0x00,ECCP2 IP Muxed With RE7 CONFIG3H~2~1=0x02,0x02,P1B/P1C On RE6/RE5, P3B/P3C On RE4/RE3 CONFIG3H~2~2=0x02,0x00,P1B/P1C On RH7/RH6, P3B/P3C Onto RH5/RH4 CONFIG4L_unused=0x00 CONFIG4H_unused=0x00 erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F86J55] pgmmem=0x0 ~pgmmem=0x1fff7 cfgmem=0x1fff8 ~cfgmem=0x1ffff userid= ~userid= eedata=0x00 ~eedata=0xf5f devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x4200 configslots=8 0x1fff8=CONFIG1L 0x1fff9=CONFIG1H 0x1fffa=CONFIG2L 0x1fffb=CONFIG2H 0x1fffc=CONFIG3L 0x1fffd=CONFIG3H 0x1fffe=CONFIG4L 0x1ffff=CONFIG4H CONFIG1L_unused=0x00 CONFIG1L~1=WDTEN,0x01,Watchdog Timer Enable CONFIG1L~2=STVREN,0x0E,PLL Configuration CONFIG1L~3=ENHCPU,0x20,Stack Overflow Reset CONFIG1L~4=EXTCPU,0x40,Extended CPU CONFIG1L~5=BACKBUG,0x80,Background Debug CONFIG1L~1~1=0x01,0x01,Enabled CONFIG1L~1~2=0x01,0x00,Disabled CONFIG1L~2~1=0x0E,0x0E,No Divide (4MHz input) CONFIG1L~2~2=0x0E,0x0C,Divide by 2 (8MHz input) CONFIG1L~2~3=0x0E,0x0A,Divide by 3 (12MHz input) CONFIG1L~2~4=0x0E,0x08,Divide by 4 (16MHz input) CONFIG1L~2~5=0x0E,0x06,Divide by 5 (20MHz input) CONFIG1L~2~6=0x0E,0x04,Divide by 6 (24MHz input) CONFIG1L~2~7=0x0E,0x02,Divide by 10 (40MHz input) CONFIG1L~2~8=0x0E,0x00,Divide by 12 (48MHz input) CONFIG1L~3~1=0x20,0x20,Enabled CONFIG1L~3~2=0x20,0x00,Disabled CONFIG1L~4~1=0x40,0x40,Enabled CONFIG1L~4~2=0x40,0x00,Disabled CONFIG1L~5~1=0x80,0x80,Disabled CONFIG1L~5~2=0x80,0x00,Enabled CONFIG1H_unused=0x00 CONFIG1H~1=CPDIV,0x3,CPU Clock Divider CONFIG1H~2=CP_0,0x4,Code Protection CONFIG1H~1~1=0x3,0x3,No divide CONFIG1H~1~2=0x3,0x2,Divide by 2 CONFIG1H~1~3=0x3,0x1,Divide by 3 CONFIG1H~1~4=0x3,0x0,Divide by 6 CONFIG1H~2~1=0x4,0x4,Disabled CONFIG1H~2~2=0x4,0x00,Enabled CONFIG2L_unused=0x00 CONFIG2L~1=FOSC,0x07,Oscillator CONFIG2L~2=FCMEN,0x40,Fail Safe Monitor Clock Enable CONFIG2L~3=IESO,0x80,Internal External Switch Over Enable CONFIG2L~1~1=0x07,0x07,EC+PLL(CLKO-RA6) USB-EC+PLL CONFIG2L~1~2=0x07,0x06,EC(CLKO-RA6) USB-EC CONFIG2L~1~3=0x07,0x05,HS+PLL USB-HS+PLL CONFIG2L~1~4=0x07,0x04,HS USB-HS CONFIG2L~1~5=0x07,0x03,INTOSC EC+PLL Osc with CLKOUT CONFIG2L~1~6=0x07,0x02,INTOSC EC Osc with CLKOUT CONFIG2L~1~7=0x07,0x01,INTOSC HS+PLL Osc CONFIG2L~1~8=0x07,0x00,INTOSC HS Osc CONFIG2L~2~1=0x40,0x40,Enabled CONFIG2L~2~2=0x40,0x00,Disabled CONFIG2L~3~1=0x80,0x80,Enabled CONFIG2L~3~2=0x80,0x00,Disabled CONFIG2H_unused=0x00 CONFIG2H~1=WDTPS,0x0f,Watchdog Timer Postscale CONFIG2H~1~1=0x000f,0x000f,1:32,768 CONFIG2H~1~2=0x000f,0x000e,1:16,384 CONFIG2H~1~3=0x000f,0x000d,1:8,192 CONFIG2H~1~4=0x000f,0x000c,1:4,096 CONFIG2H~1~5=0x000f,0x000b,1:2,048 CONFIG2H~1~6=0x000f,0x000a,1:1,024 CONFIG2H~1~7=0x000f,0x0009,1:512 CONFIG2H~1~8=0x000f,0x0008,1:256 CONFIG2H~1~9=0x000f,0x0007,1:128 CONFIG2H~1~10=0x000f,0x0006,1:64 CONFIG2H~1~11=0x000f,0x0005,1:32 CONFIG2H~1~12=0x000f,0x0004,1:16 CONFIG2H~1~13=0x000f,0x0003,1:8 CONFIG2H~1~14=0x000f,0x0002,1:4 CONFIG2H~1~15=0x000f,0x0001,1:2 CONFIG2H~1~16=0x000f,0x0000,1:1 CONFIG3L_unused=0x00 CONFIG3H_unused=0x00 CONFIG3H~1=CCP2MX,0x01,CCP2 Mux CONFIG3H~2=ECCPXM,0x02,ECCP Mux CONFIG3H~1~1=0x01,0x01,ECCP2 I/O Muxed With RC1 CONFIG3H~1~2=0x01,0x00,ECCP2 IP Muxed With RE7 CONFIG3H~2~1=0x02,0x02,P1B/P1C On RE6/RE5, P3B/P3C On RE4/RE3 CONFIG3H~2~2=0x02,0x00,P1B/P1C On RH7/RH6, P3B/P3C Onto RH5/RH4 CONFIG4L_unused=0x00 CONFIG4H_unused=0x00 erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F86J72] pgmmem=0x0 ~pgmmem=0x1fff7 cfgmem=0x1fff8 ~cfgmem=0x1ffff userid= ~userid= eedata=0x00 ~eedata=0xf5f devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x5040 configslots=8 0x1fff8=CONFIG1L 0x1fff9=CONFIG1H 0x1fffa=CONFIG2L 0x1fffb=CONFIG2H 0x1fffc=CONFIG3L 0x1fffd=CONFIG3H 0x1fffe=CONFIG4L 0x1ffff=CONFIG4H CONFIG1L_unused=0x00 CONFIG1L~1=WDTEN,0x01,Watchdog Timer Enable CONFIG1L~2=STVREN,0x0E,PLL Configuration CONFIG1L~3=ENHCPU,0x20,Stack Overflow Reset CONFIG1L~4=EXTCPU,0x40,Extended CPU CONFIG1L~5=BACKBUG,0x80,Background Debug CONFIG1L~1~1=0x01,0x01,Enabled CONFIG1L~1~2=0x01,0x00,Disabled CONFIG1L~2~1=0x0E,0x0E,No Divide (4MHz input) CONFIG1L~2~2=0x0E,0x0C,Divide by 2 (8MHz input) CONFIG1L~2~3=0x0E,0x0A,Divide by 3 (12MHz input) CONFIG1L~2~4=0x0E,0x08,Divide by 4 (16MHz input) CONFIG1L~2~5=0x0E,0x06,Divide by 5 (20MHz input) CONFIG1L~2~6=0x0E,0x04,Divide by 6 (24MHz input) CONFIG1L~2~7=0x0E,0x02,Divide by 10 (40MHz input) CONFIG1L~2~8=0x0E,0x00,Divide by 12 (48MHz input) CONFIG1L~3~1=0x20,0x20,Enabled CONFIG1L~3~2=0x20,0x00,Disabled CONFIG1L~4~1=0x40,0x40,Enabled CONFIG1L~4~2=0x40,0x00,Disabled CONFIG1L~5~1=0x80,0x80,Disabled CONFIG1L~5~2=0x80,0x00,Enabled CONFIG1H_unused=0x00 CONFIG1H~1=CPDIV,0x3,CPU Clock Divider CONFIG1H~2=CP_0,0x4,Code Protection CONFIG1H~1~1=0x3,0x3,No divide CONFIG1H~1~2=0x3,0x2,Divide by 2 CONFIG1H~1~3=0x3,0x1,Divide by 3 CONFIG1H~1~4=0x3,0x0,Divide by 6 CONFIG1H~2~1=0x4,0x4,Disabled CONFIG1H~2~2=0x4,0x00,Enabled CONFIG2L_unused=0x00 CONFIG2L~1=FOSC,0x07,Oscillator CONFIG2L~2=FCMEN,0x40,Fail Safe Monitor Clock Enable CONFIG2L~3=IESO,0x80,Internal External Switch Over Enable CONFIG2L~1~1=0x07,0x07,EC+PLL(CLKO-RA6) USB-EC+PLL CONFIG2L~1~2=0x07,0x06,EC(CLKO-RA6) USB-EC CONFIG2L~1~3=0x07,0x05,HS+PLL USB-HS+PLL CONFIG2L~1~4=0x07,0x04,HS USB-HS CONFIG2L~1~5=0x07,0x03,INTOSC EC+PLL Osc with CLKOUT CONFIG2L~1~6=0x07,0x02,INTOSC EC Osc with CLKOUT CONFIG2L~1~7=0x07,0x01,INTOSC HS+PLL Osc CONFIG2L~1~8=0x07,0x00,INTOSC HS Osc CONFIG2L~2~1=0x40,0x40,Enabled CONFIG2L~2~2=0x40,0x00,Disabled CONFIG2L~3~1=0x80,0x80,Enabled CONFIG2L~3~2=0x80,0x00,Disabled CONFIG2H_unused=0x00 CONFIG2H~1=WDTPS,0x0f,Watchdog Timer Postscale CONFIG2H~1~1=0x000f,0x000f,1:32,768 CONFIG2H~1~2=0x000f,0x000e,1:16,384 CONFIG2H~1~3=0x000f,0x000d,1:8,192 CONFIG2H~1~4=0x000f,0x000c,1:4,096 CONFIG2H~1~5=0x000f,0x000b,1:2,048 CONFIG2H~1~6=0x000f,0x000a,1:1,024 CONFIG2H~1~7=0x000f,0x0009,1:512 CONFIG2H~1~8=0x000f,0x0008,1:256 CONFIG2H~1~9=0x000f,0x0007,1:128 CONFIG2H~1~10=0x000f,0x0006,1:64 CONFIG2H~1~11=0x000f,0x0005,1:32 CONFIG2H~1~12=0x000f,0x0004,1:16 CONFIG2H~1~13=0x000f,0x0003,1:8 CONFIG2H~1~14=0x000f,0x0002,1:4 CONFIG2H~1~15=0x000f,0x0001,1:2 CONFIG2H~1~16=0x000f,0x0000,1:1 CONFIG3L_unused=0x00 CONFIG3H_unused=0x00 CONFIG3H~1=CCP2MX,0x01,CCP2 Mux CONFIG3H~2=ECCPXM,0x02,ECCP Mux CONFIG3H~1~1=0x01,0x01,ECCP2 I/O Muxed With RC1 CONFIG3H~1~2=0x01,0x00,ECCP2 IP Muxed With RE7 CONFIG3H~2~1=0x02,0x02,P1B/P1C On RE6/RE5, P3B/P3C On RE4/RE3 CONFIG3H~2~2=0x02,0x00,P1B/P1C On RH7/RH6, P3B/P3C Onto RH5/RH4 CONFIG4L_unused=0x00 CONFIG4H_unused=0x00 erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F86J90] pgmmem=0x0 ~pgmmem=0x1fff7 cfgmem=0x1fff8 ~cfgmem=0x1ffff userid= ~userid= eedata=0x00 ~eedata=0xf5f devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x5080 configslots=8 0x1fff8=CONFIG1L 0x1fff9=CONFIG1H 0x1fffa=CONFIG2L 0x1fffb=CONFIG2H 0x1fffc=CONFIG3L 0x1fffd=CONFIG3H 0x1fffe=CONFIG4L 0x1ffff=CONFIG4H CONFIG1L_unused=0x00 CONFIG1L~1=WDTEN,0x01,Watchdog Timer Enable CONFIG1L~2=STVREN,0x0E,PLL Configuration CONFIG1L~3=ENHCPU,0x20,Stack Overflow Reset CONFIG1L~4=EXTCPU,0x40,Extended CPU CONFIG1L~5=BACKBUG,0x80,Background Debug CONFIG1L~1~1=0x01,0x01,Enabled CONFIG1L~1~2=0x01,0x00,Disabled CONFIG1L~2~1=0x0E,0x0E,No Divide (4MHz input) CONFIG1L~2~2=0x0E,0x0C,Divide by 2 (8MHz input) CONFIG1L~2~3=0x0E,0x0A,Divide by 3 (12MHz input) CONFIG1L~2~4=0x0E,0x08,Divide by 4 (16MHz input) CONFIG1L~2~5=0x0E,0x06,Divide by 5 (20MHz input) CONFIG1L~2~6=0x0E,0x04,Divide by 6 (24MHz input) CONFIG1L~2~7=0x0E,0x02,Divide by 10 (40MHz input) CONFIG1L~2~8=0x0E,0x00,Divide by 12 (48MHz input) CONFIG1L~3~1=0x20,0x20,Enabled CONFIG1L~3~2=0x20,0x00,Disabled CONFIG1L~4~1=0x40,0x40,Enabled CONFIG1L~4~2=0x40,0x00,Disabled CONFIG1L~5~1=0x80,0x80,Disabled CONFIG1L~5~2=0x80,0x00,Enabled CONFIG1H_unused=0x00 CONFIG1H~1=CPDIV,0x3,CPU Clock Divider CONFIG1H~2=CP_0,0x4,Code Protection CONFIG1H~1~1=0x3,0x3,No divide CONFIG1H~1~2=0x3,0x2,Divide by 2 CONFIG1H~1~3=0x3,0x1,Divide by 3 CONFIG1H~1~4=0x3,0x0,Divide by 6 CONFIG1H~2~1=0x4,0x4,Disabled CONFIG1H~2~2=0x4,0x00,Enabled CONFIG2L_unused=0x00 CONFIG2L~1=FOSC,0x07,Oscillator CONFIG2L~2=FCMEN,0x40,Fail Safe Monitor Clock Enable CONFIG2L~3=IESO,0x80,Internal External Switch Over Enable CONFIG2L~1~1=0x07,0x07,EC+PLL(CLKO-RA6) USB-EC+PLL CONFIG2L~1~2=0x07,0x06,EC(CLKO-RA6) USB-EC CONFIG2L~1~3=0x07,0x05,HS+PLL USB-HS+PLL CONFIG2L~1~4=0x07,0x04,HS USB-HS CONFIG2L~1~5=0x07,0x03,INTOSC EC+PLL Osc with CLKOUT CONFIG2L~1~6=0x07,0x02,INTOSC EC Osc with CLKOUT CONFIG2L~1~7=0x07,0x01,INTOSC HS+PLL Osc CONFIG2L~1~8=0x07,0x00,INTOSC HS Osc CONFIG2L~2~1=0x40,0x40,Enabled CONFIG2L~2~2=0x40,0x00,Disabled CONFIG2L~3~1=0x80,0x80,Enabled CONFIG2L~3~2=0x80,0x00,Disabled CONFIG2H_unused=0x00 CONFIG2H~1=WDTPS,0x0f,Watchdog Timer Postscale CONFIG2H~1~1=0x000f,0x000f,1:32,768 CONFIG2H~1~2=0x000f,0x000e,1:16,384 CONFIG2H~1~3=0x000f,0x000d,1:8,192 CONFIG2H~1~4=0x000f,0x000c,1:4,096 CONFIG2H~1~5=0x000f,0x000b,1:2,048 CONFIG2H~1~6=0x000f,0x000a,1:1,024 CONFIG2H~1~7=0x000f,0x0009,1:512 CONFIG2H~1~8=0x000f,0x0008,1:256 CONFIG2H~1~9=0x000f,0x0007,1:128 CONFIG2H~1~10=0x000f,0x0006,1:64 CONFIG2H~1~11=0x000f,0x0005,1:32 CONFIG2H~1~12=0x000f,0x0004,1:16 CONFIG2H~1~13=0x000f,0x0003,1:8 CONFIG2H~1~14=0x000f,0x0002,1:4 CONFIG2H~1~15=0x000f,0x0001,1:2 CONFIG2H~1~16=0x000f,0x0000,1:1 CONFIG3L_unused=0x00 CONFIG3H_unused=0x00 CONFIG3H~1=CCP2MX,0x01,CCP2 Mux CONFIG3H~2=ECCPXM,0x02,ECCP Mux CONFIG3H~1~1=0x01,0x01,ECCP2 I/O Muxed With RC1 CONFIG3H~1~2=0x01,0x00,ECCP2 IP Muxed With RE7 CONFIG3H~2~1=0x02,0x02,P1B/P1C On RE6/RE5, P3B/P3C On RE4/RE3 CONFIG3H~2~2=0x02,0x00,P1B/P1C On RH7/RH6, P3B/P3C Onto RH5/RH4 CONFIG4L_unused=0x00 CONFIG4H_unused=0x00 erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F86J93] pgmmem=0x0 ~pgmmem=0x1fff7 cfgmem=0x1fff8 ~cfgmem=0x1ffff userid= ~userid= eedata=0x00 ~eedata=0xf5f devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x50C0 configslots=8 0x1fff8=CONFIG1L 0x1fff9=CONFIG1H 0x1fffa=CONFIG2L 0x1fffb=CONFIG2H 0x1fffc=CONFIG3L 0x1fffd=CONFIG3H 0x1fffe=CONFIG4L 0x1ffff=CONFIG4H CONFIG1L_unused=0x00 CONFIG1L~1=WDTEN,0x01,Watchdog Timer Enable CONFIG1L~2=STVREN,0x0E,PLL Configuration CONFIG1L~3=ENHCPU,0x20,Stack Overflow Reset CONFIG1L~4=EXTCPU,0x40,Extended CPU CONFIG1L~5=BACKBUG,0x80,Background Debug CONFIG1L~1~1=0x01,0x01,Enabled CONFIG1L~1~2=0x01,0x00,Disabled CONFIG1L~2~1=0x0E,0x0E,No Divide (4MHz input) CONFIG1L~2~2=0x0E,0x0C,Divide by 2 (8MHz input) CONFIG1L~2~3=0x0E,0x0A,Divide by 3 (12MHz input) CONFIG1L~2~4=0x0E,0x08,Divide by 4 (16MHz input) CONFIG1L~2~5=0x0E,0x06,Divide by 5 (20MHz input) CONFIG1L~2~6=0x0E,0x04,Divide by 6 (24MHz input) CONFIG1L~2~7=0x0E,0x02,Divide by 10 (40MHz input) CONFIG1L~2~8=0x0E,0x00,Divide by 12 (48MHz input) CONFIG1L~3~1=0x20,0x20,Enabled CONFIG1L~3~2=0x20,0x00,Disabled CONFIG1L~4~1=0x40,0x40,Enabled CONFIG1L~4~2=0x40,0x00,Disabled CONFIG1L~5~1=0x80,0x80,Disabled CONFIG1L~5~2=0x80,0x00,Enabled CONFIG1H_unused=0x00 CONFIG1H~1=CPDIV,0x3,CPU Clock Divider CONFIG1H~2=CP_0,0x4,Code Protection CONFIG1H~1~1=0x3,0x3,No divide CONFIG1H~1~2=0x3,0x2,Divide by 2 CONFIG1H~1~3=0x3,0x1,Divide by 3 CONFIG1H~1~4=0x3,0x0,Divide by 6 CONFIG1H~2~1=0x4,0x4,Disabled CONFIG1H~2~2=0x4,0x00,Enabled CONFIG2L_unused=0x00 CONFIG2L~1=FOSC,0x07,Oscillator CONFIG2L~2=FCMEN,0x40,Fail Safe Monitor Clock Enable CONFIG2L~3=IESO,0x80,Internal External Switch Over Enable CONFIG2L~1~1=0x07,0x07,EC+PLL(CLKO-RA6) USB-EC+PLL CONFIG2L~1~2=0x07,0x06,EC(CLKO-RA6) USB-EC CONFIG2L~1~3=0x07,0x05,HS+PLL USB-HS+PLL CONFIG2L~1~4=0x07,0x04,HS USB-HS CONFIG2L~1~5=0x07,0x03,INTOSC EC+PLL Osc with CLKOUT CONFIG2L~1~6=0x07,0x02,INTOSC EC Osc with CLKOUT CONFIG2L~1~7=0x07,0x01,INTOSC HS+PLL Osc CONFIG2L~1~8=0x07,0x00,INTOSC HS Osc CONFIG2L~2~1=0x40,0x40,Enabled CONFIG2L~2~2=0x40,0x00,Disabled CONFIG2L~3~1=0x80,0x80,Enabled CONFIG2L~3~2=0x80,0x00,Disabled CONFIG2H_unused=0x00 CONFIG2H~1=WDTPS,0x0f,Watchdog Timer Postscale CONFIG2H~1~1=0x000f,0x000f,1:32,768 CONFIG2H~1~2=0x000f,0x000e,1:16,384 CONFIG2H~1~3=0x000f,0x000d,1:8,192 CONFIG2H~1~4=0x000f,0x000c,1:4,096 CONFIG2H~1~5=0x000f,0x000b,1:2,048 CONFIG2H~1~6=0x000f,0x000a,1:1,024 CONFIG2H~1~7=0x000f,0x0009,1:512 CONFIG2H~1~8=0x000f,0x0008,1:256 CONFIG2H~1~9=0x000f,0x0007,1:128 CONFIG2H~1~10=0x000f,0x0006,1:64 CONFIG2H~1~11=0x000f,0x0005,1:32 CONFIG2H~1~12=0x000f,0x0004,1:16 CONFIG2H~1~13=0x000f,0x0003,1:8 CONFIG2H~1~14=0x000f,0x0002,1:4 CONFIG2H~1~15=0x000f,0x0001,1:2 CONFIG2H~1~16=0x000f,0x0000,1:1 CONFIG3L_unused=0x00 CONFIG3H_unused=0x00 CONFIG3H~1=CCP2MX,0x01,CCP2 Mux CONFIG3H~2=ECCPXM,0x02,ECCP Mux CONFIG3H~1~1=0x01,0x01,ECCP2 I/O Muxed With RC1 CONFIG3H~1~2=0x01,0x00,ECCP2 IP Muxed With RE7 CONFIG3H~2~1=0x02,0x02,P1B/P1C On RE6/RE5, P3B/P3C On RE4/RE3 CONFIG3H~2~2=0x02,0x00,P1B/P1C On RH7/RH6, P3B/P3C Onto RH5/RH4 CONFIG4L_unused=0x00 CONFIG4H_unused=0x00 erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F87J10] pgmmem=0x0 ~pgmmem=0x1fff7 cfgmem=0x1fff8 ~cfgmem=0x1ffff userid= ~userid= eedata=0x00 ~eedata=0xf5f devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x1760 configslots=8 0x1fff8=CONFIG1L 0x1fff9=CONFIG1H 0x1fffa=CONFIG2L 0x1fffb=CONFIG2H 0x1fffc=CONFIG3L 0x1fffd=CONFIG3H 0x1fffe=CONFIG4L 0x1ffff=CONFIG4H CONFIG1L_unused=0x00 CONFIG1L~1=WDTEN,0x01,Watchdog Timer Enable CONFIG1L~2=STVREN,0x0E,PLL Configuration CONFIG1L~3=ENHCPU,0x20,Stack Overflow Reset CONFIG1L~4=EXTCPU,0x40,Extended CPU CONFIG1L~5=BACKBUG,0x80,Background Debug CONFIG1L~1~1=0x01,0x01,Enabled CONFIG1L~1~2=0x01,0x00,Disabled CONFIG1L~2~1=0x0E,0x0E,No Divide (4MHz input) CONFIG1L~2~2=0x0E,0x0C,Divide by 2 (8MHz input) CONFIG1L~2~3=0x0E,0x0A,Divide by 3 (12MHz input) CONFIG1L~2~4=0x0E,0x08,Divide by 4 (16MHz input) CONFIG1L~2~5=0x0E,0x06,Divide by 5 (20MHz input) CONFIG1L~2~6=0x0E,0x04,Divide by 6 (24MHz input) CONFIG1L~2~7=0x0E,0x02,Divide by 10 (40MHz input) CONFIG1L~2~8=0x0E,0x00,Divide by 12 (48MHz input) CONFIG1L~3~1=0x20,0x20,Enabled CONFIG1L~3~2=0x20,0x00,Disabled CONFIG1L~4~1=0x40,0x40,Enabled CONFIG1L~4~2=0x40,0x00,Disabled CONFIG1L~5~1=0x80,0x80,Disabled CONFIG1L~5~2=0x80,0x00,Enabled CONFIG1H_unused=0x00 CONFIG1H~1=CPDIV,0x3,CPU Clock Divider CONFIG1H~2=CP_0,0x4,Code Protection CONFIG1H~1~1=0x3,0x3,No divide CONFIG1H~1~2=0x3,0x2,Divide by 2 CONFIG1H~1~3=0x3,0x1,Divide by 3 CONFIG1H~1~4=0x3,0x0,Divide by 6 CONFIG1H~2~1=0x4,0x4,Disabled CONFIG1H~2~2=0x4,0x00,Enabled CONFIG2L_unused=0x00 CONFIG2L~1=FOSC,0x07,Oscillator CONFIG2L~2=FCMEN,0x40,Fail Safe Monitor Clock Enable CONFIG2L~3=IESO,0x80,Internal External Switch Over Enable CONFIG2L~1~1=0x07,0x07,EC+PLL(CLKO-RA6) USB-EC+PLL CONFIG2L~1~2=0x07,0x06,EC(CLKO-RA6) USB-EC CONFIG2L~1~3=0x07,0x05,HS+PLL USB-HS+PLL CONFIG2L~1~4=0x07,0x04,HS USB-HS CONFIG2L~1~5=0x07,0x03,INTOSC EC+PLL Osc with CLKOUT CONFIG2L~1~6=0x07,0x02,INTOSC EC Osc with CLKOUT CONFIG2L~1~7=0x07,0x01,INTOSC HS+PLL Osc CONFIG2L~1~8=0x07,0x00,INTOSC HS Osc CONFIG2L~2~1=0x40,0x40,Enabled CONFIG2L~2~2=0x40,0x00,Disabled CONFIG2L~3~1=0x80,0x80,Enabled CONFIG2L~3~2=0x80,0x00,Disabled CONFIG2H_unused=0x00 CONFIG2H~1=WDTPS,0x0f,Watchdog Timer Postscale CONFIG2H~1~1=0x000f,0x000f,1:32,768 CONFIG2H~1~2=0x000f,0x000e,1:16,384 CONFIG2H~1~3=0x000f,0x000d,1:8,192 CONFIG2H~1~4=0x000f,0x000c,1:4,096 CONFIG2H~1~5=0x000f,0x000b,1:2,048 CONFIG2H~1~6=0x000f,0x000a,1:1,024 CONFIG2H~1~7=0x000f,0x0009,1:512 CONFIG2H~1~8=0x000f,0x0008,1:256 CONFIG2H~1~9=0x000f,0x0007,1:128 CONFIG2H~1~10=0x000f,0x0006,1:64 CONFIG2H~1~11=0x000f,0x0005,1:32 CONFIG2H~1~12=0x000f,0x0004,1:16 CONFIG2H~1~13=0x000f,0x0003,1:8 CONFIG2H~1~14=0x000f,0x0002,1:4 CONFIG2H~1~15=0x000f,0x0001,1:2 CONFIG2H~1~16=0x000f,0x0000,1:1 CONFIG3L_unused=0x00 CONFIG3H_unused=0x00 CONFIG3H~1=CCP2MX,0x01,CCP2 Mux CONFIG3H~2=ECCPXM,0x02,ECCP Mux CONFIG3H~1~1=0x01,0x01,ECCP2 I/O Muxed With RC1 CONFIG3H~1~2=0x01,0x00,ECCP2 IP Muxed With RE7 CONFIG3H~2~1=0x02,0x02,P1B/P1C On RE6/RE5, P3B/P3C On RE4/RE3 CONFIG3H~2~2=0x02,0x00,P1B/P1C On RH7/RH6, P3B/P3C Onto RH5/RH4 CONFIG4L_unused=0x00 CONFIG4H_unused=0x00 erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F87J11] pgmmem=0x0 ~pgmmem=0x1fff7 cfgmem=0x1fff8 ~cfgmem=0x1ffff userid= ~userid= eedata=0x00 ~eedata=0xf5f devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x4520 configslots=8 0x1fff8=CONFIG1L 0x1fff9=CONFIG1H 0x1fffa=CONFIG2L 0x1fffb=CONFIG2H 0x1fffc=CONFIG3L 0x1fffd=CONFIG3H 0x1fffe=CONFIG4L 0x1ffff=CONFIG4H CONFIG1L_unused=0x00 CONFIG1L~1=WDTEN,0x01,Watchdog Timer Enable CONFIG1L~2=STVREN,0x0E,PLL Configuration CONFIG1L~3=ENHCPU,0x20,Stack Overflow Reset CONFIG1L~4=EXTCPU,0x40,Extended CPU CONFIG1L~5=BACKBUG,0x80,Background Debug CONFIG1L~1~1=0x01,0x01,Enabled CONFIG1L~1~2=0x01,0x00,Disabled CONFIG1L~2~1=0x0E,0x0E,No Divide (4MHz input) CONFIG1L~2~2=0x0E,0x0C,Divide by 2 (8MHz input) CONFIG1L~2~3=0x0E,0x0A,Divide by 3 (12MHz input) CONFIG1L~2~4=0x0E,0x08,Divide by 4 (16MHz input) CONFIG1L~2~5=0x0E,0x06,Divide by 5 (20MHz input) CONFIG1L~2~6=0x0E,0x04,Divide by 6 (24MHz input) CONFIG1L~2~7=0x0E,0x02,Divide by 10 (40MHz input) CONFIG1L~2~8=0x0E,0x00,Divide by 12 (48MHz input) CONFIG1L~3~1=0x20,0x20,Enabled CONFIG1L~3~2=0x20,0x00,Disabled CONFIG1L~4~1=0x40,0x40,Enabled CONFIG1L~4~2=0x40,0x00,Disabled CONFIG1L~5~1=0x80,0x80,Disabled CONFIG1L~5~2=0x80,0x00,Enabled CONFIG1H_unused=0x00 CONFIG1H~1=CPDIV,0x3,CPU Clock Divider CONFIG1H~2=CP_0,0x4,Code Protection CONFIG1H~1~1=0x3,0x3,No divide CONFIG1H~1~2=0x3,0x2,Divide by 2 CONFIG1H~1~3=0x3,0x1,Divide by 3 CONFIG1H~1~4=0x3,0x0,Divide by 6 CONFIG1H~2~1=0x4,0x4,Disabled CONFIG1H~2~2=0x4,0x00,Enabled CONFIG2L_unused=0x00 CONFIG2L~1=FOSC,0x07,Oscillator CONFIG2L~2=FCMEN,0x40,Fail Safe Monitor Clock Enable CONFIG2L~3=IESO,0x80,Internal External Switch Over Enable CONFIG2L~1~1=0x07,0x07,EC+PLL(CLKO-RA6) USB-EC+PLL CONFIG2L~1~2=0x07,0x06,EC(CLKO-RA6) USB-EC CONFIG2L~1~3=0x07,0x05,HS+PLL USB-HS+PLL CONFIG2L~1~4=0x07,0x04,HS USB-HS CONFIG2L~1~5=0x07,0x03,INTOSC EC+PLL Osc with CLKOUT CONFIG2L~1~6=0x07,0x02,INTOSC EC Osc with CLKOUT CONFIG2L~1~7=0x07,0x01,INTOSC HS+PLL Osc CONFIG2L~1~8=0x07,0x00,INTOSC HS Osc CONFIG2L~2~1=0x40,0x40,Enabled CONFIG2L~2~2=0x40,0x00,Disabled CONFIG2L~3~1=0x80,0x80,Enabled CONFIG2L~3~2=0x80,0x00,Disabled CONFIG2H_unused=0x00 CONFIG2H~1=WDTPS,0x0f,Watchdog Timer Postscale CONFIG2H~1~1=0x000f,0x000f,1:32,768 CONFIG2H~1~2=0x000f,0x000e,1:16,384 CONFIG2H~1~3=0x000f,0x000d,1:8,192 CONFIG2H~1~4=0x000f,0x000c,1:4,096 CONFIG2H~1~5=0x000f,0x000b,1:2,048 CONFIG2H~1~6=0x000f,0x000a,1:1,024 CONFIG2H~1~7=0x000f,0x0009,1:512 CONFIG2H~1~8=0x000f,0x0008,1:256 CONFIG2H~1~9=0x000f,0x0007,1:128 CONFIG2H~1~10=0x000f,0x0006,1:64 CONFIG2H~1~11=0x000f,0x0005,1:32 CONFIG2H~1~12=0x000f,0x0004,1:16 CONFIG2H~1~13=0x000f,0x0003,1:8 CONFIG2H~1~14=0x000f,0x0002,1:4 CONFIG2H~1~15=0x000f,0x0001,1:2 CONFIG2H~1~16=0x000f,0x0000,1:1 CONFIG3L_unused=0x00 CONFIG3H_unused=0x00 CONFIG3H~1=CCP2MX,0x01,CCP2 Mux CONFIG3H~2=ECCPXM,0x02,ECCP Mux CONFIG3H~1~1=0x01,0x01,ECCP2 I/O Muxed With RC1 CONFIG3H~1~2=0x01,0x00,ECCP2 IP Muxed With RE7 CONFIG3H~2~1=0x02,0x02,P1B/P1C On RE6/RE5, P3B/P3C On RE4/RE3 CONFIG3H~2~2=0x02,0x00,P1B/P1C On RH7/RH6, P3B/P3C Onto RH5/RH4 CONFIG4L_unused=0x00 CONFIG4H_unused=0x00 erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F87J50] pgmmem=0x0 ~pgmmem=0x1fff7 cfgmem=0x1fff8 ~cfgmem=0x1ffff userid= ~userid= eedata=0x00 ~eedata=0xf5f devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x4220 configslots=8 0x1fff8=CONFIG1L 0x1fff9=CONFIG1H 0x1fffa=CONFIG2L 0x1fffb=CONFIG2H 0x1fffc=CONFIG3L 0x1fffd=CONFIG3H 0x1fffe=CONFIG4L 0x1ffff=CONFIG4H CONFIG1L_unused=0x00 CONFIG1L~1=WDTEN,0x01,Watchdog Timer Enable CONFIG1L~2=STVREN,0x0E,PLL Configuration CONFIG1L~3=ENHCPU,0x20,Stack Overflow Reset CONFIG1L~4=EXTCPU,0x40,Extended CPU CONFIG1L~5=BACKBUG,0x80,Background Debug CONFIG1L~1~1=0x01,0x01,Enabled CONFIG1L~1~2=0x01,0x00,Disabled CONFIG1L~2~1=0x0E,0x0E,No Divide (4MHz input) CONFIG1L~2~2=0x0E,0x0C,Divide by 2 (8MHz input) CONFIG1L~2~3=0x0E,0x0A,Divide by 3 (12MHz input) CONFIG1L~2~4=0x0E,0x08,Divide by 4 (16MHz input) CONFIG1L~2~5=0x0E,0x06,Divide by 5 (20MHz input) CONFIG1L~2~6=0x0E,0x04,Divide by 6 (24MHz input) CONFIG1L~2~7=0x0E,0x02,Divide by 10 (40MHz input) CONFIG1L~2~8=0x0E,0x00,Divide by 12 (48MHz input) CONFIG1L~3~1=0x20,0x20,Enabled CONFIG1L~3~2=0x20,0x00,Disabled CONFIG1L~4~1=0x40,0x40,Enabled CONFIG1L~4~2=0x40,0x00,Disabled CONFIG1L~5~1=0x80,0x80,Disabled CONFIG1L~5~2=0x80,0x00,Enabled CONFIG1H_unused=0x00 CONFIG1H~1=CPDIV,0x3,CPU Clock Divider CONFIG1H~2=CP_0,0x4,Code Protection CONFIG1H~1~1=0x3,0x3,No divide CONFIG1H~1~2=0x3,0x2,Divide by 2 CONFIG1H~1~3=0x3,0x1,Divide by 3 CONFIG1H~1~4=0x3,0x0,Divide by 6 CONFIG1H~2~1=0x4,0x4,Disabled CONFIG1H~2~2=0x4,0x00,Enabled CONFIG2L_unused=0x00 CONFIG2L~1=FOSC,0x07,Oscillator CONFIG2L~2=FCMEN,0x40,Fail Safe Monitor Clock Enable CONFIG2L~3=IESO,0x80,Internal External Switch Over Enable CONFIG2L~1~1=0x07,0x07,EC+PLL(CLKO-RA6) USB-EC+PLL CONFIG2L~1~2=0x07,0x06,EC(CLKO-RA6) USB-EC CONFIG2L~1~3=0x07,0x05,HS+PLL USB-HS+PLL CONFIG2L~1~4=0x07,0x04,HS USB-HS CONFIG2L~1~5=0x07,0x03,INTOSC EC+PLL Osc with CLKOUT CONFIG2L~1~6=0x07,0x02,INTOSC EC Osc with CLKOUT CONFIG2L~1~7=0x07,0x01,INTOSC HS+PLL Osc CONFIG2L~1~8=0x07,0x00,INTOSC HS Osc CONFIG2L~2~1=0x40,0x40,Enabled CONFIG2L~2~2=0x40,0x00,Disabled CONFIG2L~3~1=0x80,0x80,Enabled CONFIG2L~3~2=0x80,0x00,Disabled CONFIG2H_unused=0x00 CONFIG2H~1=WDTPS,0x0f,Watchdog Timer Postscale CONFIG2H~1~1=0x000f,0x000f,1:32,768 CONFIG2H~1~2=0x000f,0x000e,1:16,384 CONFIG2H~1~3=0x000f,0x000d,1:8,192 CONFIG2H~1~4=0x000f,0x000c,1:4,096 CONFIG2H~1~5=0x000f,0x000b,1:2,048 CONFIG2H~1~6=0x000f,0x000a,1:1,024 CONFIG2H~1~7=0x000f,0x0009,1:512 CONFIG2H~1~8=0x000f,0x0008,1:256 CONFIG2H~1~9=0x000f,0x0007,1:128 CONFIG2H~1~10=0x000f,0x0006,1:64 CONFIG2H~1~11=0x000f,0x0005,1:32 CONFIG2H~1~12=0x000f,0x0004,1:16 CONFIG2H~1~13=0x000f,0x0003,1:8 CONFIG2H~1~14=0x000f,0x0002,1:4 CONFIG2H~1~15=0x000f,0x0001,1:2 CONFIG2H~1~16=0x000f,0x0000,1:1 CONFIG3L_unused=0x00 CONFIG3H_unused=0x00 CONFIG3H~1=CCP2MX,0x01,CCP2 Mux CONFIG3H~2=ECCPXM,0x02,ECCP Mux CONFIG3H~1~1=0x01,0x01,ECCP2 I/O Muxed With RC1 CONFIG3H~1~2=0x01,0x00,ECCP2 IP Muxed With RE7 CONFIG3H~2~1=0x02,0x02,P1B/P1C On RE6/RE5, P3B/P3C On RE4/RE3 CONFIG3H~2~2=0x02,0x00,P1B/P1C On RH7/RH6, P3B/P3C Onto RH5/RH4 CONFIG4L_unused=0x00 CONFIG4H_unused=0x00 erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F87J72] pgmmem=0x0 ~pgmmem=0x1fff7 cfgmem=0x1fff8 ~cfgmem=0x1ffff userid= ~userid= eedata=0x00 ~eedata=0xf5f devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x5060 configslots=8 0x1fff8=CONFIG1L 0x1fff9=CONFIG1H 0x1fffa=CONFIG2L 0x1fffb=CONFIG2H 0x1fffc=CONFIG3L 0x1fffd=CONFIG3H 0x1fffe=CONFIG4L 0x1ffff=CONFIG4H CONFIG1L_unused=0x00 CONFIG1L~1=WDTEN,0x01,Watchdog Timer Enable CONFIG1L~2=STVREN,0x0E,PLL Configuration CONFIG1L~3=ENHCPU,0x20,Stack Overflow Reset CONFIG1L~4=EXTCPU,0x40,Extended CPU CONFIG1L~5=BACKBUG,0x80,Background Debug CONFIG1L~1~1=0x01,0x01,Enabled CONFIG1L~1~2=0x01,0x00,Disabled CONFIG1L~2~1=0x0E,0x0E,No Divide (4MHz input) CONFIG1L~2~2=0x0E,0x0C,Divide by 2 (8MHz input) CONFIG1L~2~3=0x0E,0x0A,Divide by 3 (12MHz input) CONFIG1L~2~4=0x0E,0x08,Divide by 4 (16MHz input) CONFIG1L~2~5=0x0E,0x06,Divide by 5 (20MHz input) CONFIG1L~2~6=0x0E,0x04,Divide by 6 (24MHz input) CONFIG1L~2~7=0x0E,0x02,Divide by 10 (40MHz input) CONFIG1L~2~8=0x0E,0x00,Divide by 12 (48MHz input) CONFIG1L~3~1=0x20,0x20,Enabled CONFIG1L~3~2=0x20,0x00,Disabled CONFIG1L~4~1=0x40,0x40,Enabled CONFIG1L~4~2=0x40,0x00,Disabled CONFIG1L~5~1=0x80,0x80,Disabled CONFIG1L~5~2=0x80,0x00,Enabled CONFIG1H_unused=0x00 CONFIG1H~1=CPDIV,0x3,CPU Clock Divider CONFIG1H~2=CP_0,0x4,Code Protection CONFIG1H~1~1=0x3,0x3,No divide CONFIG1H~1~2=0x3,0x2,Divide by 2 CONFIG1H~1~3=0x3,0x1,Divide by 3 CONFIG1H~1~4=0x3,0x0,Divide by 6 CONFIG1H~2~1=0x4,0x4,Disabled CONFIG1H~2~2=0x4,0x00,Enabled CONFIG2L_unused=0x00 CONFIG2L~1=FOSC,0x07,Oscillator CONFIG2L~2=FCMEN,0x40,Fail Safe Monitor Clock Enable CONFIG2L~3=IESO,0x80,Internal External Switch Over Enable CONFIG2L~1~1=0x07,0x07,EC+PLL(CLKO-RA6) USB-EC+PLL CONFIG2L~1~2=0x07,0x06,EC(CLKO-RA6) USB-EC CONFIG2L~1~3=0x07,0x05,HS+PLL USB-HS+PLL CONFIG2L~1~4=0x07,0x04,HS USB-HS CONFIG2L~1~5=0x07,0x03,INTOSC EC+PLL Osc with CLKOUT CONFIG2L~1~6=0x07,0x02,INTOSC EC Osc with CLKOUT CONFIG2L~1~7=0x07,0x01,INTOSC HS+PLL Osc CONFIG2L~1~8=0x07,0x00,INTOSC HS Osc CONFIG2L~2~1=0x40,0x40,Enabled CONFIG2L~2~2=0x40,0x00,Disabled CONFIG2L~3~1=0x80,0x80,Enabled CONFIG2L~3~2=0x80,0x00,Disabled CONFIG2H_unused=0x00 CONFIG2H~1=WDTPS,0x0f,Watchdog Timer Postscale CONFIG2H~1~1=0x000f,0x000f,1:32,768 CONFIG2H~1~2=0x000f,0x000e,1:16,384 CONFIG2H~1~3=0x000f,0x000d,1:8,192 CONFIG2H~1~4=0x000f,0x000c,1:4,096 CONFIG2H~1~5=0x000f,0x000b,1:2,048 CONFIG2H~1~6=0x000f,0x000a,1:1,024 CONFIG2H~1~7=0x000f,0x0009,1:512 CONFIG2H~1~8=0x000f,0x0008,1:256 CONFIG2H~1~9=0x000f,0x0007,1:128 CONFIG2H~1~10=0x000f,0x0006,1:64 CONFIG2H~1~11=0x000f,0x0005,1:32 CONFIG2H~1~12=0x000f,0x0004,1:16 CONFIG2H~1~13=0x000f,0x0003,1:8 CONFIG2H~1~14=0x000f,0x0002,1:4 CONFIG2H~1~15=0x000f,0x0001,1:2 CONFIG2H~1~16=0x000f,0x0000,1:1 CONFIG3L_unused=0x00 CONFIG3H_unused=0x00 CONFIG3H~1=CCP2MX,0x01,CCP2 Mux CONFIG3H~2=ECCPXM,0x02,ECCP Mux CONFIG3H~1~1=0x01,0x01,ECCP2 I/O Muxed With RC1 CONFIG3H~1~2=0x01,0x00,ECCP2 IP Muxed With RE7 CONFIG3H~2~1=0x02,0x02,P1B/P1C On RE6/RE5, P3B/P3C On RE4/RE3 CONFIG3H~2~2=0x02,0x00,P1B/P1C On RH7/RH6, P3B/P3C Onto RH5/RH4 CONFIG4L_unused=0x00 CONFIG4H_unused=0x00 erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F87J90] pgmmem=0x0 ~pgmmem=0x1fff7 cfgmem=0x1fff8 ~cfgmem=0x1ffff userid= ~userid= eedata=0x00 ~eedata=0xf5f devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x50A0 configslots=8 0x1fff8=CONFIG1L 0x1fff9=CONFIG1H 0x1fffa=CONFIG2L 0x1fffb=CONFIG2H 0x1fffc=CONFIG3L 0x1fffd=CONFIG3H 0x1fffe=CONFIG4L 0x1ffff=CONFIG4H CONFIG1L_unused=0x00 CONFIG1L~1=WDTEN,0x01,Watchdog Timer Enable CONFIG1L~2=STVREN,0x0E,PLL Configuration CONFIG1L~3=ENHCPU,0x20,Stack Overflow Reset CONFIG1L~4=EXTCPU,0x40,Extended CPU CONFIG1L~5=BACKBUG,0x80,Background Debug CONFIG1L~1~1=0x01,0x01,Enabled CONFIG1L~1~2=0x01,0x00,Disabled CONFIG1L~2~1=0x0E,0x0E,No Divide (4MHz input) CONFIG1L~2~2=0x0E,0x0C,Divide by 2 (8MHz input) CONFIG1L~2~3=0x0E,0x0A,Divide by 3 (12MHz input) CONFIG1L~2~4=0x0E,0x08,Divide by 4 (16MHz input) CONFIG1L~2~5=0x0E,0x06,Divide by 5 (20MHz input) CONFIG1L~2~6=0x0E,0x04,Divide by 6 (24MHz input) CONFIG1L~2~7=0x0E,0x02,Divide by 10 (40MHz input) CONFIG1L~2~8=0x0E,0x00,Divide by 12 (48MHz input) CONFIG1L~3~1=0x20,0x20,Enabled CONFIG1L~3~2=0x20,0x00,Disabled CONFIG1L~4~1=0x40,0x40,Enabled CONFIG1L~4~2=0x40,0x00,Disabled CONFIG1L~5~1=0x80,0x80,Disabled CONFIG1L~5~2=0x80,0x00,Enabled CONFIG1H_unused=0x00 CONFIG1H~1=CPDIV,0x3,CPU Clock Divider CONFIG1H~2=CP_0,0x4,Code Protection CONFIG1H~1~1=0x3,0x3,No divide CONFIG1H~1~2=0x3,0x2,Divide by 2 CONFIG1H~1~3=0x3,0x1,Divide by 3 CONFIG1H~1~4=0x3,0x0,Divide by 6 CONFIG1H~2~1=0x4,0x4,Disabled CONFIG1H~2~2=0x4,0x00,Enabled CONFIG2L_unused=0x00 CONFIG2L~1=FOSC,0x07,Oscillator CONFIG2L~2=FCMEN,0x40,Fail Safe Monitor Clock Enable CONFIG2L~3=IESO,0x80,Internal External Switch Over Enable CONFIG2L~1~1=0x07,0x07,EC+PLL(CLKO-RA6) USB-EC+PLL CONFIG2L~1~2=0x07,0x06,EC(CLKO-RA6) USB-EC CONFIG2L~1~3=0x07,0x05,HS+PLL USB-HS+PLL CONFIG2L~1~4=0x07,0x04,HS USB-HS CONFIG2L~1~5=0x07,0x03,INTOSC EC+PLL Osc with CLKOUT CONFIG2L~1~6=0x07,0x02,INTOSC EC Osc with CLKOUT CONFIG2L~1~7=0x07,0x01,INTOSC HS+PLL Osc CONFIG2L~1~8=0x07,0x00,INTOSC HS Osc CONFIG2L~2~1=0x40,0x40,Enabled CONFIG2L~2~2=0x40,0x00,Disabled CONFIG2L~3~1=0x80,0x80,Enabled CONFIG2L~3~2=0x80,0x00,Disabled CONFIG2H_unused=0x00 CONFIG2H~1=WDTPS,0x0f,Watchdog Timer Postscale CONFIG2H~1~1=0x000f,0x000f,1:32,768 CONFIG2H~1~2=0x000f,0x000e,1:16,384 CONFIG2H~1~3=0x000f,0x000d,1:8,192 CONFIG2H~1~4=0x000f,0x000c,1:4,096 CONFIG2H~1~5=0x000f,0x000b,1:2,048 CONFIG2H~1~6=0x000f,0x000a,1:1,024 CONFIG2H~1~7=0x000f,0x0009,1:512 CONFIG2H~1~8=0x000f,0x0008,1:256 CONFIG2H~1~9=0x000f,0x0007,1:128 CONFIG2H~1~10=0x000f,0x0006,1:64 CONFIG2H~1~11=0x000f,0x0005,1:32 CONFIG2H~1~12=0x000f,0x0004,1:16 CONFIG2H~1~13=0x000f,0x0003,1:8 CONFIG2H~1~14=0x000f,0x0002,1:4 CONFIG2H~1~15=0x000f,0x0001,1:2 CONFIG2H~1~16=0x000f,0x0000,1:1 CONFIG3L_unused=0x00 CONFIG3H_unused=0x00 CONFIG3H~1=CCP2MX,0x01,CCP2 Mux CONFIG3H~2=ECCPXM,0x02,ECCP Mux CONFIG3H~1~1=0x01,0x01,ECCP2 I/O Muxed With RC1 CONFIG3H~1~2=0x01,0x00,ECCP2 IP Muxed With RE7 CONFIG3H~2~1=0x02,0x02,P1B/P1C On RE6/RE5, P3B/P3C On RE4/RE3 CONFIG3H~2~2=0x02,0x00,P1B/P1C On RH7/RH6, P3B/P3C Onto RH5/RH4 CONFIG4L_unused=0x00 CONFIG4H_unused=0x00 erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F87J93] pgmmem=0x0 ~pgmmem=0x1fff7 cfgmem=0x1fff8 ~cfgmem=0x1ffff userid= ~userid= eedata=0x00 ~eedata=0xf5f devid=0x3FFFFE ~devid=0x3FFFFF idmask=0xFFE0 id=0x50E0 configslots=8 0x1fff8=CONFIG1L 0x1fff9=CONFIG1H 0x1fffa=CONFIG2L 0x1fffb=CONFIG2H 0x1fffc=CONFIG3L 0x1fffd=CONFIG3H 0x1fffe=CONFIG4L 0x1ffff=CONFIG4H CONFIG1L_unused=0x00 CONFIG1L~1=WDTEN,0x01,Watchdog Timer Enable CONFIG1L~2=STVREN,0x0E,PLL Configuration CONFIG1L~3=ENHCPU,0x20,Stack Overflow Reset CONFIG1L~4=EXTCPU,0x40,Extended CPU CONFIG1L~5=BACKBUG,0x80,Background Debug CONFIG1L~1~1=0x01,0x01,Enabled CONFIG1L~1~2=0x01,0x00,Disabled CONFIG1L~2~1=0x0E,0x0E,No Divide (4MHz input) CONFIG1L~2~2=0x0E,0x0C,Divide by 2 (8MHz input) CONFIG1L~2~3=0x0E,0x0A,Divide by 3 (12MHz input) CONFIG1L~2~4=0x0E,0x08,Divide by 4 (16MHz input) CONFIG1L~2~5=0x0E,0x06,Divide by 5 (20MHz input) CONFIG1L~2~6=0x0E,0x04,Divide by 6 (24MHz input) CONFIG1L~2~7=0x0E,0x02,Divide by 10 (40MHz input) CONFIG1L~2~8=0x0E,0x00,Divide by 12 (48MHz input) CONFIG1L~3~1=0x20,0x20,Enabled CONFIG1L~3~2=0x20,0x00,Disabled CONFIG1L~4~1=0x40,0x40,Enabled CONFIG1L~4~2=0x40,0x00,Disabled CONFIG1L~5~1=0x80,0x80,Disabled CONFIG1L~5~2=0x80,0x00,Enabled CONFIG1H_unused=0x00 CONFIG1H~1=CPDIV,0x3,CPU Clock Divider CONFIG1H~2=CP_0,0x4,Code Protection CONFIG1H~1~1=0x3,0x3,No divide CONFIG1H~1~2=0x3,0x2,Divide by 2 CONFIG1H~1~3=0x3,0x1,Divide by 3 CONFIG1H~1~4=0x3,0x0,Divide by 6 CONFIG1H~2~1=0x4,0x4,Disabled CONFIG1H~2~2=0x4,0x00,Enabled CONFIG2L_unused=0x00 CONFIG2L~1=FOSC,0x07,Oscillator CONFIG2L~2=FCMEN,0x40,Fail Safe Monitor Clock Enable CONFIG2L~3=IESO,0x80,Internal External Switch Over Enable CONFIG2L~1~1=0x07,0x07,EC+PLL(CLKO-RA6) USB-EC+PLL CONFIG2L~1~2=0x07,0x06,EC(CLKO-RA6) USB-EC CONFIG2L~1~3=0x07,0x05,HS+PLL USB-HS+PLL CONFIG2L~1~4=0x07,0x04,HS USB-HS CONFIG2L~1~5=0x07,0x03,INTOSC EC+PLL Osc with CLKOUT CONFIG2L~1~6=0x07,0x02,INTOSC EC Osc with CLKOUT CONFIG2L~1~7=0x07,0x01,INTOSC HS+PLL Osc CONFIG2L~1~8=0x07,0x00,INTOSC HS Osc CONFIG2L~2~1=0x40,0x40,Enabled CONFIG2L~2~2=0x40,0x00,Disabled CONFIG2L~3~1=0x80,0x80,Enabled CONFIG2L~3~2=0x80,0x00,Disabled CONFIG2H_unused=0x00 CONFIG2H~1=WDTPS,0x0f,Watchdog Timer Postscale CONFIG2H~1~1=0x000f,0x000f,1:32,768 CONFIG2H~1~2=0x000f,0x000e,1:16,384 CONFIG2H~1~3=0x000f,0x000d,1:8,192 CONFIG2H~1~4=0x000f,0x000c,1:4,096 CONFIG2H~1~5=0x000f,0x000b,1:2,048 CONFIG2H~1~6=0x000f,0x000a,1:1,024 CONFIG2H~1~7=0x000f,0x0009,1:512 CONFIG2H~1~8=0x000f,0x0008,1:256 CONFIG2H~1~9=0x000f,0x0007,1:128 CONFIG2H~1~10=0x000f,0x0006,1:64 CONFIG2H~1~11=0x000f,0x0005,1:32 CONFIG2H~1~12=0x000f,0x0004,1:16 CONFIG2H~1~13=0x000f,0x0003,1:8 CONFIG2H~1~14=0x000f,0x0002,1:4 CONFIG2H~1~15=0x000f,0x0001,1:2 CONFIG2H~1~16=0x000f,0x0000,1:1 CONFIG3L_unused=0x00 CONFIG3H_unused=0x00 CONFIG3H~1=CCP2MX,0x01,CCP2 Mux CONFIG3H~2=ECCPXM,0x02,ECCP Mux CONFIG3H~1~1=0x01,0x01,ECCP2 I/O Muxed With RC1 CONFIG3H~1~2=0x01,0x00,ECCP2 IP Muxed With RE7 CONFIG3H~2~1=0x02,0x02,P1B/P1C On RE6/RE5, P3B/P3C On RE4/RE3 CONFIG3H~2~2=0x02,0x00,P1B/P1C On RH7/RH6, P3B/P3C Onto RH5/RH4 CONFIG4L_unused=0x00 CONFIG4H_unused=0x00 erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F67J60] pgmmem=0x20000 ~pgmmem=0x1fffff cfgmem=0x1fff8 ~cfgmem=0x1ffff userid= ~userid= eedata= ~eedata= devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0x1f20 configslots=8 0x1fff8=CONFIG1L 0x1fff9=CONFIG1H 0x1fffa=CONFIG2L 0x1fffb=CONFIG2H 0x1fffc=CONFIG3L 0x1fffd=CONFIG3H 0x1fffe= 0x1ffff= CONFIG1L_unused=0x0 CONFIG1L~1=WDTEN,0x1,Watchdog Timer Enable CONFIG1L~2=STVREN,0x20,Stack Overflow Reset Enable CONFIG1L~3=XINST,0x40,Extended Instruction Set Enable bit CONFIG1L~4=BACKBUG,0x80,Background Debug CONFIG1L~1~1=0x1,0x1,Enabled CONFIG1L~1~2=0x1,0x0,Disabled CONFIG1L~2~1=0x20,0x20,Enabled CONFIG1L~2~2=0x20,0x0,Disabled CONFIG1L~3~1=0x40,0x40,Enabled CONFIG1L~3~2=0x40,0x0,Disabled CONFIG1L~4~1=0x80,0x80,Disabled CONFIG1L~4~2=0x80,0x0,Enabled CONFIG1H_unused=0x0 CONFIG1H~1=CP_0,0x4,Code Protect 000000-01FFFF CONFIG1H~2=RESERVED,0xf0,RESERVED CONFIG1H~1~1=0x4,0x4,Disabled CONFIG1H~1~2=0x4,0x0,Enabled CONFIG1H~2~1=0xf0,0x0,RESERVED CONFIG2L_unused=0x0 CONFIG2L~1=FOSC,0x7,Oscillator CONFIG2L~2=FCMEN,0x40,Fail Safe Monitor Clock Enable CONFIG2L~3=IESO,0x80,Internal External Switch Over Enable CONFIG2L~1~1=0x7,0x7,OSC1/OSC2 as Primary, EC+PLL Osc with CLKOUT Function CONFIG2L~1~2=0x7,0x6,OSC1/OSC2 as Primary, EC Osc with CLKOUT Function CONFIG2L~1~3=0x7,0x5,OSC1/OSC2 as primary, HS+PLL Osc CONFIG2L~1~4=0x7,0x4,OSC1/OSC2 as primary, HS Osc CONFIG2L~1~5=0x7,0x3,INTOSC as Primary, EC+PLL Osc with CLKOUT CONFIG2L~1~6=0x7,0x2,INTOSC as Primary, EC Osc with CLKOUT CONFIG2L~1~7=0x7,0x1,INTOSC as Primary, HS+PLL Osc CONFIG2L~1~8=0x7,0x0,INTOSC as Primary, HS Osc CONFIG2L~2~1=0x40,0x40,Enabled CONFIG2L~2~2=0x40,0x0,Disabled CONFIG2L~3~1=0x80,0x80,Enabled CONFIG2L~3~2=0x80,0x0,Disabled CONFIG2H_unused=0x0 CONFIG2H~1=WDTPS,0xf,Watchdog Timer Postscale CONFIG2H~2=RESERVED,0xf0,RESERVED CONFIG2H~1~1=0xf,0xf,1:32,768 CONFIG2H~1~2=0xf,0xe,1:16,384 CONFIG2H~1~3=0xf,0xd,1:8,192 CONFIG2H~1~4=0xf,0xc,1:4,096 CONFIG2H~1~5=0xf,0xb,1:2,048 CONFIG2H~1~6=0xf,0xa,1:1,024 CONFIG2H~1~7=0xf,0x9,1:512 CONFIG2H~1~8=0xf,0x8,1:256 CONFIG2H~1~9=0xf,0x7,1:128 CONFIG2H~1~10=0xf,0x6,1:64 CONFIG2H~1~11=0xf,0x5,1:32 CONFIG2H~1~12=0xf,0x4,1:16 CONFIG2H~1~13=0xf,0x3,1:8 CONFIG2H~1~14=0xf,0x2,1:4 CONFIG2H~1~15=0xf,0x1,1:2 CONFIG2H~1~16=0xf,0x0,1:1 CONFIG2H~2~1=0xf0,0x0,RESERVED CONFIG3L_unused=0x0 CONFIG3L~1=RES,0xf8,Reserved CONFIG3L~1~1=0xf8,0xf8,maintain these bits as 1 CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MX,0x1,CCP2 Mux CONFIG3H~2=ECCPXM,0x2,ECCP Mux CONFIG3H~3=ETHLED,0x4,Ethernet LED Enable CONFIG3H~4=RESERVED,0xf0,RESERVED CONFIG3H~1~1=0x1,0x1,ECCP2 I/O Muxed With RC1 CONFIG3H~1~2=0x1,0x0,ECCP2 IP Muxed With RE7 CONFIG3H~2~1=0x2,0x2,P1B/P1C On RE6/RE5, P3B/P3C On RE4/RE3 CONFIG3H~2~2=0x2,0x0,P1B/P1C On RH7/RH6, P3B/P3C Onto RH5/RH4 CONFIG3H~3~1=0x4,0x4,LEDA/LEDB On RA0/RA1 With Ethernet, RA0/AN0 Without CONFIG3H~3~2=0x4,0x0,RA0 On RA0/AN0), RA1 On RA1/AN1 CONFIG3H~4~1=0xf0,0x0,RESERVED erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F23K22] pgmmem=0x0 ~pgmmem=0x1fff cfgmem=0x300000 ~cfgmem=0x30000d userid=0x200000 ~userid=0x200007 eedata=0x0 ~eedata=0xff devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0x5740 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000a=CONFIG6L 0x30000b=CONFIG6H 0x30000c=CONFIG7L 0x30000d=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=FOSC,0xf,Oscillator Selection bits CONFIG1H~2=PLLCFG,0x10,4X PLL Enable CONFIG1H~3=PRICLKEN,0x20,Primary clock enable bit CONFIG1H~4=FCMEN,0x40,Fail-Safe Clock Monitor Enable bit CONFIG1H~5=IESO,0x80,Internal/External Oscillator Switchover bit CONFIG1H~1~1=0xe,0xe,111X External RC oscillator, CLKOUT function on OSC2 CONFIG1H~1~2=0xf,0xd,EC oscillator (low power, < 4 MHz) CONFIG1H~1~3=0xf,0xc,EC oscillator, CLKOUT on OSC2 (low power, < 4 MHz) CONFIG1H~1~4=0xf,0xb,EC oscillator (medium power, 4-16 MHz) CONFIG1H~1~5=0xf,0xa,EC oscillator, CLKOUT on OSC2 (medium power, 4-16 MHz) CONFIG1H~1~6=0xf,0x9,Internal oscillator block, CLKOUT function on RA6, port function on RA7 CONFIG1H~1~7=0xf,0x8,Internal oscillator block, port function on RA6 and RA7 CONFIG1H~1~8=0xf,0x7,External RC oscillator, port function on RA6 CONFIG1H~1~9=0xf,0x6,External RC, CLKOUT on OSC2 CONFIG1H~1~10=0xf,0x5,EC oscillator, port function on RA6 (high power, >16 MHz) CONFIG1H~1~11=0xf,0x4,EC oscillator, CLKOUT function on OSC2 (high power, >16 MHz) CONFIG1H~1~12=0xf,0x3,HS oscillator (medium power 4-16 MHz) CONFIG1H~1~13=0xf,0x2,HS oscillator (high power > 16 MHz) CONFIG1H~1~14=0xf,0x1,XT oscillator CONFIG1H~1~15=0xf,0x0,LP oscillator CONFIG1H~2~1=0x10,0x0,Disabled CONFIG1H~2~2=0x10,0x10,Enabled CONFIG1H~3~1=0x20,0x0,Disabled CONFIG1H~3~2=0x20,0x20,Enabled CONFIG1H~4~1=0x40,0x0,Disabled CONFIG1H~4~2=0x40,0x40,Enabled CONFIG1H~5~1=0x80,0x0,Disabled CONFIG1H~5~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PWRTEN,0x1,Power-up Timer Enable bit CONFIG2L~2=BOREN,0x6,Brown-out Reset Enable bits CONFIG2L~3=BORV,0x18,Brown Out Reset Voltage bits CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Brown-out Reset enabled in hardware only (SBOREN is disabled) CONFIG2L~2~2=0x6,0x4,Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) CONFIG2L~2~3=0x6,0x2,Enabled CONFIG2L~2~4=0x6,0x0,Disabled CONFIG2L~3~1=0x18,0x18,VBOR set to 1.90 V nominal CONFIG2L~3~2=0x18,0x10,VBOR set to 2.20 V nominal CONFIG2L~3~3=0x18,0x8,VBOR set to 2.50 V nominal CONFIG2L~3~4=0x18,0x0,VBOR set to 2.85 V nominal CONFIG2H_unused=0x0 CONFIG2H~1=WDTEN,0x3,Watchdog Timer Enable bits CONFIG2H~2=WDTPS,0x3c,Watchdog Timer Postscale Select bits CONFIG2H~1~1=0x3,0x3,Enabled CONFIG2H~1~2=0x3,0x2,WDT is controlled by SWDTEN bit of the WDTCON register CONFIG2H~1~3=0x3,0x1,WDT is disabled in sleep, otherwise enabled. SWDTEN bit has no effect CONFIG2H~1~4=0x3,0x0,Disabled CONFIG2H~2~1=0x3c,0x3c,1:32768 CONFIG2H~2~2=0x3c,0x38,1:16384 CONFIG2H~2~3=0x3c,0x34,1:8192 CONFIG2H~2~4=0x3c,0x30,1:4096 CONFIG2H~2~5=0x3c,0x2c,1:2048 CONFIG2H~2~6=0x3c,0x28,1:1024 CONFIG2H~2~7=0x3c,0x24,1:512 CONFIG2H~2~8=0x3c,0x20,1:256 CONFIG2H~2~9=0x3c,0x1c,1:128 CONFIG2H~2~10=0x3c,0x18,1:64 CONFIG2H~2~11=0x3c,0x14,1:32 CONFIG2H~2~12=0x3c,0x10,1:16 CONFIG2H~2~13=0x3c,0xc,1:8 CONFIG2H~2~14=0x3c,0x8,1:4 CONFIG2H~2~15=0x3c,0x4,1:2 CONFIG2H~2~16=0x3c,0x0,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 MUX bit CONFIG3H~2=PBADEN,0x2,PORTB A/D Enable bit CONFIG3H~3=CCP3MX,0x4,P3A/CCP3 Mux bit CONFIG3H~4=HFOFST,0x8,HFINTOSC Fast Start-up CONFIG3H~5=T3CMX,0x10,Timer3 Clock input mux bit CONFIG3H~6=P2BMX,0x20,ECCP2 B output mux bit CONFIG3H~7=MCLRE,0x80,MCLR Pin Enable bit CONFIG3H~1~1=0x1,0x1,CCP2 input/output is multiplexed with RC1 CONFIG3H~1~2=0x1,0x0,CCP2 input/output is multiplexed with RB3 CONFIG3H~2~1=0x2,0x2,Enabled CONFIG3H~2~2=0x2,0x0,Disabled CONFIG3H~3~1=0x4,0x4,P3A/CCP3 input/output is multiplexed with RB5 CONFIG3H~3~2=0x4,0x0,P3A/CCP3 input/output is mulitplexed with RC6 CONFIG3H~4~1=0x8,0x8,Enabled CONFIG3H~4~2=0x8,0x0,Disabled CONFIG3H~5~1=0x10,0x10,T3CKI is on RC0 CONFIG3H~5~2=0x10,0x0,T3CKI is on RB5 CONFIG3H~6~1=0x20,0x20,P2B is on RB5 CONFIG3H~6~2=0x20,0x0,P2B is on RC0 CONFIG3H~7~1=0x80,0x80,MCLR pin enabled, RE3 input pin disabled CONFIG3H~7~2=0x80,0x0,RE3 input pin enabled; MCLR disabled CONFIG4L_unused=0x0 CONFIG4L~1=STVREN,0x1,Stack Full/Underflow Reset Enable bit CONFIG4L~2=LVP,0x4,Single-Supply ICSP Enable bit CONFIG4L~3=XINST,0x40,Extended Instruction Set Enable bit CONFIG4L~4=DEBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x40,0x40,Enabled CONFIG4L~3~2=0x40,0x0,Disabled CONFIG4L~4~1=0x80,0x80,Disabled CONFIG4L~4~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP0,0x1,Code Protection Block 0 CONFIG5L~2=CP1,0x2,Code Protection Block 1 CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x0,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x0,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPB,0x40,Boot Block Code Protection bit CONFIG5H~2=CPD,0x80,Data EEPROM Code Protection bit CONFIG5H~1~1=0x40,0x40,Disabled CONFIG5H~1~2=0x40,0x0,Enabled CONFIG5H~2~1=0x80,0x80,Disabled CONFIG5H~2~2=0x80,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT0,0x1,Write Protection Block 0 CONFIG6L~2=WRT1,0x2,Write Protection Block 1 CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x0,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x0,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTC,0x20,Configuration Register Write Protection bit CONFIG6H~2=WRTB,0x40,Boot Block Write Protection bit CONFIG6H~3=WRTD,0x80,Data EEPROM Write Protection bit CONFIG6H~1~1=0x20,0x20,Disabled CONFIG6H~1~2=0x20,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x80,0x80,Disabled CONFIG6H~3~2=0x80,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR0,0x1,Table Read Protection Block 0 CONFIG7L~2=EBTR1,0x2,Table Read Protection Block 1 CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x0,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x0,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Boot Block Table Read Protection bit CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F24K22] pgmmem=0x0 ~pgmmem=0x3fff cfgmem=0x300000 ~cfgmem=0x30000d userid=0x200000 ~userid=0x200007 eedata=0x0 ~eedata=0xff devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0x5640 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000a=CONFIG6L 0x30000b=CONFIG6H 0x30000c=CONFIG7L 0x30000d=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=FOSC,0xf,Oscillator Selection bits CONFIG1H~2=PLLCFG,0x10,4X PLL Enable CONFIG1H~3=PRICLKEN,0x20,Primary clock enable bit CONFIG1H~4=FCMEN,0x40,Fail-Safe Clock Monitor Enable bit CONFIG1H~5=IESO,0x80,Internal/External Oscillator Switchover bit CONFIG1H~1~1=0xe,0xe,111X External RC oscillator, CLKOUT function on OSC2 CONFIG1H~1~2=0xf,0xd,EC oscillator (low power, < 4 MHz) CONFIG1H~1~3=0xf,0xc,EC oscillator, CLKOUT on OSC2 (low power, < 4 MHz) CONFIG1H~1~4=0xf,0xb,EC oscillator (medium power, 4-16 MHz) CONFIG1H~1~5=0xf,0xa,EC oscillator, CLKOUT on OSC2 (medium power, 4-16 MHz) CONFIG1H~1~6=0xf,0x9,Internal oscillator block, CLKOUT function on RA6, port function on RA7 CONFIG1H~1~7=0xf,0x8,Internal oscillator block, port function on RA6 and RA7 CONFIG1H~1~8=0xf,0x7,External RC oscillator, port function on RA6 CONFIG1H~1~9=0xf,0x6,External RC, CLKOUT on OSC2 CONFIG1H~1~10=0xf,0x5,EC oscillator, port function on RA6 (high power, >16 MHz) CONFIG1H~1~11=0xf,0x4,EC oscillator, CLKOUT function on OSC2 (high power, >16 MHz) CONFIG1H~1~12=0xf,0x3,HS oscillator (medium power 4-16 MHz) CONFIG1H~1~13=0xf,0x2,HS oscillator (high power > 16 MHz) CONFIG1H~1~14=0xf,0x1,XT oscillator CONFIG1H~1~15=0xf,0x0,LP oscillator CONFIG1H~2~1=0x10,0x0,Disabled CONFIG1H~2~2=0x10,0x10,Enabled CONFIG1H~3~1=0x20,0x0,Disabled CONFIG1H~3~2=0x20,0x20,Enabled CONFIG1H~4~1=0x40,0x0,Disabled CONFIG1H~4~2=0x40,0x40,Enabled CONFIG1H~5~1=0x80,0x0,Disabled CONFIG1H~5~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PWRTEN,0x1,Power-up Timer Enable bit CONFIG2L~2=BOREN,0x6,Brown-out Reset Enable bits CONFIG2L~3=BORV,0x18,Brown Out Reset Voltage bits CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Brown-out Reset enabled in hardware only (SBOREN is disabled) CONFIG2L~2~2=0x6,0x4,Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) CONFIG2L~2~3=0x6,0x2,Enabled CONFIG2L~2~4=0x6,0x0,Disabled CONFIG2L~3~1=0x18,0x18,VBOR set to 1.90 V nominal CONFIG2L~3~2=0x18,0x10,VBOR set to 2.20 V nominal CONFIG2L~3~3=0x18,0x8,VBOR set to 2.50 V nominal CONFIG2L~3~4=0x18,0x0,VBOR set to 2.85 V nominal CONFIG2H_unused=0x0 CONFIG2H~1=WDTEN,0x3,Watchdog Timer Enable bits CONFIG2H~2=WDTPS,0x3c,Watchdog Timer Postscale Select bits CONFIG2H~1~1=0x3,0x3,Enabled CONFIG2H~1~2=0x3,0x2,WDT is controlled by SWDTEN bit of the WDTCON register CONFIG2H~1~3=0x3,0x1,WDT is disabled in sleep, otherwise enabled. SWDTEN bit has no effect CONFIG2H~1~4=0x3,0x0,Disabled CONFIG2H~2~1=0x3c,0x3c,1:32768 CONFIG2H~2~2=0x3c,0x38,1:16384 CONFIG2H~2~3=0x3c,0x34,1:8192 CONFIG2H~2~4=0x3c,0x30,1:4096 CONFIG2H~2~5=0x3c,0x2c,1:2048 CONFIG2H~2~6=0x3c,0x28,1:1024 CONFIG2H~2~7=0x3c,0x24,1:512 CONFIG2H~2~8=0x3c,0x20,1:256 CONFIG2H~2~9=0x3c,0x1c,1:128 CONFIG2H~2~10=0x3c,0x18,1:64 CONFIG2H~2~11=0x3c,0x14,1:32 CONFIG2H~2~12=0x3c,0x10,1:16 CONFIG2H~2~13=0x3c,0xc,1:8 CONFIG2H~2~14=0x3c,0x8,1:4 CONFIG2H~2~15=0x3c,0x4,1:2 CONFIG2H~2~16=0x3c,0x0,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 MUX bit CONFIG3H~2=PBADEN,0x2,PORTB A/D Enable bit CONFIG3H~3=CCP3MX,0x4,P3A/CCP3 Mux bit CONFIG3H~4=HFOFST,0x8,HFINTOSC Fast Start-up CONFIG3H~5=T3CMX,0x10,Timer3 Clock input mux bit CONFIG3H~6=P2BMX,0x20,ECCP2 B output mux bit CONFIG3H~7=MCLRE,0x80,MCLR Pin Enable bit CONFIG3H~1~1=0x1,0x1,CCP2 input/output is multiplexed with RC1 CONFIG3H~1~2=0x1,0x0,CCP2 input/output is multiplexed with RB3 CONFIG3H~2~1=0x2,0x2,Enabled CONFIG3H~2~2=0x2,0x0,Disabled CONFIG3H~3~1=0x4,0x4,P3A/CCP3 input/output is multiplexed with RB5 CONFIG3H~3~2=0x4,0x0,P3A/CCP3 input/output is mulitplexed with RC6 CONFIG3H~4~1=0x8,0x8,Enabled CONFIG3H~4~2=0x8,0x0,Disabled CONFIG3H~5~1=0x10,0x10,T3CKI is on RC0 CONFIG3H~5~2=0x10,0x0,T3CKI is on RB5 CONFIG3H~6~1=0x20,0x20,P2B is on RB5 CONFIG3H~6~2=0x20,0x0,P2B is on RC0 CONFIG3H~7~1=0x80,0x80,MCLR pin enabled, RE3 input pin disabled CONFIG3H~7~2=0x80,0x0,RE3 input pin enabled; MCLR disabled CONFIG4L_unused=0x0 CONFIG4L~1=STVREN,0x1,Stack Full/Underflow Reset Enable bit CONFIG4L~2=LVP,0x4,Single-Supply ICSP Enable bit CONFIG4L~3=XINST,0x40,Extended Instruction Set Enable bit CONFIG4L~4=DEBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x40,0x40,Enabled CONFIG4L~3~2=0x40,0x0,Disabled CONFIG4L~4~1=0x80,0x80,Disabled CONFIG4L~4~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP0,0x1,Code Protection Block 0 CONFIG5L~2=CP1,0x2,Code Protection Block 1 CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x0,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x0,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPB,0x40,Boot Block Code Protection bit CONFIG5H~2=CPD,0x80,Data EEPROM Code Protection bit CONFIG5H~1~1=0x40,0x40,Disabled CONFIG5H~1~2=0x40,0x0,Enabled CONFIG5H~2~1=0x80,0x80,Disabled CONFIG5H~2~2=0x80,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT0,0x1,Write Protection Block 0 CONFIG6L~2=WRT1,0x2,Write Protection Block 1 CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x0,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x0,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTC,0x20,Configuration Register Write Protection bit CONFIG6H~2=WRTB,0x40,Boot Block Write Protection bit CONFIG6H~3=WRTD,0x80,Data EEPROM Write Protection bit CONFIG6H~1~1=0x20,0x20,Disabled CONFIG6H~1~2=0x20,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x80,0x80,Disabled CONFIG6H~3~2=0x80,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR0,0x1,Table Read Protection Block 0 CONFIG7L~2=EBTR1,0x2,Table Read Protection Block 1 CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x0,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x0,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Boot Block Table Read Protection bit CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F25K22] pgmmem=0x0 ~pgmmem=0x7fff cfgmem=0x300000 ~cfgmem=0x30000d userid=0x200000 ~userid=0x200007 eedata=0x0 ~eedata=0xff devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0x5540 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000a=CONFIG6L 0x30000b=CONFIG6H 0x30000c=CONFIG7L 0x30000d=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=FOSC,0xf,Oscillator Selection bits CONFIG1H~2=PLLCFG,0x10,4X PLL Enable CONFIG1H~3=PRICLKEN,0x20,Primary clock enable bit CONFIG1H~4=FCMEN,0x40,Fail-Safe Clock Monitor Enable bit CONFIG1H~5=IESO,0x80,Internal/External Oscillator Switchover bit CONFIG1H~1~1=0xe,0xe,111X External RC oscillator, CLKOUT function on OSC2 CONFIG1H~1~2=0xf,0xd,EC oscillator (low power, < 4 MHz) CONFIG1H~1~3=0xf,0xc,EC oscillator, CLKOUT on OSC2 (low power, < 4 MHz) CONFIG1H~1~4=0xf,0xb,EC oscillator (medium power, 4-16 MHz) CONFIG1H~1~5=0xf,0xa,EC oscillator, CLKOUT on OSC2 (medium power, 4-16 MHz) CONFIG1H~1~6=0xf,0x9,Internal oscillator block, CLKOUT function on RA6, port function on RA7 CONFIG1H~1~7=0xf,0x8,Internal oscillator block, port function on RA6 and RA7 CONFIG1H~1~8=0xf,0x7,External RC oscillator, port function on RA6 CONFIG1H~1~9=0xf,0x6,External RC, CLKOUT on OSC2 CONFIG1H~1~10=0xf,0x5,EC oscillator, port function on RA6 (high power, >16 MHz) CONFIG1H~1~11=0xf,0x4,EC oscillator, CLKOUT function on OSC2 (high power, >16 MHz) CONFIG1H~1~12=0xf,0x3,HS oscillator (medium power 4-16 MHz) CONFIG1H~1~13=0xf,0x2,HS oscillator (high power > 16 MHz) CONFIG1H~1~14=0xf,0x1,XT oscillator CONFIG1H~1~15=0xf,0x0,LP oscillator CONFIG1H~2~1=0x10,0x0,Disabled CONFIG1H~2~2=0x10,0x10,Enabled CONFIG1H~3~1=0x20,0x0,Disabled CONFIG1H~3~2=0x20,0x20,Enabled CONFIG1H~4~1=0x40,0x0,Disabled CONFIG1H~4~2=0x40,0x40,Enabled CONFIG1H~5~1=0x80,0x0,Disabled CONFIG1H~5~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PWRTEN,0x1,Power-up Timer Enable bit CONFIG2L~2=BOREN,0x6,Brown-out Reset Enable bits CONFIG2L~3=BORV,0x18,Brown Out Reset Voltage bits CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Brown-out Reset enabled in hardware only (SBOREN is disabled) CONFIG2L~2~2=0x6,0x4,Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) CONFIG2L~2~3=0x6,0x2,Enabled CONFIG2L~2~4=0x6,0x0,Disabled CONFIG2L~3~1=0x18,0x18,VBOR set to 1.90 V nominal CONFIG2L~3~2=0x18,0x10,VBOR set to 2.20 V nominal CONFIG2L~3~3=0x18,0x8,VBOR set to 2.50 V nominal CONFIG2L~3~4=0x18,0x0,VBOR set to 2.85 V nominal CONFIG2H_unused=0x0 CONFIG2H~1=WDTEN,0x3,Watchdog Timer Enable bits CONFIG2H~2=WDTPS,0x3c,Watchdog Timer Postscale Select bits CONFIG2H~1~1=0x3,0x3,Enabled CONFIG2H~1~2=0x3,0x2,WDT is controlled by SWDTEN bit of the WDTCON register CONFIG2H~1~3=0x3,0x1,WDT is disabled in sleep, otherwise enabled. SWDTEN bit has no effect CONFIG2H~1~4=0x3,0x0,Disabled CONFIG2H~2~1=0x3c,0x3c,1:32768 CONFIG2H~2~2=0x3c,0x38,1:16384 CONFIG2H~2~3=0x3c,0x34,1:8192 CONFIG2H~2~4=0x3c,0x30,1:4096 CONFIG2H~2~5=0x3c,0x2c,1:2048 CONFIG2H~2~6=0x3c,0x28,1:1024 CONFIG2H~2~7=0x3c,0x24,1:512 CONFIG2H~2~8=0x3c,0x20,1:256 CONFIG2H~2~9=0x3c,0x1c,1:128 CONFIG2H~2~10=0x3c,0x18,1:64 CONFIG2H~2~11=0x3c,0x14,1:32 CONFIG2H~2~12=0x3c,0x10,1:16 CONFIG2H~2~13=0x3c,0xc,1:8 CONFIG2H~2~14=0x3c,0x8,1:4 CONFIG2H~2~15=0x3c,0x4,1:2 CONFIG2H~2~16=0x3c,0x0,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 MUX bit CONFIG3H~2=PBADEN,0x2,PORTB A/D Enable bit CONFIG3H~3=CCP3MX,0x4,P3A/CCP3 Mux bit CONFIG3H~4=HFOFST,0x8,HFINTOSC Fast Start-up CONFIG3H~5=T3CMX,0x10,Timer3 Clock input mux bit CONFIG3H~6=P2BMX,0x20,ECCP2 B output mux bit CONFIG3H~7=MCLRE,0x80,MCLR Pin Enable bit CONFIG3H~1~1=0x1,0x1,CCP2 input/output is multiplexed with RC1 CONFIG3H~1~2=0x1,0x0,CCP2 input/output is multiplexed with RB3 CONFIG3H~2~1=0x2,0x2,Enabled CONFIG3H~2~2=0x2,0x0,Disabled CONFIG3H~3~1=0x4,0x4,P3A/CCP3 input/output is multiplexed with RB5 CONFIG3H~3~2=0x4,0x0,P3A/CCP3 input/output is mulitplexed with RC6 CONFIG3H~4~1=0x8,0x8,Enabled CONFIG3H~4~2=0x8,0x0,Disabled CONFIG3H~5~1=0x10,0x10,T3CKI is on RC0 CONFIG3H~5~2=0x10,0x0,T3CKI is on RB5 CONFIG3H~6~1=0x20,0x20,P2B is on RB5 CONFIG3H~6~2=0x20,0x0,P2B is on RC0 CONFIG3H~7~1=0x80,0x80,MCLR pin enabled, RE3 input pin disabled CONFIG3H~7~2=0x80,0x0,RE3 input pin enabled; MCLR disabled CONFIG4L_unused=0x0 CONFIG4L~1=STVREN,0x1,Stack Full/Underflow Reset Enable bit CONFIG4L~2=LVP,0x4,Single-Supply ICSP Enable bit CONFIG4L~3=XINST,0x40,Extended Instruction Set Enable bit CONFIG4L~4=DEBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x40,0x40,Enabled CONFIG4L~3~2=0x40,0x0,Disabled CONFIG4L~4~1=0x80,0x80,Disabled CONFIG4L~4~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP0,0x1,Code Protection Block 0 CONFIG5L~2=CP1,0x2,Code Protection Block 1 CONFIG5L~3=CP2,0x4,Code Protection Block 2 CONFIG5L~4=CP3,0x8,Code Protection Block 3 CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x0,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x0,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x0,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x0,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPB,0x40,Boot Block Code Protection bit CONFIG5H~2=CPD,0x80,Data EEPROM Code Protection bit CONFIG5H~1~1=0x40,0x40,Disabled CONFIG5H~1~2=0x40,0x0,Enabled CONFIG5H~2~1=0x80,0x80,Disabled CONFIG5H~2~2=0x80,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT0,0x1,Write Protection Block 0 CONFIG6L~2=WRT1,0x2,Write Protection Block 1 CONFIG6L~3=WRT2,0x4,Write Protection Block 2 CONFIG6L~4=WRT3,0x8,Write Protection Block 3 CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x0,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x0,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x0,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x0,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTC,0x20,Configuration Register Write Protection bit CONFIG6H~2=WRTB,0x40,Boot Block Write Protection bit CONFIG6H~3=WRTD,0x80,Data EEPROM Write Protection bit CONFIG6H~1~1=0x20,0x20,Disabled CONFIG6H~1~2=0x20,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x80,0x80,Disabled CONFIG6H~3~2=0x80,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR0,0x1,Table Read Protection Block 0 CONFIG7L~2=EBTR1,0x2,Table Read Protection Block 1 CONFIG7L~3=EBTR2,0x4,Table Read Protection Block 2 CONFIG7L~4=EBTR3,0x8,Table Read Protection Block 3 CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x0,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x0,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x0,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x0,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Boot Block Table Read Protection bit CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F26K22] pgmmem=0x0 ~pgmmem=0xffff cfgmem=0x300000 ~cfgmem=0x30000d userid=0x200000 ~userid=0x200007 eedata=0x0 ~eedata=0x3ff devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0x5440 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000a=CONFIG6L 0x30000b=CONFIG6H 0x30000c=CONFIG7L 0x30000d=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=FOSC,0xf,Oscillator Selection bits CONFIG1H~2=PLLCFG,0x10,4X PLL Enable CONFIG1H~3=PRICLKEN,0x20,Primary clock enable bit CONFIG1H~4=FCMEN,0x40,Fail-Safe Clock Monitor Enable bit CONFIG1H~5=IESO,0x80,Internal/External Oscillator Switchover bit CONFIG1H~1~1=0xe,0xe,111X External RC oscillator, CLKOUT function on OSC2 CONFIG1H~1~2=0xf,0xd,EC oscillator (low power, < 4 MHz) CONFIG1H~1~3=0xf,0xc,EC oscillator, CLKOUT on OSC2 (low power, < 4 MHz) CONFIG1H~1~4=0xf,0xb,EC oscillator (medium power, 4-16 MHz) CONFIG1H~1~5=0xf,0xa,EC oscillator, CLKOUT on OSC2 (medium power, 4-16 MHz) CONFIG1H~1~6=0xf,0x9,Internal oscillator block, CLKOUT function on RA6, port function on RA7 CONFIG1H~1~7=0xf,0x8,Internal oscillator block, port function on RA6 and RA7 CONFIG1H~1~8=0xf,0x7,External RC oscillator, port function on RA6 CONFIG1H~1~9=0xf,0x6,External RC, CLKOUT on OSC2 CONFIG1H~1~10=0xf,0x5,EC oscillator, port function on RA6 (high power, >16 MHz) CONFIG1H~1~11=0xf,0x4,EC oscillator, CLKOUT function on OSC2 (high power, >16 MHz) CONFIG1H~1~12=0xf,0x3,HS oscillator (medium power 4-16 MHz) CONFIG1H~1~13=0xf,0x2,HS oscillator (high power > 16 MHz) CONFIG1H~1~14=0xf,0x1,XT oscillator CONFIG1H~1~15=0xf,0x0,LP oscillator CONFIG1H~2~1=0x10,0x0,Disabled CONFIG1H~2~2=0x10,0x10,Enabled CONFIG1H~3~1=0x20,0x0,Disabled CONFIG1H~3~2=0x20,0x20,Enabled CONFIG1H~4~1=0x40,0x0,Disabled CONFIG1H~4~2=0x40,0x40,Enabled CONFIG1H~5~1=0x80,0x0,Disabled CONFIG1H~5~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PWRTEN,0x1,Power-up Timer Enable bit CONFIG2L~2=BOREN,0x6,Brown-out Reset Enable bits CONFIG2L~3=BORV,0x18,Brown Out Reset Voltage bits CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Brown-out Reset enabled in hardware only (SBOREN is disabled) CONFIG2L~2~2=0x6,0x4,Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) CONFIG2L~2~3=0x6,0x2,Enabled CONFIG2L~2~4=0x6,0x0,Disabled CONFIG2L~3~1=0x18,0x18,VBOR set to 1.90 V nominal CONFIG2L~3~2=0x18,0x10,VBOR set to 2.20 V nominal CONFIG2L~3~3=0x18,0x8,VBOR set to 2.50 V nominal CONFIG2L~3~4=0x18,0x0,VBOR set to 2.85 V nominal CONFIG2H_unused=0x0 CONFIG2H~1=WDTEN,0x3,Watchdog Timer Enable bits CONFIG2H~2=WDTPS,0x3c,Watchdog Timer Postscale Select bits CONFIG2H~1~1=0x3,0x3,Enabled CONFIG2H~1~2=0x3,0x2,WDT is controlled by SWDTEN bit of the WDTCON register CONFIG2H~1~3=0x3,0x1,WDT is disabled in sleep, otherwise enabled. SWDTEN bit has no effect CONFIG2H~1~4=0x3,0x0,Disabled CONFIG2H~2~1=0x3c,0x3c,1:32768 CONFIG2H~2~2=0x3c,0x38,1:16384 CONFIG2H~2~3=0x3c,0x34,1:8192 CONFIG2H~2~4=0x3c,0x30,1:4096 CONFIG2H~2~5=0x3c,0x2c,1:2048 CONFIG2H~2~6=0x3c,0x28,1:1024 CONFIG2H~2~7=0x3c,0x24,1:512 CONFIG2H~2~8=0x3c,0x20,1:256 CONFIG2H~2~9=0x3c,0x1c,1:128 CONFIG2H~2~10=0x3c,0x18,1:64 CONFIG2H~2~11=0x3c,0x14,1:32 CONFIG2H~2~12=0x3c,0x10,1:16 CONFIG2H~2~13=0x3c,0xc,1:8 CONFIG2H~2~14=0x3c,0x8,1:4 CONFIG2H~2~15=0x3c,0x4,1:2 CONFIG2H~2~16=0x3c,0x0,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 MUX bit CONFIG3H~2=PBADEN,0x2,PORTB A/D Enable bit CONFIG3H~3=CCP3MX,0x4,P3A/CCP3 Mux bit CONFIG3H~4=HFOFST,0x8,HFINTOSC Fast Start-up CONFIG3H~5=T3CMX,0x10,Timer3 Clock input mux bit CONFIG3H~6=P2BMX,0x20,ECCP2 B output mux bit CONFIG3H~7=MCLRE,0x80,MCLR Pin Enable bit CONFIG3H~1~1=0x1,0x1,CCP2 input/output is multiplexed with RC1 CONFIG3H~1~2=0x1,0x0,CCP2 input/output is multiplexed with RB3 CONFIG3H~2~1=0x2,0x2,Enabled CONFIG3H~2~2=0x2,0x0,Disabled CONFIG3H~3~1=0x4,0x4,P3A/CCP3 input/output is multiplexed with RB5 CONFIG3H~3~2=0x4,0x0,P3A/CCP3 input/output is mulitplexed with RC6 CONFIG3H~4~1=0x8,0x8,Enabled CONFIG3H~4~2=0x8,0x0,Disabled CONFIG3H~5~1=0x10,0x10,T3CKI is on RC0 CONFIG3H~5~2=0x10,0x0,T3CKI is on RB5 CONFIG3H~6~1=0x20,0x20,P2B is on RB5 CONFIG3H~6~2=0x20,0x0,P2B is on RC0 CONFIG3H~7~1=0x80,0x80,MCLR pin enabled, RE3 input pin disabled CONFIG3H~7~2=0x80,0x0,RE3 input pin enabled; MCLR disabled CONFIG4L_unused=0x0 CONFIG4L~1=STVREN,0x1,Stack Full/Underflow Reset Enable bit CONFIG4L~2=LVP,0x4,Single-Supply ICSP Enable bit CONFIG4L~3=XINST,0x40,Extended Instruction Set Enable bit CONFIG4L~4=DEBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x40,0x40,Enabled CONFIG4L~3~2=0x40,0x0,Disabled CONFIG4L~4~1=0x80,0x80,Disabled CONFIG4L~4~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP0,0x1,Code Protection Block 0 CONFIG5L~2=CP1,0x2,Code Protection Block 1 CONFIG5L~3=CP2,0x4,Code Protection Block 2 CONFIG5L~4=CP3,0x8,Code Protection Block 3 CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x0,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x0,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x0,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x0,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPB,0x40,Boot Block Code Protection bit CONFIG5H~2=CPD,0x80,Data EEPROM Code Protection bit CONFIG5H~1~1=0x40,0x40,Disabled CONFIG5H~1~2=0x40,0x0,Enabled CONFIG5H~2~1=0x80,0x80,Disabled CONFIG5H~2~2=0x80,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT0,0x1,Write Protection Block 0 CONFIG6L~2=WRT1,0x2,Write Protection Block 1 CONFIG6L~3=WRT2,0x4,Write Protection Block 2 CONFIG6L~4=WRT3,0x8,Write Protection Block 3 CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x0,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x0,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x0,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x0,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTC,0x20,Configuration Register Write Protection bit CONFIG6H~2=WRTB,0x40,Boot Block Write Protection bit CONFIG6H~3=WRTD,0x80,Data EEPROM Write Protection bit CONFIG6H~1~1=0x20,0x20,Disabled CONFIG6H~1~2=0x20,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x80,0x80,Disabled CONFIG6H~3~2=0x80,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR0,0x1,Table Read Protection Block 0 CONFIG7L~2=EBTR1,0x2,Table Read Protection Block 1 CONFIG7L~3=EBTR2,0x4,Table Read Protection Block 2 CONFIG7L~4=EBTR3,0x8,Table Read Protection Block 3 CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x0,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x0,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x0,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x0,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Boot Block Table Read Protection bit CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F43K22] pgmmem=0x0 ~pgmmem=0x1fff cfgmem=0x300000 ~cfgmem=0x30000d userid=0x200000 ~userid=0x200007 eedata=0x0 ~eedata=0xff devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0x5700 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000a=CONFIG6L 0x30000b=CONFIG6H 0x30000c=CONFIG7L 0x30000d=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=FOSC,0xf,Oscillator Selection bits CONFIG1H~2=PLLCFG,0x10,4X PLL Enable CONFIG1H~3=PRICLKEN,0x20,Primary clock enable bit CONFIG1H~4=FCMEN,0x40,Fail-Safe Clock Monitor Enable bit CONFIG1H~5=IESO,0x80,Internal/External Oscillator Switchover bit CONFIG1H~1~1=0xe,0xe,111X External RC oscillator, CLKOUT function on OSC2 CONFIG1H~1~2=0xf,0xd,EC oscillator (low power, < 4 MHz) CONFIG1H~1~3=0xf,0xc,EC oscillator, CLKOUT on OSC2 (low power, < 4 MHz) CONFIG1H~1~4=0xf,0xb,EC oscillator (medium power, 4-16 MHz) CONFIG1H~1~5=0xf,0xa,EC oscillator, CLKOUT on OSC2 (medium power, 4-16 MHz) CONFIG1H~1~6=0xf,0x9,Internal oscillator block, CLKOUT function on RA6, port function on RA7 CONFIG1H~1~7=0xf,0x8,Internal oscillator block, port function on RA6 and RA7 CONFIG1H~1~8=0xf,0x7,External RC oscillator, port function on RA6 CONFIG1H~1~9=0xf,0x6,External RC, CLKOUT on OSC2 CONFIG1H~1~10=0xf,0x5,EC oscillator, port function on RA6 (high power, >16 MHz) CONFIG1H~1~11=0xf,0x4,EC oscillator, CLKOUT function on OSC2 (high power, >16 MHz) CONFIG1H~1~12=0xf,0x3,HS oscillator (medium power 4-16 MHz) CONFIG1H~1~13=0xf,0x2,HS oscillator (high power > 16 MHz) CONFIG1H~1~14=0xf,0x1,XT oscillator CONFIG1H~1~15=0xf,0x0,LP oscillator CONFIG1H~2~1=0x10,0x0,Disabled CONFIG1H~2~2=0x10,0x10,Enabled CONFIG1H~3~1=0x20,0x0,Disabled CONFIG1H~3~2=0x20,0x20,Enabled CONFIG1H~4~1=0x40,0x0,Disabled CONFIG1H~4~2=0x40,0x40,Enabled CONFIG1H~5~1=0x80,0x0,Disabled CONFIG1H~5~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PWRTEN,0x1,Power-up Timer Enable bit CONFIG2L~2=BOREN,0x6,Brown-out Reset Enable bits CONFIG2L~3=BORV,0x18,Brown Out Reset Voltage bits CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Brown-out Reset enabled in hardware only (SBOREN is disabled) CONFIG2L~2~2=0x6,0x4,Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) CONFIG2L~2~3=0x6,0x2,Enabled CONFIG2L~2~4=0x6,0x0,Disabled CONFIG2L~3~1=0x18,0x18,VBOR set to 1.90 V nominal CONFIG2L~3~2=0x18,0x10,VBOR set to 2.20 V nominal CONFIG2L~3~3=0x18,0x8,VBOR set to 2.50 V nominal CONFIG2L~3~4=0x18,0x0,VBOR set to 2.85 V nominal CONFIG2H_unused=0x0 CONFIG2H~1=WDTEN,0x3,Watchdog Timer Enable bits CONFIG2H~2=WDTPS,0x3c,Watchdog Timer Postscale Select bits CONFIG2H~1~1=0x3,0x3,Enabled CONFIG2H~1~2=0x3,0x2,WDT is controlled by SWDTEN bit of the WDTCON register CONFIG2H~1~3=0x3,0x1,WDT is disabled in sleep, otherwise enabled. SWDTEN bit has no effect CONFIG2H~1~4=0x3,0x0,Disabled CONFIG2H~2~1=0x3c,0x3c,1:32768 CONFIG2H~2~2=0x3c,0x38,1:16384 CONFIG2H~2~3=0x3c,0x34,1:8192 CONFIG2H~2~4=0x3c,0x30,1:4096 CONFIG2H~2~5=0x3c,0x2c,1:2048 CONFIG2H~2~6=0x3c,0x28,1:1024 CONFIG2H~2~7=0x3c,0x24,1:512 CONFIG2H~2~8=0x3c,0x20,1:256 CONFIG2H~2~9=0x3c,0x1c,1:128 CONFIG2H~2~10=0x3c,0x18,1:64 CONFIG2H~2~11=0x3c,0x14,1:32 CONFIG2H~2~12=0x3c,0x10,1:16 CONFIG2H~2~13=0x3c,0xc,1:8 CONFIG2H~2~14=0x3c,0x8,1:4 CONFIG2H~2~15=0x3c,0x4,1:2 CONFIG2H~2~16=0x3c,0x0,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 MUX bit CONFIG3H~2=PBADEN,0x2,PORTB A/D Enable bit CONFIG3H~3=CCP3MX,0x4,P3A/CCP3 Mux bit CONFIG3H~4=HFOFST,0x8,HFINTOSC Fast Start-up CONFIG3H~5=T3CMX,0x10,Timer3 Clock input mux bit CONFIG3H~6=P2BMX,0x20,ECCP2 B output mux bit CONFIG3H~7=MCLRE,0x80,MCLR Pin Enable bit CONFIG3H~1~1=0x1,0x1,CCP2 input/output is multiplexed with RC1 CONFIG3H~1~2=0x1,0x0,CCP2 input/output is multiplexed with RB3 CONFIG3H~2~1=0x2,0x2,Enabled CONFIG3H~2~2=0x2,0x0,Disabled CONFIG3H~3~1=0x4,0x4,P3A/CCP3 input/output is multiplexed with RB5 CONFIG3H~3~2=0x4,0x0,P3A/CCP3 input/output is mulitplexed with RE0 CONFIG3H~4~1=0x8,0x8,Enabled CONFIG3H~4~2=0x8,0x0,Disabled CONFIG3H~5~1=0x10,0x10,T3CKI is on RC0 CONFIG3H~5~2=0x10,0x0,T3CKI is on RB5 CONFIG3H~6~1=0x20,0x20,P2B is on RD2 CONFIG3H~6~2=0x20,0x0,P2B is on RC0 CONFIG3H~7~1=0x80,0x80,MCLR pin enabled, RE3 input pin disabled CONFIG3H~7~2=0x80,0x0,RE3 input pin enabled; MCLR disabled CONFIG4L_unused=0x0 CONFIG4L~1=STVREN,0x1,Stack Full/Underflow Reset Enable bit CONFIG4L~2=LVP,0x4,Single-Supply ICSP Enable bit CONFIG4L~3=XINST,0x40,Extended Instruction Set Enable bit CONFIG4L~4=DEBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x40,0x40,Enabled CONFIG4L~3~2=0x40,0x0,Disabled CONFIG4L~4~1=0x80,0x80,Disabled CONFIG4L~4~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP0,0x1,Code Protection Block 0 CONFIG5L~2=CP1,0x2,Code Protection Block 1 CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x0,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x0,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPB,0x40,Boot Block Code Protection bit CONFIG5H~2=CPD,0x80,Data EEPROM Code Protection bit CONFIG5H~1~1=0x40,0x40,Disabled CONFIG5H~1~2=0x40,0x0,Enabled CONFIG5H~2~1=0x80,0x80,Disabled CONFIG5H~2~2=0x80,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT0,0x1,Write Protection Block 0 CONFIG6L~2=WRT1,0x2,Write Protection Block 1 CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x0,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x0,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTC,0x20,Configuration Register Write Protection bit CONFIG6H~2=WRTB,0x40,Boot Block Write Protection bit CONFIG6H~3=WRTD,0x80,Data EEPROM Write Protection bit CONFIG6H~1~1=0x20,0x20,Disabled CONFIG6H~1~2=0x20,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x80,0x80,Disabled CONFIG6H~3~2=0x80,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR0,0x1,Table Read Protection Block 0 CONFIG7L~2=EBTR1,0x2,Table Read Protection Block 1 CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x0,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x0,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Boot Block Table Read Protection bit CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F44K22] pgmmem=0x0 ~pgmmem=0x3fff cfgmem=0x300000 ~cfgmem=0x30000d userid=0x200000 ~userid=0x200007 eedata=0x0 ~eedata=0xff devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0x5600 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000a=CONFIG6L 0x30000b=CONFIG6H 0x30000c=CONFIG7L 0x30000d=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=FOSC,0xf,Oscillator Selection bits CONFIG1H~2=PLLCFG,0x10,4X PLL Enable CONFIG1H~3=PRICLKEN,0x20,Primary clock enable bit CONFIG1H~4=FCMEN,0x40,Fail-Safe Clock Monitor Enable bit CONFIG1H~5=IESO,0x80,Internal/External Oscillator Switchover bit CONFIG1H~1~1=0xe,0xe,111X External RC oscillator, CLKOUT function on OSC2 CONFIG1H~1~2=0xf,0xd,EC oscillator (low power, < 4 MHz) CONFIG1H~1~3=0xf,0xc,EC oscillator, CLKOUT on OSC2 (low power, < 4 MHz) CONFIG1H~1~4=0xf,0xb,EC oscillator (medium power, 4-16 MHz) CONFIG1H~1~5=0xf,0xa,EC oscillator, CLKOUT on OSC2 (medium power, 4-16 MHz) CONFIG1H~1~6=0xf,0x9,Internal oscillator block, CLKOUT function on RA6, port function on RA7 CONFIG1H~1~7=0xf,0x8,Internal oscillator block, port function on RA6 and RA7 CONFIG1H~1~8=0xf,0x7,External RC oscillator, port function on RA6 CONFIG1H~1~9=0xf,0x6,External RC, CLKOUT on OSC2 CONFIG1H~1~10=0xf,0x5,EC oscillator, port function on RA6 (high power, >16 MHz) CONFIG1H~1~11=0xf,0x4,EC oscillator, CLKOUT function on OSC2 (high power, >16 MHz) CONFIG1H~1~12=0xf,0x3,HS oscillator (medium power 4-16 MHz) CONFIG1H~1~13=0xf,0x2,HS oscillator (high power > 16 MHz) CONFIG1H~1~14=0xf,0x1,XT oscillator CONFIG1H~1~15=0xf,0x0,LP oscillator CONFIG1H~2~1=0x10,0x0,Disabled CONFIG1H~2~2=0x10,0x10,Enabled CONFIG1H~3~1=0x20,0x0,Disabled CONFIG1H~3~2=0x20,0x20,Enabled CONFIG1H~4~1=0x40,0x0,Disabled CONFIG1H~4~2=0x40,0x40,Enabled CONFIG1H~5~1=0x80,0x0,Disabled CONFIG1H~5~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PWRTEN,0x1,Power-up Timer Enable bit CONFIG2L~2=BOREN,0x6,Brown-out Reset Enable bits CONFIG2L~3=BORV,0x18,Brown Out Reset Voltage bits CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Brown-out Reset enabled in hardware only (SBOREN is disabled) CONFIG2L~2~2=0x6,0x4,Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) CONFIG2L~2~3=0x6,0x2,Enabled CONFIG2L~2~4=0x6,0x0,Disabled CONFIG2L~3~1=0x18,0x18,VBOR set to 1.90 V nominal CONFIG2L~3~2=0x18,0x10,VBOR set to 2.20 V nominal CONFIG2L~3~3=0x18,0x8,VBOR set to 2.50 V nominal CONFIG2L~3~4=0x18,0x0,VBOR set to 2.85 V nominal CONFIG2H_unused=0x0 CONFIG2H~1=WDTEN,0x3,Watchdog Timer Enable bits CONFIG2H~2=WDTPS,0x3c,Watchdog Timer Postscale Select bits CONFIG2H~1~1=0x3,0x3,Enabled CONFIG2H~1~2=0x3,0x2,WDT is controlled by SWDTEN bit of the WDTCON register CONFIG2H~1~3=0x3,0x1,WDT is disabled in sleep, otherwise enabled. SWDTEN bit has no effect CONFIG2H~1~4=0x3,0x0,Disabled CONFIG2H~2~1=0x3c,0x3c,1:32768 CONFIG2H~2~2=0x3c,0x38,1:16384 CONFIG2H~2~3=0x3c,0x34,1:8192 CONFIG2H~2~4=0x3c,0x30,1:4096 CONFIG2H~2~5=0x3c,0x2c,1:2048 CONFIG2H~2~6=0x3c,0x28,1:1024 CONFIG2H~2~7=0x3c,0x24,1:512 CONFIG2H~2~8=0x3c,0x20,1:256 CONFIG2H~2~9=0x3c,0x1c,1:128 CONFIG2H~2~10=0x3c,0x18,1:64 CONFIG2H~2~11=0x3c,0x14,1:32 CONFIG2H~2~12=0x3c,0x10,1:16 CONFIG2H~2~13=0x3c,0xc,1:8 CONFIG2H~2~14=0x3c,0x8,1:4 CONFIG2H~2~15=0x3c,0x4,1:2 CONFIG2H~2~16=0x3c,0x0,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 MUX bit CONFIG3H~2=PBADEN,0x2,PORTB A/D Enable bit CONFIG3H~3=CCP3MX,0x4,P3A/CCP3 Mux bit CONFIG3H~4=HFOFST,0x8,HFINTOSC Fast Start-up CONFIG3H~5=T3CMX,0x10,Timer3 Clock input mux bit CONFIG3H~6=P2BMX,0x20,ECCP2 B output mux bit CONFIG3H~7=MCLRE,0x80,MCLR Pin Enable bit CONFIG3H~1~1=0x1,0x1,CCP2 input/output is multiplexed with RC1 CONFIG3H~1~2=0x1,0x0,CCP2 input/output is multiplexed with RB3 CONFIG3H~2~1=0x2,0x2,Enabled CONFIG3H~2~2=0x2,0x0,Disabled CONFIG3H~3~1=0x4,0x4,P3A/CCP3 input/output is multiplexed with RB5 CONFIG3H~3~2=0x4,0x0,P3A/CCP3 input/output is mulitplexed with RE0 CONFIG3H~4~1=0x8,0x8,Enabled CONFIG3H~4~2=0x8,0x0,Disabled CONFIG3H~5~1=0x10,0x10,T3CKI is on RC0 CONFIG3H~5~2=0x10,0x0,T3CKI is on RB5 CONFIG3H~6~1=0x20,0x20,P2B is on RD2 CONFIG3H~6~2=0x20,0x0,P2B is on RC0 CONFIG3H~7~1=0x80,0x80,MCLR pin enabled, RE3 input pin disabled CONFIG3H~7~2=0x80,0x0,RE3 input pin enabled; MCLR disabled CONFIG4L_unused=0x0 CONFIG4L~1=STVREN,0x1,Stack Full/Underflow Reset Enable bit CONFIG4L~2=LVP,0x4,Single-Supply ICSP Enable bit CONFIG4L~3=XINST,0x40,Extended Instruction Set Enable bit CONFIG4L~4=DEBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x40,0x40,Enabled CONFIG4L~3~2=0x40,0x0,Disabled CONFIG4L~4~1=0x80,0x80,Disabled CONFIG4L~4~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP0,0x1,Code Protection Block 0 CONFIG5L~2=CP1,0x2,Code Protection Block 1 CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x0,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x0,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPB,0x40,Boot Block Code Protection bit CONFIG5H~2=CPD,0x80,Data EEPROM Code Protection bit CONFIG5H~1~1=0x40,0x40,Disabled CONFIG5H~1~2=0x40,0x0,Enabled CONFIG5H~2~1=0x80,0x80,Disabled CONFIG5H~2~2=0x80,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT0,0x1,Write Protection Block 0 CONFIG6L~2=WRT1,0x2,Write Protection Block 1 CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x0,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x0,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTC,0x20,Configuration Register Write Protection bit CONFIG6H~2=WRTB,0x40,Boot Block Write Protection bit CONFIG6H~3=WRTD,0x80,Data EEPROM Write Protection bit CONFIG6H~1~1=0x20,0x20,Disabled CONFIG6H~1~2=0x20,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x80,0x80,Disabled CONFIG6H~3~2=0x80,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR0,0x1,Table Read Protection Block 0 CONFIG7L~2=EBTR1,0x2,Table Read Protection Block 1 CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x0,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x0,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Boot Block Table Read Protection bit CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F45K22] pgmmem=0x0 ~pgmmem=0x7fff cfgmem=0x300000 ~cfgmem=0x30000d userid=0x200000 ~userid=0x200007 eedata=0x0 ~eedata=0xff devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0x5500 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000a=CONFIG6L 0x30000b=CONFIG6H 0x30000c=CONFIG7L 0x30000d=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=FOSC,0xf,Oscillator Selection bits CONFIG1H~2=PLLCFG,0x10,4X PLL Enable CONFIG1H~3=PRICLKEN,0x20,Primary clock enable bit CONFIG1H~4=FCMEN,0x40,Fail-Safe Clock Monitor Enable bit CONFIG1H~5=IESO,0x80,Internal/External Oscillator Switchover bit CONFIG1H~1~1=0xe,0xe,111X External RC oscillator, CLKOUT function on OSC2 CONFIG1H~1~2=0xf,0xd,EC oscillator (low power, < 4 MHz) CONFIG1H~1~3=0xf,0xc,EC oscillator, CLKOUT on OSC2 (low power, < 4 MHz) CONFIG1H~1~4=0xf,0xb,EC oscillator (medium power, 4-16 MHz) CONFIG1H~1~5=0xf,0xa,EC oscillator, CLKOUT on OSC2 (medium power, 4-16 MHz) CONFIG1H~1~6=0xf,0x9,Internal oscillator block, CLKOUT function on RA6, port function on RA7 CONFIG1H~1~7=0xf,0x8,Internal oscillator block, port function on RA6 and RA7 CONFIG1H~1~8=0xf,0x7,External RC oscillator, port function on RA6 CONFIG1H~1~9=0xf,0x6,External RC, CLKOUT on OSC2 CONFIG1H~1~10=0xf,0x5,EC oscillator, port function on RA6 (high power, >16 MHz) CONFIG1H~1~11=0xf,0x4,EC oscillator, CLKOUT function on OSC2 (high power, >16 MHz) CONFIG1H~1~12=0xf,0x3,HS oscillator (medium power 4-16 MHz) CONFIG1H~1~13=0xf,0x2,HS oscillator (high power > 16 MHz) CONFIG1H~1~14=0xf,0x1,XT oscillator CONFIG1H~1~15=0xf,0x0,LP oscillator CONFIG1H~2~1=0x10,0x0,Disabled CONFIG1H~2~2=0x10,0x10,Enabled CONFIG1H~3~1=0x20,0x0,Disabled CONFIG1H~3~2=0x20,0x20,Enabled CONFIG1H~4~1=0x40,0x0,Disabled CONFIG1H~4~2=0x40,0x40,Enabled CONFIG1H~5~1=0x80,0x0,Disabled CONFIG1H~5~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PWRTEN,0x1,Power-up Timer Enable bit CONFIG2L~2=BOREN,0x6,Brown-out Reset Enable bits CONFIG2L~3=BORV,0x18,Brown Out Reset Voltage bits CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Brown-out Reset enabled in hardware only (SBOREN is disabled) CONFIG2L~2~2=0x6,0x4,Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) CONFIG2L~2~3=0x6,0x2,Enabled CONFIG2L~2~4=0x6,0x0,Disabled CONFIG2L~3~1=0x18,0x18,VBOR set to 1.90 V nominal CONFIG2L~3~2=0x18,0x10,VBOR set to 2.20 V nominal CONFIG2L~3~3=0x18,0x8,VBOR set to 2.50 V nominal CONFIG2L~3~4=0x18,0x0,VBOR set to 2.85 V nominal CONFIG2H_unused=0x0 CONFIG2H~1=WDTEN,0x3,Watchdog Timer Enable bits CONFIG2H~2=WDTPS,0x3c,Watchdog Timer Postscale Select bits CONFIG2H~1~1=0x3,0x3,Enabled CONFIG2H~1~2=0x3,0x2,WDT is controlled by SWDTEN bit of the WDTCON register CONFIG2H~1~3=0x3,0x1,WDT is disabled in sleep, otherwise enabled. SWDTEN bit has no effect CONFIG2H~1~4=0x3,0x0,Disabled CONFIG2H~2~1=0x3c,0x3c,1:32768 CONFIG2H~2~2=0x3c,0x38,1:16384 CONFIG2H~2~3=0x3c,0x34,1:8192 CONFIG2H~2~4=0x3c,0x30,1:4096 CONFIG2H~2~5=0x3c,0x2c,1:2048 CONFIG2H~2~6=0x3c,0x28,1:1024 CONFIG2H~2~7=0x3c,0x24,1:512 CONFIG2H~2~8=0x3c,0x20,1:256 CONFIG2H~2~9=0x3c,0x1c,1:128 CONFIG2H~2~10=0x3c,0x18,1:64 CONFIG2H~2~11=0x3c,0x14,1:32 CONFIG2H~2~12=0x3c,0x10,1:16 CONFIG2H~2~13=0x3c,0xc,1:8 CONFIG2H~2~14=0x3c,0x8,1:4 CONFIG2H~2~15=0x3c,0x4,1:2 CONFIG2H~2~16=0x3c,0x0,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 MUX bit CONFIG3H~2=PBADEN,0x2,PORTB A/D Enable bit CONFIG3H~3=CCP3MX,0x4,P3A/CCP3 Mux bit CONFIG3H~4=HFOFST,0x8,HFINTOSC Fast Start-up CONFIG3H~5=T3CMX,0x10,Timer3 Clock input mux bit CONFIG3H~6=P2BMX,0x20,ECCP2 B output mux bit CONFIG3H~7=MCLRE,0x80,MCLR Pin Enable bit CONFIG3H~1~1=0x1,0x1,CCP2 input/output is multiplexed with RC1 CONFIG3H~1~2=0x1,0x0,CCP2 input/output is multiplexed with RB3 CONFIG3H~2~1=0x2,0x2,Enabled CONFIG3H~2~2=0x2,0x0,Disabled CONFIG3H~3~1=0x4,0x4,P3A/CCP3 input/output is multiplexed with RB5 CONFIG3H~3~2=0x4,0x0,P3A/CCP3 input/output is mulitplexed with RE0 CONFIG3H~4~1=0x8,0x8,Enabled CONFIG3H~4~2=0x8,0x0,Disabled CONFIG3H~5~1=0x10,0x10,T3CKI is on RC0 CONFIG3H~5~2=0x10,0x0,T3CKI is on RB5 CONFIG3H~6~1=0x20,0x20,P2B is on RD2 CONFIG3H~6~2=0x20,0x0,P2B is on RC0 CONFIG3H~7~1=0x80,0x80,MCLR pin enabled, RE3 input pin disabled CONFIG3H~7~2=0x80,0x0,RE3 input pin enabled; MCLR disabled CONFIG4L_unused=0x0 CONFIG4L~1=STVREN,0x1,Stack Full/Underflow Reset Enable bit CONFIG4L~2=LVP,0x4,Single-Supply ICSP Enable bit CONFIG4L~3=XINST,0x40,Extended Instruction Set Enable bit CONFIG4L~4=DEBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x40,0x40,Enabled CONFIG4L~3~2=0x40,0x0,Disabled CONFIG4L~4~1=0x80,0x80,Disabled CONFIG4L~4~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP0,0x1,Code Protection Block 0 CONFIG5L~2=CP1,0x2,Code Protection Block 1 CONFIG5L~3=CP2,0x4,Code Protection Block 2 CONFIG5L~4=CP3,0x8,Code Protection Block 3 CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x0,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x0,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x0,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x0,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPB,0x40,Boot Block Code Protection bit CONFIG5H~2=CPD,0x80,Data EEPROM Code Protection bit CONFIG5H~1~1=0x40,0x40,Disabled CONFIG5H~1~2=0x40,0x0,Enabled CONFIG5H~2~1=0x80,0x80,Disabled CONFIG5H~2~2=0x80,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT0,0x1,Write Protection Block 0 CONFIG6L~2=WRT1,0x2,Write Protection Block 1 CONFIG6L~3=WRT2,0x4,Write Protection Block 2 CONFIG6L~4=WRT3,0x8,Write Protection Block 3 CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x0,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x0,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x0,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x0,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTC,0x20,Configuration Register Write Protection bit CONFIG6H~2=WRTB,0x40,Boot Block Write Protection bit CONFIG6H~3=WRTD,0x80,Data EEPROM Write Protection bit CONFIG6H~1~1=0x20,0x20,Disabled CONFIG6H~1~2=0x20,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x80,0x80,Disabled CONFIG6H~3~2=0x80,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR0,0x1,Table Read Protection Block 0 CONFIG7L~2=EBTR1,0x2,Table Read Protection Block 1 CONFIG7L~3=EBTR2,0x4,Table Read Protection Block 2 CONFIG7L~4=EBTR3,0x8,Table Read Protection Block 3 CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x0,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x0,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x0,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x0,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Boot Block Table Read Protection bit CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE_24xx05 prog=18F_PROG_24xx05 config=18F_CONFIG data=18F_DATA_24xx05 [PIC18F46K22] pgmmem=0x0 ~pgmmem=0xffff cfgmem=0x300000 ~cfgmem=0x30000d userid=0x200000 ~userid=0x200007 eedata=0x0 ~eedata=0x3ff devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0x5400 configslots=14 0x300000= 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000a=CONFIG6L 0x30000b=CONFIG6H 0x30000c=CONFIG7L 0x30000d=CONFIG7H CONFIG1H_unused=0x0 CONFIG1H~1=FOSC,0xf,Oscillator Selection bits CONFIG1H~2=PLLCFG,0x10,4X PLL Enable CONFIG1H~3=PRICLKEN,0x20,Primary clock enable bit CONFIG1H~4=FCMEN,0x40,Fail-Safe Clock Monitor Enable bit CONFIG1H~5=IESO,0x80,Internal/External Oscillator Switchover bit CONFIG1H~1~1=0xe,0xe,111X External RC oscillator, CLKOUT function on OSC2 CONFIG1H~1~2=0xf,0xd,EC oscillator (low power, < 4 MHz) CONFIG1H~1~3=0xf,0xc,EC oscillator, CLKOUT on OSC2 (low power, < 4 MHz) CONFIG1H~1~4=0xf,0xb,EC oscillator (medium power, 4-16 MHz) CONFIG1H~1~5=0xf,0xa,EC oscillator, CLKOUT on OSC2 (medium power, 4-16 MHz) CONFIG1H~1~6=0xf,0x9,Internal oscillator block, CLKOUT function on RA6, port function on RA7 CONFIG1H~1~7=0xf,0x8,Internal oscillator block, port function on RA6 and RA7 CONFIG1H~1~8=0xf,0x7,External RC oscillator, port function on RA6 CONFIG1H~1~9=0xf,0x6,External RC, CLKOUT on OSC2 CONFIG1H~1~10=0xf,0x5,EC oscillator, port function on RA6 (high power, >16 MHz) CONFIG1H~1~11=0xf,0x4,EC oscillator, CLKOUT function on OSC2 (high power, >16 MHz) CONFIG1H~1~12=0xf,0x3,HS oscillator (medium power 4-16 MHz) CONFIG1H~1~13=0xf,0x2,HS oscillator (high power > 16 MHz) CONFIG1H~1~14=0xf,0x1,XT oscillator CONFIG1H~1~15=0xf,0x0,LP oscillator CONFIG1H~2~1=0x10,0x0,Disabled CONFIG1H~2~2=0x10,0x10,Enabled CONFIG1H~3~1=0x20,0x0,Disabled CONFIG1H~3~2=0x20,0x20,Enabled CONFIG1H~4~1=0x40,0x0,Disabled CONFIG1H~4~2=0x40,0x40,Enabled CONFIG1H~5~1=0x80,0x0,Disabled CONFIG1H~5~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PWRTEN,0x1,Power-up Timer Enable bit CONFIG2L~2=BOREN,0x6,Brown-out Reset Enable bits CONFIG2L~3=BORV,0x18,Brown Out Reset Voltage bits CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Brown-out Reset enabled in hardware only (SBOREN is disabled) CONFIG2L~2~2=0x6,0x4,Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) CONFIG2L~2~3=0x6,0x2,Enabled CONFIG2L~2~4=0x6,0x0,Disabled CONFIG2L~3~1=0x18,0x18,VBOR set to 1.90 V nominal CONFIG2L~3~2=0x18,0x10,VBOR set to 2.20 V nominal CONFIG2L~3~3=0x18,0x8,VBOR set to 2.50 V nominal CONFIG2L~3~4=0x18,0x0,VBOR set to 2.85 V nominal CONFIG2H_unused=0x0 CONFIG2H~1=WDTEN,0x3,Watchdog Timer Enable bits CONFIG2H~2=WDTPS,0x3c,Watchdog Timer Postscale Select bits CONFIG2H~1~1=0x3,0x3,Enabled CONFIG2H~1~2=0x3,0x2,WDT is controlled by SWDTEN bit of the WDTCON register CONFIG2H~1~3=0x3,0x1,WDT is disabled in sleep, otherwise enabled. SWDTEN bit has no effect CONFIG2H~1~4=0x3,0x0,Disabled CONFIG2H~2~1=0x3c,0x3c,1:32768 CONFIG2H~2~2=0x3c,0x38,1:16384 CONFIG2H~2~3=0x3c,0x34,1:8192 CONFIG2H~2~4=0x3c,0x30,1:4096 CONFIG2H~2~5=0x3c,0x2c,1:2048 CONFIG2H~2~6=0x3c,0x28,1:1024 CONFIG2H~2~7=0x3c,0x24,1:512 CONFIG2H~2~8=0x3c,0x20,1:256 CONFIG2H~2~9=0x3c,0x1c,1:128 CONFIG2H~2~10=0x3c,0x18,1:64 CONFIG2H~2~11=0x3c,0x14,1:32 CONFIG2H~2~12=0x3c,0x10,1:16 CONFIG2H~2~13=0x3c,0xc,1:8 CONFIG2H~2~14=0x3c,0x8,1:4 CONFIG2H~2~15=0x3c,0x4,1:2 CONFIG2H~2~16=0x3c,0x0,1:1 CONFIG3H_unused=0x0 CONFIG3H~1=CCP2MUX,0x1,CCP2 MUX bit CONFIG3H~2=PBADEN,0x2,PORTB A/D Enable bit CONFIG3H~3=CCP3MX,0x4,P3A/CCP3 Mux bit CONFIG3H~4=HFOFST,0x8,HFINTOSC Fast Start-up CONFIG3H~5=T3CMX,0x10,Timer3 Clock input mux bit CONFIG3H~6=P2BMX,0x20,ECCP2 B output mux bit CONFIG3H~7=MCLRE,0x80,MCLR Pin Enable bit CONFIG3H~1~1=0x1,0x1,CCP2 input/output is multiplexed with RC1 CONFIG3H~1~2=0x1,0x0,CCP2 input/output is multiplexed with RB3 CONFIG3H~2~1=0x2,0x2,Enabled CONFIG3H~2~2=0x2,0x0,Disabled CONFIG3H~3~1=0x4,0x4,P3A/CCP3 input/output is multiplexed with RB5 CONFIG3H~3~2=0x4,0x0,P3A/CCP3 input/output is mulitplexed with RE0 CONFIG3H~4~1=0x8,0x8,Enabled CONFIG3H~4~2=0x8,0x0,Disabled CONFIG3H~5~1=0x10,0x10,T3CKI is on RC0 CONFIG3H~5~2=0x10,0x0,T3CKI is on RB5 CONFIG3H~6~1=0x20,0x20,P2B is on RD2 CONFIG3H~6~2=0x20,0x0,P2B is on RC0 CONFIG3H~7~1=0x80,0x80,MCLR pin enabled, RE3 input pin disabled CONFIG3H~7~2=0x80,0x0,RE3 input pin enabled; MCLR disabled CONFIG4L_unused=0x0 CONFIG4L~1=STVREN,0x1,Stack Full/Underflow Reset Enable bit CONFIG4L~2=LVP,0x4,Single-Supply ICSP Enable bit CONFIG4L~3=XINST,0x40,Extended Instruction Set Enable bit CONFIG4L~4=DEBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x4,0x4,Enabled CONFIG4L~2~2=0x4,0x0,Disabled CONFIG4L~3~1=0x40,0x40,Enabled CONFIG4L~3~2=0x40,0x0,Disabled CONFIG4L~4~1=0x80,0x80,Disabled CONFIG4L~4~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP0,0x1,Code Protection Block 0 CONFIG5L~2=CP1,0x2,Code Protection Block 1 CONFIG5L~3=CP2,0x4,Code Protection Block 2 CONFIG5L~4=CP3,0x8,Code Protection Block 3 CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x0,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x0,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x0,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x0,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPB,0x40,Boot Block Code Protection bit CONFIG5H~2=CPD,0x80,Data EEPROM Code Protection bit CONFIG5H~1~1=0x40,0x40,Disabled CONFIG5H~1~2=0x40,0x0,Enabled CONFIG5H~2~1=0x80,0x80,Disabled CONFIG5H~2~2=0x80,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT0,0x1,Write Protection Block 0 CONFIG6L~2=WRT1,0x2,Write Protection Block 1 CONFIG6L~3=WRT2,0x4,Write Protection Block 2 CONFIG6L~4=WRT3,0x8,Write Protection Block 3 CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x0,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x0,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x0,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x0,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTC,0x20,Configuration Register Write Protection bit CONFIG6H~2=WRTB,0x40,Boot Block Write Protection bit CONFIG6H~3=WRTD,0x80,Data EEPROM Write Protection bit CONFIG6H~1~1=0x20,0x20,Disabled CONFIG6H~1~2=0x20,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x80,0x80,Disabled CONFIG6H~3~2=0x80,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBTR0,0x1,Table Read Protection Block 0 CONFIG7L~2=EBTR1,0x2,Table Read Protection Block 1 CONFIG7L~3=EBTR2,0x4,Table Read Protection Block 2 CONFIG7L~4=EBTR3,0x8,Table Read Protection Block 3 CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x0,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x0,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x0,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x0,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBTRB,0x40,Boot Block Table Read Protection bit CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F25K80] pgmmem=0x0 ~pgmmem=0x7fff cfgmem=0x300000 ~cfgmem=0x30000d userid=0x200000 ~userid=0x200007 eedata=0x0 ~eedata=0x3ff devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0x6180 configslots=14 0x300000=CONFIG1L 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000a=CONFIG6L 0x30000b=CONFIG6H 0x30000c=CONFIG7L 0x30000d=CONFIG7H CONFIG1L_unused=0x0 CONFIG1L~1=RETEN,0x1,VREG Sleep Enable bit CONFIG1L~2=INTOSCSEL,0x4,LF-INTOSC Low-power Enable bit CONFIG1L~3=SOSCSEL,0x18,SOSC Power Selection and mode Configuration bits CONFIG1L~4=XINST,0x40,Extended Instruction Set CONFIG1L~1~1=0x1,0x0,Enabled CONFIG1L~1~2=0x1,0x1,Disabled CONFIG1L~2~1=0x4,0x4,High Security Code Protection Enable CONFIG1L~2~2=0x4,0x0,LF-INTOSC in Low-power mode during Sleep CONFIG1L~3~1=0x18,0x18,High Power SOSC circuit selected CONFIG1L~3~2=0x18,0x8,Low Power SOSC circuit selected CONFIG1L~3~3=0x18,0x10,Digital (SCLKI) mode CONFIG1L~4~1=0x40,0x40,Enabled CONFIG1L~4~2=0x40,0x0,Disabled CONFIG1H_unused=0x0 CONFIG1H~1=FOSC,0xf,Oscillator CONFIG1H~2=PLLCFG,0x10,PLL x4 Enable bit CONFIG1H~3=FCMEN,0x40,Fail-Safe Clock Monitor CONFIG1H~4=IESO,0x80,Internal External Oscillator Switch Over Mode CONFIG1H~1~1=0x7,0x7,External RC oscillator CONFIG1H~1~2=0x7,0x6,External RC oscillator, CLKOUT function on OSC2 CONFIG1H~1~3=0xf,0xd,EC oscillator (Low power, DC - 160 kHz) CONFIG1H~1~4=0xf,0xc,EC oscillator, CLKOUT function on OSC2 (Low power, DC - 160 kHz) CONFIG1H~1~5=0xf,0xb,EC oscillator (Medium power, 160 kHz - 4 MHz) CONFIG1H~1~6=0xf,0xa,EC oscillator, CLKOUT function on OSC2 (Medium power, 160 kHz - 4 MHz) CONFIG1H~1~7=0xf,0x9,Internal RC oscillator, CLKOUT function on OSC2 CONFIG1H~1~8=0xf,0x8,Internal RC oscillator CONFIG1H~1~9=0xf,0x5,EC oscillator (High power, 16 MHz - 64 MHz) CONFIG1H~1~10=0xf,0x4,EC oscillator, CLKOUT function on OSC2 (High power, 16 MHz - 64 MHz) CONFIG1H~1~11=0xf,0x3,HS oscillator (Medium power, 4 MHz - 16 MHz) CONFIG1H~1~12=0xf,0x2,HS oscillator (High power, 16 MHz - 25 MHz) CONFIG1H~1~13=0xf,0x1,XT oscillator CONFIG1H~1~14=0xf,0x0,LP oscillator CONFIG1H~2~1=0x10,0x10,Enabled CONFIG1H~2~2=0x10,0x0,Disabled CONFIG1H~3~1=0x40,0x0,Disabled CONFIG1H~3~2=0x40,0x40,Enabled CONFIG1H~4~1=0x80,0x0,Disabled CONFIG1H~4~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PWRTEN,0x1,Power Up Timer CONFIG2L~2=BOREN,0x6,Brown Out Detect CONFIG2L~3=BORV,0x18,Brown-out Reset Voltage bits CONFIG2L~4=BORPWR,0x60,BORMV Power level CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active, disabled in SLEEP, SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,1.8V CONFIG2L~3~2=0x18,0x10,2.0V CONFIG2L~3~3=0x18,0x8,2.7V CONFIG2L~3~4=0x18,0x0,3.0V CONFIG2L~4~1=0x60,0x60,ZPBORMV instead of BORMV is selected CONFIG2L~4~2=0x60,0x40,BORMV set to high power level CONFIG2L~4~3=0x60,0x20,BORMV set to medium power level CONFIG2L~4~4=0x60,0x0,BORMV set to low power level CONFIG2H_unused=0x0 CONFIG2H~1=WDTEN,0x3,Watchdog Timer CONFIG2H~2=WDTPS,0x78,Watchdog Postscaler CONFIG2H~3=WDTPS,0x04,Watchdog Postscaler/2 CONFIG2H~1~1=0x3,0x3,WDT enabled in hardware; SWDTEN bit disabled CONFIG2H~1~2=0x3,0x2,WDT controlled by SWDTEN bit setting CONFIG2H~1~3=0x3,0x1,WDT enabled only while device is active and disabled in Sleep mode; SWDTEN bit disabled CONFIG2H~1~4=0x3,0x0,WDT disabled in hardware; SWDTEN bit disabled CONFIG2H~2~1=0x78,0x70,1:1048576 CONFIG2H~2~2=0x78,0x48,1:262144 CONFIG2H~2~3=0x78,0x40,1:65536 CONFIG2H~2~4=0x78,0x38,1:16384 CONFIG2H~2~5=0x78,0x30,1:4096 CONFIG2H~2~6=0x78,0x28,1:1024 CONFIG2H~2~7=0x78,0x20,1:256 CONFIG2H~2~8=0x78,0x18,1:64 CONFIG2H~2~9=0x78,0x10,1:16 CONFIG2H~2~10=0x78,0x8,1:4 CONFIG2H~2~11=0x78,0x0,1:1 CONFIG2H~3~1=0x04,0x04,No Divide CONFIG2H~3~2=0x04,0x0,Divide By 2 CONFIG3H_unused=0x0 CONFIG3H~1=CANMX,0x1,ECAN Mux bit CONFIG3H~2=MSSPMSK,0x8,MSSP address masking CONFIG3H~3=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,ECAN TX and RX pins are located on RB2 and RB3, respectively CONFIG3H~1~2=0x1,0x0,ECAN TX and RX pins are located on RC6 and RC7, respectively CONFIG3H~2~1=0x8,0x8,7 Bit address masking mode CONFIG3H~2~2=0x8,0x0,5 bit address masking mode CONFIG3H~3~1=0x80,0x80,MCLR Enabled, RG5 Disabled CONFIG3H~3~2=0x80,0x0,MCLR Disabled, RG5 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVREN,0x1,Stack Overflow Reset CONFIG4L~2=BBSIZ,0x10,Boot Block Size CONFIG4L~3=DEBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x10,0x10,2K word Boot Block size CONFIG4L~2~2=0x10,0x0,1K word Boot Block size CONFIG4L~3~1=0x80,0x80,Disabled CONFIG4L~3~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP0,0x1,Code Protect 00800-03FFF CONFIG5L~2=CP1,0x2,Code Protect 04000-07FFF CONFIG5L~3=CP2,0x4,Code Protect 08000-0BFFF CONFIG5L~4=CP3,0x8,Code Protect 0C000-0FFFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x0,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x0,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x0,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x0,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPB,0x40,Code Protect Boot CONFIG5H~2=CPD,0x80,Data EE Read Protect CONFIG5H~1~1=0x40,0x40,Disabled CONFIG5H~1~2=0x40,0x0,Enabled CONFIG5H~2~1=0x80,0x80,Disabled CONFIG5H~2~2=0x80,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT0,0x1,Table Write Protect 00800-03FFF CONFIG6L~2=WRT1,0x2,Table Write Protect 04000-07FFF CONFIG6L~3=WRT2,0x4,Table Write Protect 08000-0BFFF CONFIG6L~4=WRT3,0x8,Table Write Protect 0C000-0FFFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x0,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x0,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x0,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x0,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTC,0x20,Config. Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTD,0x80,Data EE Write Protect CONFIG6H~1~1=0x20,0x20,Disabled CONFIG6H~1~2=0x20,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x80,0x80,Disabled CONFIG6H~3~2=0x80,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBRT0,0x1,Table Read Protect 00800-03FFF CONFIG7L~2=EBRT1,0x2,Table Read Protect 04000-07FFF CONFIG7L~3=EBRT2,0x4,Table Read Protect 08000-0BFFF CONFIG7L~4=EBRT3,0x8,Table Read Protect 0C000-0FFFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x0,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x0,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x0,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x0,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBRTB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F26K80] pgmmem=0x0 ~pgmmem=0xffff cfgmem=0x300000 ~cfgmem=0x30000d userid=0x200000 ~userid=0x200007 eedata=0x0 ~eedata=0x3ff devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0x6120 configslots=14 0x300000=CONFIG1L 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000a=CONFIG6L 0x30000b=CONFIG6H 0x30000c=CONFIG7L 0x30000d=CONFIG7H CONFIG1L_unused=0x0 CONFIG1L~1=RETEN,0x1,VREG Sleep Enable bit CONFIG1L~2=INTOSCSEL,0x4,LF-INTOSC Low-power Enable bit CONFIG1L~3=SOSCSEL,0x18,SOSC Power Selection and mode Configuration bits CONFIG1L~4=XINST,0x40,Extended Instruction Set CONFIG1L~1~1=0x1,0x0,Enabled CONFIG1L~1~2=0x1,0x1,Disabled CONFIG1L~2~1=0x4,0x4,High Security Code Protection Enable CONFIG1L~2~2=0x4,0x0,LF-INTOSC in Low-power mode during Sleep CONFIG1L~3~1=0x18,0x18,High Power SOSC circuit selected CONFIG1L~3~2=0x18,0x8,Low Power SOSC circuit selected CONFIG1L~3~3=0x18,0x10,Digital (SCLKI) mode CONFIG1L~4~1=0x40,0x40,Enabled CONFIG1L~4~2=0x40,0x0,Disabled CONFIG1H_unused=0x0 CONFIG1H~1=FOSC,0xf,Oscillator CONFIG1H~2=PLLCFG,0x10,PLL x4 Enable bit CONFIG1H~3=FCMEN,0x40,Fail-Safe Clock Monitor CONFIG1H~4=IESO,0x80,Internal External Oscillator Switch Over Mode CONFIG1H~1~1=0x7,0x7,External RC oscillator CONFIG1H~1~2=0x7,0x6,External RC oscillator, CLKOUT function on OSC2 CONFIG1H~1~3=0xf,0xd,EC oscillator (Low power, DC - 160 kHz) CONFIG1H~1~4=0xf,0xc,EC oscillator, CLKOUT function on OSC2 (Low power, DC - 160 kHz) CONFIG1H~1~5=0xf,0xb,EC oscillator (Medium power, 160 kHz - 4 MHz) CONFIG1H~1~6=0xf,0xa,EC oscillator, CLKOUT function on OSC2 (Medium power, 160 kHz - 4 MHz) CONFIG1H~1~7=0xf,0x9,Internal RC oscillator, CLKOUT function on OSC2 CONFIG1H~1~8=0xf,0x8,Internal RC oscillator CONFIG1H~1~9=0xf,0x5,EC oscillator (High power, 16 MHz - 64 MHz) CONFIG1H~1~10=0xf,0x4,EC oscillator, CLKOUT function on OSC2 (High power, 16 MHz - 64 MHz) CONFIG1H~1~11=0xf,0x3,HS oscillator (Medium power, 4 MHz - 16 MHz) CONFIG1H~1~12=0xf,0x2,HS oscillator (High power, 16 MHz - 25 MHz) CONFIG1H~1~13=0xf,0x1,XT oscillator CONFIG1H~1~14=0xf,0x0,LP oscillator CONFIG1H~2~1=0x10,0x10,Enabled CONFIG1H~2~2=0x10,0x0,Disabled CONFIG1H~3~1=0x40,0x0,Disabled CONFIG1H~3~2=0x40,0x40,Enabled CONFIG1H~4~1=0x80,0x0,Disabled CONFIG1H~4~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PWRTEN,0x1,Power Up Timer CONFIG2L~2=BOREN,0x6,Brown Out Detect CONFIG2L~3=BORV,0x18,Brown-out Reset Voltage bits CONFIG2L~4=BORPWR,0x60,BORMV Power level CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active, disabled in SLEEP, SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,1.8V CONFIG2L~3~2=0x18,0x10,2.0V CONFIG2L~3~3=0x18,0x8,2.7V CONFIG2L~3~4=0x18,0x0,3.0V CONFIG2L~4~1=0x60,0x60,ZPBORMV instead of BORMV is selected CONFIG2L~4~2=0x60,0x40,BORMV set to high power level CONFIG2L~4~3=0x60,0x20,BORMV set to medium power level CONFIG2L~4~4=0x60,0x0,BORMV set to low power level CONFIG2H_unused=0x0 CONFIG2H~1=WDTEN,0x3,Watchdog Timer CONFIG2H~2=WDTPS,0x78,Watchdog Postscaler CONFIG2H~3=WDTPS,0x04,Watchdog Postscaler/2 CONFIG2H~1~1=0x3,0x3,WDT enabled in hardware; SWDTEN bit disabled CONFIG2H~1~2=0x3,0x2,WDT controlled by SWDTEN bit setting CONFIG2H~1~3=0x3,0x1,WDT enabled only while device is active and disabled in Sleep mode; SWDTEN bit disabled CONFIG2H~1~4=0x3,0x0,WDT disabled in hardware; SWDTEN bit disabled CONFIG2H~2~1=0x78,0x70,1:1048576 CONFIG2H~2~2=0x78,0x48,1:262144 CONFIG2H~2~3=0x78,0x40,1:65536 CONFIG2H~2~4=0x78,0x38,1:16384 CONFIG2H~2~5=0x78,0x30,1:4096 CONFIG2H~2~6=0x78,0x28,1:1024 CONFIG2H~2~7=0x78,0x20,1:256 CONFIG2H~2~8=0x78,0x18,1:64 CONFIG2H~2~9=0x78,0x10,1:16 CONFIG2H~2~10=0x78,0x8,1:4 CONFIG2H~2~11=0x78,0x0,1:1 CONFIG2H~3~1=0x04,0x04,No Divide CONFIG2H~3~2=0x04,0x0,Divide By 2 CONFIG3H_unused=0x0 CONFIG3H~1=CANMX,0x1,ECAN Mux bit CONFIG3H~2=MSSPMSK,0x8,MSSP address masking CONFIG3H~3=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,ECAN TX and RX pins are located on RB2 and RB3, respectively CONFIG3H~1~2=0x1,0x0,ECAN TX and RX pins are located on RC6 and RC7, respectively CONFIG3H~2~1=0x8,0x8,7 Bit address masking mode CONFIG3H~2~2=0x8,0x0,5 bit address masking mode CONFIG3H~3~1=0x80,0x80,MCLR Enabled, RG5 Disabled CONFIG3H~3~2=0x80,0x0,MCLR Disabled, RG5 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVREN,0x1,Stack Overflow Reset CONFIG4L~2=BBSIZ,0x10,Boot Block Size CONFIG4L~3=DEBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x10,0x10,2K word Boot Block size CONFIG4L~2~2=0x10,0x0,1K word Boot Block size CONFIG4L~3~1=0x80,0x80,Disabled CONFIG4L~3~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP0,0x1,Code Protect 00800-03FFF CONFIG5L~2=CP1,0x2,Code Protect 04000-07FFF CONFIG5L~3=CP2,0x4,Code Protect 08000-0BFFF CONFIG5L~4=CP3,0x8,Code Protect 0C000-0FFFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x0,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x0,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x0,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x0,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPB,0x40,Code Protect Boot CONFIG5H~2=CPD,0x80,Data EE Read Protect CONFIG5H~1~1=0x40,0x40,Disabled CONFIG5H~1~2=0x40,0x0,Enabled CONFIG5H~2~1=0x80,0x80,Disabled CONFIG5H~2~2=0x80,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT0,0x1,Table Write Protect 00800-03FFF CONFIG6L~2=WRT1,0x2,Table Write Protect 04000-07FFF CONFIG6L~3=WRT2,0x4,Table Write Protect 08000-0BFFF CONFIG6L~4=WRT3,0x8,Table Write Protect 0C000-0FFFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x0,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x0,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x0,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x0,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTC,0x20,Config. Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTD,0x80,Data EE Write Protect CONFIG6H~1~1=0x20,0x20,Disabled CONFIG6H~1~2=0x20,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x80,0x80,Disabled CONFIG6H~3~2=0x80,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBRT0,0x1,Table Read Protect 00800-03FFF CONFIG7L~2=EBRT1,0x2,Table Read Protect 04000-07FFF CONFIG7L~3=EBRT2,0x4,Table Read Protect 08000-0BFFF CONFIG7L~4=EBRT3,0x8,Table Read Protect 0C000-0FFFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x0,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x0,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x0,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x0,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBRTB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F45K80] pgmmem=0x0 ~pgmmem=0x7fff cfgmem=0x300000 ~cfgmem=0x30000d userid=0x200000 ~userid=0x200007 eedata=0x0 ~eedata=0x3ff devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0x6160 configslots=14 0x300000=CONFIG1L 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000a=CONFIG6L 0x30000b=CONFIG6H 0x30000c=CONFIG7L 0x30000d=CONFIG7H CONFIG1L_unused=0x0 CONFIG1L~1=RETEN,0x1,VREG Sleep Enable bit CONFIG1L~2=INTOSCSEL,0x4,LF-INTOSC Low-power Enable bit CONFIG1L~3=SOSCSEL,0x18,SOSC Power Selection and mode Configuration bits CONFIG1L~4=XINST,0x40,Extended Instruction Set CONFIG1L~1~1=0x1,0x0,Enabled CONFIG1L~1~2=0x1,0x1,Disabled CONFIG1L~2~1=0x4,0x4,High Security Code Protection Enable CONFIG1L~2~2=0x4,0x0,LF-INTOSC in Low-power mode during Sleep CONFIG1L~3~1=0x18,0x18,High Power SOSC circuit selected CONFIG1L~3~2=0x18,0x8,Low Power SOSC circuit selected CONFIG1L~3~3=0x18,0x10,Digital (SCLKI) mode CONFIG1L~4~1=0x40,0x40,Enabled CONFIG1L~4~2=0x40,0x0,Disabled CONFIG1H_unused=0x0 CONFIG1H~1=FOSC,0xf,Oscillator CONFIG1H~2=PLLCFG,0x10,PLL x4 Enable bit CONFIG1H~3=FCMEN,0x40,Fail-Safe Clock Monitor CONFIG1H~4=IESO,0x80,Internal External Oscillator Switch Over Mode CONFIG1H~1~1=0x7,0x7,External RC oscillator CONFIG1H~1~2=0x7,0x6,External RC oscillator, CLKOUT function on OSC2 CONFIG1H~1~3=0xf,0xd,EC oscillator (Low power, DC - 160 kHz) CONFIG1H~1~4=0xf,0xc,EC oscillator, CLKOUT function on OSC2 (Low power, DC - 160 kHz) CONFIG1H~1~5=0xf,0xb,EC oscillator (Medium power, 160 kHz - 4 MHz) CONFIG1H~1~6=0xf,0xa,EC oscillator, CLKOUT function on OSC2 (Medium power, 160 kHz - 4 MHz) CONFIG1H~1~7=0xf,0x9,Internal RC oscillator, CLKOUT function on OSC2 CONFIG1H~1~8=0xf,0x8,Internal RC oscillator CONFIG1H~1~9=0xf,0x5,EC oscillator (High power, 16 MHz - 64 MHz) CONFIG1H~1~10=0xf,0x4,EC oscillator, CLKOUT function on OSC2 (High power, 16 MHz - 64 MHz) CONFIG1H~1~11=0xf,0x3,HS oscillator (Medium power, 4 MHz - 16 MHz) CONFIG1H~1~12=0xf,0x2,HS oscillator (High power, 16 MHz - 25 MHz) CONFIG1H~1~13=0xf,0x1,XT oscillator CONFIG1H~1~14=0xf,0x0,LP oscillator CONFIG1H~2~1=0x10,0x10,Enabled CONFIG1H~2~2=0x10,0x0,Disabled CONFIG1H~3~1=0x40,0x0,Disabled CONFIG1H~3~2=0x40,0x40,Enabled CONFIG1H~4~1=0x80,0x0,Disabled CONFIG1H~4~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PWRTEN,0x1,Power Up Timer CONFIG2L~2=BOREN,0x6,Brown Out Detect CONFIG2L~3=BORV,0x18,Brown-out Reset Voltage bits CONFIG2L~4=BORPWR,0x60,BORMV Power level CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active, disabled in SLEEP, SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,1.8V CONFIG2L~3~2=0x18,0x10,2.0V CONFIG2L~3~3=0x18,0x8,2.7V CONFIG2L~3~4=0x18,0x0,3.0V CONFIG2L~4~1=0x60,0x60,ZPBORMV instead of BORMV is selected CONFIG2L~4~2=0x60,0x40,BORMV set to high power level CONFIG2L~4~3=0x60,0x20,BORMV set to medium power level CONFIG2L~4~4=0x60,0x0,BORMV set to low power level CONFIG2H_unused=0x0 CONFIG2H~1=WDTEN,0x3,Watchdog Timer CONFIG2H~2=WDTPS,0x78,Watchdog Postscaler CONFIG2H~3=WDTPS,0x04,Watchdog Postscaler/2 CONFIG2H~1~1=0x3,0x3,WDT enabled in hardware; SWDTEN bit disabled CONFIG2H~1~2=0x3,0x2,WDT controlled by SWDTEN bit setting CONFIG2H~1~3=0x3,0x1,WDT enabled only while device is active and disabled in Sleep mode; SWDTEN bit disabled CONFIG2H~1~4=0x3,0x0,WDT disabled in hardware; SWDTEN bit disabled CONFIG2H~2~1=0x78,0x70,1:1048576 CONFIG2H~2~2=0x78,0x48,1:262144 CONFIG2H~2~3=0x78,0x40,1:65536 CONFIG2H~2~4=0x78,0x38,1:16384 CONFIG2H~2~5=0x78,0x30,1:4096 CONFIG2H~2~6=0x78,0x28,1:1024 CONFIG2H~2~7=0x78,0x20,1:256 CONFIG2H~2~8=0x78,0x18,1:64 CONFIG2H~2~9=0x78,0x10,1:16 CONFIG2H~2~10=0x78,0x8,1:4 CONFIG2H~2~11=0x78,0x0,1:1 CONFIG2H~3~1=0x04,0x04,No Divide CONFIG2H~3~2=0x04,0x0,Divide By 2 CONFIG3H_unused=0x0 CONFIG3H~1=CANMX,0x1,ECAN Mux bit CONFIG3H~2=MSSPMSK,0x8,MSSP address masking CONFIG3H~3=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,ECAN TX and RX pins are located on RB2 and RB3, respectively CONFIG3H~1~2=0x1,0x0,ECAN TX and RX pins are located on RC6 and RC7, respectively CONFIG3H~2~1=0x8,0x8,7 Bit address masking mode CONFIG3H~2~2=0x8,0x0,5 bit address masking mode CONFIG3H~3~1=0x80,0x80,MCLR Enabled, RG5 Disabled CONFIG3H~3~2=0x80,0x0,MCLR Disabled, RG5 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVREN,0x1,Stack Overflow Reset CONFIG4L~2=BBSIZ,0x10,Boot Block Size CONFIG4L~3=DEBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x10,0x10,2K word Boot Block size CONFIG4L~2~2=0x10,0x0,1K word Boot Block size CONFIG4L~3~1=0x80,0x80,Disabled CONFIG4L~3~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP0,0x1,Code Protect 00800-03FFF CONFIG5L~2=CP1,0x2,Code Protect 04000-07FFF CONFIG5L~3=CP2,0x4,Code Protect 08000-0BFFF CONFIG5L~4=CP3,0x8,Code Protect 0C000-0FFFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x0,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x0,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x0,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x0,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPB,0x40,Code Protect Boot CONFIG5H~2=CPD,0x80,Data EE Read Protect CONFIG5H~1~1=0x40,0x40,Disabled CONFIG5H~1~2=0x40,0x0,Enabled CONFIG5H~2~1=0x80,0x80,Disabled CONFIG5H~2~2=0x80,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT0,0x1,Table Write Protect 00800-03FFF CONFIG6L~2=WRT1,0x2,Table Write Protect 04000-07FFF CONFIG6L~3=WRT2,0x4,Table Write Protect 08000-0BFFF CONFIG6L~4=WRT3,0x8,Table Write Protect 0C000-0FFFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x0,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x0,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x0,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x0,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTC,0x20,Config. Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTD,0x80,Data EE Write Protect CONFIG6H~1~1=0x20,0x20,Disabled CONFIG6H~1~2=0x20,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x80,0x80,Disabled CONFIG6H~3~2=0x80,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBRT0,0x1,Table Read Protect 00800-03FFF CONFIG7L~2=EBRT1,0x2,Table Read Protect 04000-07FFF CONFIG7L~3=EBRT2,0x4,Table Read Protect 08000-0BFFF CONFIG7L~4=EBRT3,0x8,Table Read Protect 0C000-0FFFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x0,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x0,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x0,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x0,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBRTB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F46K80] pgmmem=0x0 ~pgmmem=0xffff cfgmem=0x300000 ~cfgmem=0x30000d userid=0x200000 ~userid=0x200007 eedata=0x0 ~eedata=0x3ff devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0x6100 configslots=14 0x300000=CONFIG1L 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000a=CONFIG6L 0x30000b=CONFIG6H 0x30000c=CONFIG7L 0x30000d=CONFIG7H CONFIG1L_unused=0x0 CONFIG1L~1=RETEN,0x1,VREG Sleep Enable bit CONFIG1L~2=INTOSCSEL,0x4,LF-INTOSC Low-power Enable bit CONFIG1L~3=SOSCSEL,0x18,SOSC Power Selection and mode Configuration bits CONFIG1L~4=XINST,0x40,Extended Instruction Set CONFIG1L~1~1=0x1,0x0,Enabled CONFIG1L~1~2=0x1,0x1,Disabled CONFIG1L~2~1=0x4,0x4,High Security Code Protection Enable CONFIG1L~2~2=0x4,0x0,LF-INTOSC in Low-power mode during Sleep CONFIG1L~3~1=0x18,0x18,High Power SOSC circuit selected CONFIG1L~3~2=0x18,0x8,Low Power SOSC circuit selected CONFIG1L~3~3=0x18,0x10,Digital (SCLKI) mode CONFIG1L~4~1=0x40,0x40,Enabled CONFIG1L~4~2=0x40,0x0,Disabled CONFIG1H_unused=0x0 CONFIG1H~1=FOSC,0xf,Oscillator CONFIG1H~2=PLLCFG,0x10,PLL x4 Enable bit CONFIG1H~3=FCMEN,0x40,Fail-Safe Clock Monitor CONFIG1H~4=IESO,0x80,Internal External Oscillator Switch Over Mode CONFIG1H~1~1=0x7,0x7,External RC oscillator CONFIG1H~1~2=0x7,0x6,External RC oscillator, CLKOUT function on OSC2 CONFIG1H~1~3=0xf,0xd,EC oscillator (Low power, DC - 160 kHz) CONFIG1H~1~4=0xf,0xc,EC oscillator, CLKOUT function on OSC2 (Low power, DC - 160 kHz) CONFIG1H~1~5=0xf,0xb,EC oscillator (Medium power, 160 kHz - 4 MHz) CONFIG1H~1~6=0xf,0xa,EC oscillator, CLKOUT function on OSC2 (Medium power, 160 kHz - 4 MHz) CONFIG1H~1~7=0xf,0x9,Internal RC oscillator, CLKOUT function on OSC2 CONFIG1H~1~8=0xf,0x8,Internal RC oscillator CONFIG1H~1~9=0xf,0x5,EC oscillator (High power, 16 MHz - 64 MHz) CONFIG1H~1~10=0xf,0x4,EC oscillator, CLKOUT function on OSC2 (High power, 16 MHz - 64 MHz) CONFIG1H~1~11=0xf,0x3,HS oscillator (Medium power, 4 MHz - 16 MHz) CONFIG1H~1~12=0xf,0x2,HS oscillator (High power, 16 MHz - 25 MHz) CONFIG1H~1~13=0xf,0x1,XT oscillator CONFIG1H~1~14=0xf,0x0,LP oscillator CONFIG1H~2~1=0x10,0x10,Enabled CONFIG1H~2~2=0x10,0x0,Disabled CONFIG1H~3~1=0x40,0x0,Disabled CONFIG1H~3~2=0x40,0x40,Enabled CONFIG1H~4~1=0x80,0x0,Disabled CONFIG1H~4~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PWRTEN,0x1,Power Up Timer CONFIG2L~2=BOREN,0x6,Brown Out Detect CONFIG2L~3=BORV,0x18,Brown-out Reset Voltage bits CONFIG2L~4=BORPWR,0x60,BORMV Power level CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active, disabled in SLEEP, SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,1.8V CONFIG2L~3~2=0x18,0x10,2.0V CONFIG2L~3~3=0x18,0x8,2.7V CONFIG2L~3~4=0x18,0x0,3.0V CONFIG2L~4~1=0x60,0x60,ZPBORMV instead of BORMV is selected CONFIG2L~4~2=0x60,0x40,BORMV set to high power level CONFIG2L~4~3=0x60,0x20,BORMV set to medium power level CONFIG2L~4~4=0x60,0x0,BORMV set to low power level CONFIG2H_unused=0x0 CONFIG2H~1=WDTEN,0x3,Watchdog Timer CONFIG2H~2=WDTPS,0x78,Watchdog Postscaler CONFIG2H~3=WDTPS,0x04,Watchdog Postscaler/2 CONFIG2H~1~1=0x3,0x3,WDT enabled in hardware; SWDTEN bit disabled CONFIG2H~1~2=0x3,0x2,WDT controlled by SWDTEN bit setting CONFIG2H~1~3=0x3,0x1,WDT enabled only while device is active and disabled in Sleep mode; SWDTEN bit disabled CONFIG2H~1~4=0x3,0x0,WDT disabled in hardware; SWDTEN bit disabled CONFIG2H~2~1=0x78,0x70,1:1048576 CONFIG2H~2~2=0x78,0x48,1:262144 CONFIG2H~2~3=0x78,0x40,1:65536 CONFIG2H~2~4=0x78,0x38,1:16384 CONFIG2H~2~5=0x78,0x30,1:4096 CONFIG2H~2~6=0x78,0x28,1:1024 CONFIG2H~2~7=0x78,0x20,1:256 CONFIG2H~2~8=0x78,0x18,1:64 CONFIG2H~2~9=0x78,0x10,1:16 CONFIG2H~2~10=0x78,0x8,1:4 CONFIG2H~2~11=0x78,0x0,1:1 CONFIG2H~3~1=0x04,0x04,No Divide CONFIG2H~3~2=0x04,0x0,Divide By 2 CONFIG3H_unused=0x0 CONFIG3H~1=CANMX,0x1,ECAN Mux bit CONFIG3H~2=MSSPMSK,0x8,MSSP address masking CONFIG3H~3=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,ECAN TX and RX pins are located on RB2 and RB3, respectively CONFIG3H~1~2=0x1,0x0,ECAN TX and RX pins are located on RC6 and RC7, respectively CONFIG3H~2~1=0x8,0x8,7 Bit address masking mode CONFIG3H~2~2=0x8,0x0,5 bit address masking mode CONFIG3H~3~1=0x80,0x80,MCLR Enabled, RG5 Disabled CONFIG3H~3~2=0x80,0x0,MCLR Disabled, RG5 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVREN,0x1,Stack Overflow Reset CONFIG4L~2=BBSIZ,0x10,Boot Block Size CONFIG4L~3=DEBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x10,0x10,2K word Boot Block size CONFIG4L~2~2=0x10,0x0,1K word Boot Block size CONFIG4L~3~1=0x80,0x80,Disabled CONFIG4L~3~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP0,0x1,Code Protect 00800-03FFF CONFIG5L~2=CP1,0x2,Code Protect 04000-07FFF CONFIG5L~3=CP2,0x4,Code Protect 08000-0BFFF CONFIG5L~4=CP3,0x8,Code Protect 0C000-0FFFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x0,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x0,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x0,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x0,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPB,0x40,Code Protect Boot CONFIG5H~2=CPD,0x80,Data EE Read Protect CONFIG5H~1~1=0x40,0x40,Disabled CONFIG5H~1~2=0x40,0x0,Enabled CONFIG5H~2~1=0x80,0x80,Disabled CONFIG5H~2~2=0x80,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT0,0x1,Table Write Protect 00800-03FFF CONFIG6L~2=WRT1,0x2,Table Write Protect 04000-07FFF CONFIG6L~3=WRT2,0x4,Table Write Protect 08000-0BFFF CONFIG6L~4=WRT3,0x8,Table Write Protect 0C000-0FFFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x0,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x0,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x0,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x0,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTC,0x20,Config. Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTD,0x80,Data EE Write Protect CONFIG6H~1~1=0x20,0x20,Disabled CONFIG6H~1~2=0x20,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x80,0x80,Disabled CONFIG6H~3~2=0x80,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBRT0,0x1,Table Read Protect 00800-03FFF CONFIG7L~2=EBRT1,0x2,Table Read Protect 04000-07FFF CONFIG7L~3=EBRT2,0x4,Table Read Protect 08000-0BFFF CONFIG7L~4=EBRT3,0x8,Table Read Protect 0C000-0FFFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x0,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x0,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x0,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x0,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBRTB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F65K80] pgmmem=0x0 ~pgmmem=0x7fff cfgmem=0x300000 ~cfgmem=0x30000d userid=0x200000 ~userid=0x200007 eedata=0x0 ~eedata=0x3ff devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0x6140 configslots=14 0x300000=CONFIG1L 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000a=CONFIG6L 0x30000b=CONFIG6H 0x30000c=CONFIG7L 0x30000d=CONFIG7H CONFIG1L_unused=0x0 CONFIG1L~1=RETEN,0x1,VREG Sleep Enable bit CONFIG1L~2=INTOSCSEL,0x4,LF-INTOSC Low-power Enable bit CONFIG1L~3=SOSCSEL,0x18,SOSC Power Selection and mode Configuration bits CONFIG1L~4=XINST,0x40,Extended Instruction Set CONFIG1L~1~1=0x1,0x0,Enabled CONFIG1L~1~2=0x1,0x1,Disabled CONFIG1L~2~1=0x4,0x4,High Security Code Protection Enable CONFIG1L~2~2=0x4,0x0,LF-INTOSC in Low-power mode during Sleep CONFIG1L~3~1=0x18,0x18,High Power SOSC circuit selected CONFIG1L~3~2=0x18,0x8,Low Power SOSC circuit selected CONFIG1L~3~3=0x18,0x10,Digital (SCLKI) mode CONFIG1L~4~1=0x40,0x40,Enabled CONFIG1L~4~2=0x40,0x0,Disabled CONFIG1H_unused=0x0 CONFIG1H~1=FOSC,0xf,Oscillator CONFIG1H~2=PLLCFG,0x10,PLL x4 Enable bit CONFIG1H~3=FCMEN,0x40,Fail-Safe Clock Monitor CONFIG1H~4=IESO,0x80,Internal External Oscillator Switch Over Mode CONFIG1H~1~1=0x7,0x7,External RC oscillator CONFIG1H~1~2=0x7,0x6,External RC oscillator, CLKOUT function on OSC2 CONFIG1H~1~3=0xf,0xd,EC oscillator (Low power, DC - 160 kHz) CONFIG1H~1~4=0xf,0xc,EC oscillator, CLKOUT function on OSC2 (Low power, DC - 160 kHz) CONFIG1H~1~5=0xf,0xb,EC oscillator (Medium power, 160 kHz - 4 MHz) CONFIG1H~1~6=0xf,0xa,EC oscillator, CLKOUT function on OSC2 (Medium power, 160 kHz - 4 MHz) CONFIG1H~1~7=0xf,0x9,Internal RC oscillator, CLKOUT function on OSC2 CONFIG1H~1~8=0xf,0x8,Internal RC oscillator CONFIG1H~1~9=0xf,0x5,EC oscillator (High power, 16 MHz - 64 MHz) CONFIG1H~1~10=0xf,0x4,EC oscillator, CLKOUT function on OSC2 (High power, 16 MHz - 64 MHz) CONFIG1H~1~11=0xf,0x3,HS oscillator (Medium power, 4 MHz - 16 MHz) CONFIG1H~1~12=0xf,0x2,HS oscillator (High power, 16 MHz - 25 MHz) CONFIG1H~1~13=0xf,0x1,XT oscillator CONFIG1H~1~14=0xf,0x0,LP oscillator CONFIG1H~2~1=0x10,0x10,Enabled CONFIG1H~2~2=0x10,0x0,Disabled CONFIG1H~3~1=0x40,0x0,Disabled CONFIG1H~3~2=0x40,0x40,Enabled CONFIG1H~4~1=0x80,0x0,Disabled CONFIG1H~4~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PWRTEN,0x1,Power Up Timer CONFIG2L~2=BOREN,0x6,Brown Out Detect CONFIG2L~3=BORV,0x18,Brown-out Reset Voltage bits CONFIG2L~4=BORPWR,0x60,BORMV Power level CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active, disabled in SLEEP, SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,1.8V CONFIG2L~3~2=0x18,0x10,2.0V CONFIG2L~3~3=0x18,0x8,2.7V CONFIG2L~3~4=0x18,0x0,3.0V CONFIG2L~4~1=0x60,0x60,ZPBORMV instead of BORMV is selected CONFIG2L~4~2=0x60,0x40,BORMV set to high power level CONFIG2L~4~3=0x60,0x20,BORMV set to medium power level CONFIG2L~4~4=0x60,0x0,BORMV set to low power level CONFIG2H_unused=0x0 CONFIG2H~1=WDTEN,0x3,Watchdog Timer CONFIG2H~2=WDTPS,0x78,Watchdog Postscaler CONFIG2H~3=WDTPS,0x04,Watchdog Postscaler/2 CONFIG2H~1~1=0x3,0x3,WDT enabled in hardware; SWDTEN bit disabled CONFIG2H~1~2=0x3,0x2,WDT controlled by SWDTEN bit setting CONFIG2H~1~3=0x3,0x1,WDT enabled only while device is active and disabled in Sleep mode; SWDTEN bit disabled CONFIG2H~1~4=0x3,0x0,WDT disabled in hardware; SWDTEN bit disabled CONFIG2H~2~1=0x78,0x70,1:1048576 CONFIG2H~2~2=0x78,0x48,1:262144 CONFIG2H~2~3=0x78,0x40,1:65536 CONFIG2H~2~4=0x78,0x38,1:16384 CONFIG2H~2~5=0x78,0x30,1:4096 CONFIG2H~2~6=0x78,0x28,1:1024 CONFIG2H~2~7=0x78,0x20,1:256 CONFIG2H~2~8=0x78,0x18,1:64 CONFIG2H~2~9=0x78,0x10,1:16 CONFIG2H~2~10=0x78,0x8,1:4 CONFIG2H~2~11=0x78,0x0,1:1 CONFIG2H~3~1=0x04,0x04,No Divide CONFIG2H~3~2=0x04,0x0,Divide By 2 CONFIG3H_unused=0x0 CONFIG3H~1=CANMX,0x1,ECAN Mux bit CONFIG3H~2=T0CKMX,0x2,Timer0 Clock Input Mux bit CONFIG3H~3=T3CKMX,0x4,Timer3 Clock Input Mux bit CONFIG3H~4=MSSPMSK,0x8,MSSP address masking CONFIG3H~5=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,ECAN TX and RX pins are located on RB2 and RB3, respectively CONFIG3H~1~2=0x1,0x0,ECAN TX and RX pins are located on RE5 and RE4, respectively CONFIG3H~2~1=0x2,0x2,Timer0 gets its clock input from the RB5/T0CKI pin on 64-pin packages CONFIG3H~2~2=0x2,0x0,Timer0 gets its clock input from the RG4/T0CKI pin on 64-pin packages CONFIG3H~3~1=0x4,0x4,Timer3 gets its clock input from the RG2/T3CKI pin on 64-pin packages CONFIG3H~3~2=0x4,0x0,Timer3 gets its clock input from the RB5/T3CKI pin on 64-pin packages CONFIG3H~4~1=0x8,0x8,7 Bit address masking mode CONFIG3H~4~2=0x8,0x0,5 bit address masking mode CONFIG3H~5~1=0x80,0x80,MCLR Enabled, RG5 Disabled CONFIG3H~5~2=0x80,0x0,MCLR Disabled, RG5 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVREN,0x1,Stack Overflow Reset CONFIG4L~2=BBSIZ,0x10,Boot Block Size CONFIG4L~3=DEBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x10,0x10,2K word Boot Block size CONFIG4L~2~2=0x10,0x0,1K word Boot Block size CONFIG4L~3~1=0x80,0x80,Disabled CONFIG4L~3~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP0,0x1,Code Protect 00800-03FFF CONFIG5L~2=CP1,0x2,Code Protect 04000-07FFF CONFIG5L~3=CP2,0x4,Code Protect 08000-0BFFF CONFIG5L~4=CP3,0x8,Code Protect 0C000-0FFFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x0,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x0,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x0,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x0,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPB,0x40,Code Protect Boot CONFIG5H~2=CPD,0x80,Data EE Read Protect CONFIG5H~1~1=0x40,0x40,Disabled CONFIG5H~1~2=0x40,0x0,Enabled CONFIG5H~2~1=0x80,0x80,Disabled CONFIG5H~2~2=0x80,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT0,0x1,Table Write Protect 00800-03FFF CONFIG6L~2=WRT1,0x2,Table Write Protect 04000-07FFF CONFIG6L~3=WRT2,0x4,Table Write Protect 08000-0BFFF CONFIG6L~4=WRT3,0x8,Table Write Protect 0C000-0FFFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x0,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x0,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x0,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x0,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTC,0x20,Config. Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTD,0x80,Data EE Write Protect CONFIG6H~1~1=0x20,0x20,Disabled CONFIG6H~1~2=0x20,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x80,0x80,Disabled CONFIG6H~3~2=0x80,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBRT0,0x1,Table Read Protect 00800-03FFF CONFIG7L~2=EBRT1,0x2,Table Read Protect 04000-07FFF CONFIG7L~3=EBRT2,0x4,Table Read Protect 08000-0BFFF CONFIG7L~4=EBRT3,0x8,Table Read Protect 0C000-0FFFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x0,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x0,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x0,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x0,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBRTB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA [PIC18F66K80] pgmmem=0x0 ~pgmmem=0xffff cfgmem=0x300000 ~cfgmem=0x30000d userid=0x200000 ~userid=0x200007 eedata=0x0 ~eedata=0x3ff devid=0x3ffffe ~devid=0x3fffff idmask=0xffe0 id=0x60e0 configslots=14 0x300000=CONFIG1L 0x300001=CONFIG1H 0x300002=CONFIG2L 0x300003=CONFIG2H 0x300004= 0x300005=CONFIG3H 0x300006=CONFIG4L 0x300007= 0x300008=CONFIG5L 0x300009=CONFIG5H 0x30000a=CONFIG6L 0x30000b=CONFIG6H 0x30000c=CONFIG7L 0x30000d=CONFIG7H CONFIG1L_unused=0x0 CONFIG1L~1=RETEN,0x1,VREG Sleep Enable bit CONFIG1L~2=INTOSCSEL,0x4,LF-INTOSC Low-power Enable bit CONFIG1L~3=SOSCSEL,0x18,SOSC Power Selection and mode Configuration bits CONFIG1L~4=XINST,0x40,Extended Instruction Set CONFIG1L~1~1=0x1,0x0,Enabled CONFIG1L~1~2=0x1,0x1,Disabled CONFIG1L~2~1=0x4,0x4,High Security Code Protection Enable CONFIG1L~2~2=0x4,0x0,LF-INTOSC in Low-power mode during Sleep CONFIG1L~3~1=0x18,0x18,High Power SOSC circuit selected CONFIG1L~3~2=0x18,0x8,Low Power SOSC circuit selected CONFIG1L~3~3=0x18,0x10,Digital (SCLKI) mode CONFIG1L~4~1=0x40,0x40,Enabled CONFIG1L~4~2=0x40,0x0,Disabled CONFIG1H_unused=0x0 CONFIG1H~1=FOSC,0xf,Oscillator CONFIG1H~2=PLLCFG,0x10,PLL x4 Enable bit CONFIG1H~3=FCMEN,0x40,Fail-Safe Clock Monitor CONFIG1H~4=IESO,0x80,Internal External Oscillator Switch Over Mode CONFIG1H~1~1=0x7,0x7,External RC oscillator CONFIG1H~1~2=0x7,0x6,External RC oscillator, CLKOUT function on OSC2 CONFIG1H~1~3=0xf,0xd,EC oscillator (Low power, DC - 160 kHz) CONFIG1H~1~4=0xf,0xc,EC oscillator, CLKOUT function on OSC2 (Low power, DC - 160 kHz) CONFIG1H~1~5=0xf,0xb,EC oscillator (Medium power, 160 kHz - 4 MHz) CONFIG1H~1~6=0xf,0xa,EC oscillator, CLKOUT function on OSC2 (Medium power, 160 kHz - 4 MHz) CONFIG1H~1~7=0xf,0x9,Internal RC oscillator, CLKOUT function on OSC2 CONFIG1H~1~8=0xf,0x8,Internal RC oscillator CONFIG1H~1~9=0xf,0x5,EC oscillator (High power, 16 MHz - 64 MHz) CONFIG1H~1~10=0xf,0x4,EC oscillator, CLKOUT function on OSC2 (High power, 16 MHz - 64 MHz) CONFIG1H~1~11=0xf,0x3,HS oscillator (Medium power, 4 MHz - 16 MHz) CONFIG1H~1~12=0xf,0x2,HS oscillator (High power, 16 MHz - 25 MHz) CONFIG1H~1~13=0xf,0x1,XT oscillator CONFIG1H~1~14=0xf,0x0,LP oscillator CONFIG1H~2~1=0x10,0x10,Enabled CONFIG1H~2~2=0x10,0x0,Disabled CONFIG1H~3~1=0x40,0x0,Disabled CONFIG1H~3~2=0x40,0x40,Enabled CONFIG1H~4~1=0x80,0x0,Disabled CONFIG1H~4~2=0x80,0x80,Enabled CONFIG2L_unused=0x0 CONFIG2L~1=PWRTEN,0x1,Power Up Timer CONFIG2L~2=BOREN,0x6,Brown Out Detect CONFIG2L~3=BORV,0x18,Brown-out Reset Voltage bits CONFIG2L~4=BORPWR,0x60,BORMV Power level CONFIG2L~1~1=0x1,0x1,Disabled CONFIG2L~1~2=0x1,0x0,Enabled CONFIG2L~2~1=0x6,0x6,Enabled in hardware, SBOREN disabled CONFIG2L~2~2=0x6,0x4,Enabled while active, disabled in SLEEP, SBOREN disabled CONFIG2L~2~3=0x6,0x2,Controlled with SBOREN bit CONFIG2L~2~4=0x6,0x0,Disabled in hardware, SBOREN disabled CONFIG2L~3~1=0x18,0x18,1.8V CONFIG2L~3~2=0x18,0x10,2.0V CONFIG2L~3~3=0x18,0x8,2.7V CONFIG2L~3~4=0x18,0x0,3.0V CONFIG2L~4~1=0x60,0x60,ZPBORMV instead of BORMV is selected CONFIG2L~4~2=0x60,0x40,BORMV set to high power level CONFIG2L~4~3=0x60,0x20,BORMV set to medium power level CONFIG2L~4~4=0x60,0x0,BORMV set to low power level CONFIG2H_unused=0x0 CONFIG2H~1=WDTEN,0x3,Watchdog Timer CONFIG2H~2=WDTPS,0x78,Watchdog Postscaler CONFIG2H~3=WDTPS,0x04,Watchdog Postscaler/2 CONFIG2H~1~1=0x3,0x3,WDT enabled in hardware; SWDTEN bit disabled CONFIG2H~1~2=0x3,0x2,WDT controlled by SWDTEN bit setting CONFIG2H~1~3=0x3,0x1,WDT enabled only while device is active and disabled in Sleep mode; SWDTEN bit disabled CONFIG2H~1~4=0x3,0x0,WDT disabled in hardware; SWDTEN bit disabled CONFIG2H~2~1=0x78,0x70,1:1048576 CONFIG2H~2~2=0x78,0x48,1:262144 CONFIG2H~2~3=0x78,0x40,1:65536 CONFIG2H~2~4=0x78,0x38,1:16384 CONFIG2H~2~5=0x78,0x30,1:4096 CONFIG2H~2~6=0x78,0x28,1:1024 CONFIG2H~2~7=0x78,0x20,1:256 CONFIG2H~2~8=0x78,0x18,1:64 CONFIG2H~2~9=0x78,0x10,1:16 CONFIG2H~2~10=0x78,0x8,1:4 CONFIG2H~2~11=0x78,0x0,1:1 CONFIG2H~3~1=0x04,0x04,No Divide CONFIG2H~3~2=0x04,0x0,Divide By 2 CONFIG3H_unused=0x0 CONFIG3H~1=CANMX,0x1,ECAN Mux bit CONFIG3H~2=T0CKMX,0x2,Timer0 Clock Input Mux bit CONFIG3H~3=T3CKMX,0x4,Timer3 Clock Input Mux bit CONFIG3H~4=MSSPMSK,0x8,MSSP address masking CONFIG3H~5=MCLRE,0x80,Master Clear Enable CONFIG3H~1~1=0x1,0x1,ECAN TX and RX pins are located on RB2 and RB3, respectively CONFIG3H~1~2=0x1,0x0,ECAN TX and RX pins are located on RE5 and RE4, respectively CONFIG3H~2~1=0x2,0x2,Timer0 gets its clock input from the RB5/T0CKI pin on 64-pin packages CONFIG3H~2~2=0x2,0x0,Timer0 gets its clock input from the RG4/T0CKI pin on 64-pin packages CONFIG3H~3~1=0x4,0x4,Timer3 gets its clock input from the RG2/T3CKI pin on 64-pin packages CONFIG3H~3~2=0x4,0x0,Timer3 gets its clock input from the RB5/T3CKI pin on 64-pin packages CONFIG3H~4~1=0x8,0x8,7 Bit address masking mode CONFIG3H~4~2=0x8,0x0,5 bit address masking mode CONFIG3H~5~1=0x80,0x80,MCLR Enabled, RG5 Disabled CONFIG3H~5~2=0x80,0x0,MCLR Disabled, RG5 Enabled CONFIG4L_unused=0x0 CONFIG4L~1=STVREN,0x1,Stack Overflow Reset CONFIG4L~2=BBSIZ,0x10,Boot Block Size CONFIG4L~3=DEBUG,0x80,Background Debug CONFIG4L~1~1=0x1,0x1,Enabled CONFIG4L~1~2=0x1,0x0,Disabled CONFIG4L~2~1=0x10,0x10,2K word Boot Block size CONFIG4L~2~2=0x10,0x0,1K word Boot Block size CONFIG4L~3~1=0x80,0x80,Disabled CONFIG4L~3~2=0x80,0x0,Enabled CONFIG5L_unused=0x0 CONFIG5L~1=CP0,0x1,Code Protect 00800-03FFF CONFIG5L~2=CP1,0x2,Code Protect 04000-07FFF CONFIG5L~3=CP2,0x4,Code Protect 08000-0BFFF CONFIG5L~4=CP3,0x8,Code Protect 0C000-0FFFF CONFIG5L~1~1=0x1,0x1,Disabled CONFIG5L~1~2=0x1,0x0,Enabled CONFIG5L~2~1=0x2,0x2,Disabled CONFIG5L~2~2=0x2,0x0,Enabled CONFIG5L~3~1=0x4,0x4,Disabled CONFIG5L~3~2=0x4,0x0,Enabled CONFIG5L~4~1=0x8,0x8,Disabled CONFIG5L~4~2=0x8,0x0,Enabled CONFIG5H_unused=0x0 CONFIG5H~1=CPB,0x40,Code Protect Boot CONFIG5H~2=CPD,0x80,Data EE Read Protect CONFIG5H~1~1=0x40,0x40,Disabled CONFIG5H~1~2=0x40,0x0,Enabled CONFIG5H~2~1=0x80,0x80,Disabled CONFIG5H~2~2=0x80,0x0,Enabled CONFIG6L_unused=0x0 CONFIG6L~1=WRT0,0x1,Table Write Protect 00800-03FFF CONFIG6L~2=WRT1,0x2,Table Write Protect 04000-07FFF CONFIG6L~3=WRT2,0x4,Table Write Protect 08000-0BFFF CONFIG6L~4=WRT3,0x8,Table Write Protect 0C000-0FFFF CONFIG6L~1~1=0x1,0x1,Disabled CONFIG6L~1~2=0x1,0x0,Enabled CONFIG6L~2~1=0x2,0x2,Disabled CONFIG6L~2~2=0x2,0x0,Enabled CONFIG6L~3~1=0x4,0x4,Disabled CONFIG6L~3~2=0x4,0x0,Enabled CONFIG6L~4~1=0x8,0x8,Disabled CONFIG6L~4~2=0x8,0x0,Enabled CONFIG6H_unused=0x0 CONFIG6H~1=WRTC,0x20,Config. Write Protect CONFIG6H~2=WRTB,0x40,Table Write Protect Boot CONFIG6H~3=WRTD,0x80,Data EE Write Protect CONFIG6H~1~1=0x20,0x20,Disabled CONFIG6H~1~2=0x20,0x0,Enabled CONFIG6H~2~1=0x40,0x40,Disabled CONFIG6H~2~2=0x40,0x0,Enabled CONFIG6H~3~1=0x80,0x80,Disabled CONFIG6H~3~2=0x80,0x0,Enabled CONFIG7L_unused=0x0 CONFIG7L~1=EBRT0,0x1,Table Read Protect 00800-03FFF CONFIG7L~2=EBRT1,0x2,Table Read Protect 04000-07FFF CONFIG7L~3=EBRT2,0x4,Table Read Protect 08000-0BFFF CONFIG7L~4=EBRT3,0x8,Table Read Protect 0C000-0FFFF CONFIG7L~1~1=0x1,0x1,Disabled CONFIG7L~1~2=0x1,0x0,Enabled CONFIG7L~2~1=0x2,0x2,Disabled CONFIG7L~2~2=0x2,0x0,Enabled CONFIG7L~3~1=0x4,0x4,Disabled CONFIG7L~3~2=0x4,0x0,Enabled CONFIG7L~4~1=0x8,0x8,Disabled CONFIG7L~4~2=0x8,0x0,Enabled CONFIG7H_unused=0x0 CONFIG7H~1=EBRTB,0x40,Table Read Protect Boot CONFIG7H~1~1=0x40,0x40,Disabled CONFIG7H~1~2=0x40,0x0,Enabled erase=18F_ERASE prog=18F_PROG config=18F_CONFIG data=18F_DATA