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Hi All,
Using Hi-tec I wanted to determine if cause of firmware resetting was watchdog time out or not.
So at the beginning of main I placed: In the hope to test watchdog timeout.
Data sheet shows if watch timeout occurred, then TO bit of status would change to 0
So I enabled WDT and placed while(1) loop.
I am getting a load of 1's sent via RS232,
so WDT register is read as 1 and not expected 0.
Not sent reset WDT command prior to reading status bit4 , So status(4) is not acting on a clear watchdog command

So after a WDT reset does anyone know why status bit TO is set at 1 when data sheet shows as NOT TO?
I.e. default for status bit 4 = 0 .
Thanks

Martin

Hi Martin,

Hm thats an odd one. I wonder if its anything to do with how you are reading the bit from the register.

Could you try this C code instead.

FCV_PREV_FINAL_SPEED = test_bit(STATUS, TO);

or

FCV_PREV_FINAL_SPEED = STATUSbits.TO;

The status register might be named slightly differently. Eg maybe status_reg.

Section 11.6 of the datasheet has a bit more information but not a lot.

Thanks for your reply Ben,
I tried the top option and just all number 2's was displayed.
That was odd since it's a bit that is being tested, was expecting a 0 or 1

Tried different combinations for the second option you gave, and all combinations would not allow flowchart to compile.

Martin