Phase Locked Loop (PLL) - Revision history

DavidA at 11:12, 5 August 2019

2019-08-05T11:12:34Z

2019-07-02T08:24:46Z

2014-03-10T17:41:40Z

2014-03-07T17:12:17Z

2013-11-06T14:03:10Z

2013-11-06T11:40:22Z

2013-11-06T11:39:36Z

2013-11-06T11:37:12Z

2013-11-06T11:05:44Z

2013-11-06T11:04:46Z

@@ Line 16: / Line 16: @@
 Here is a piece of example C code used to enable the PLL on-board a PIC18F24J50 device.
-[[File:PLLConf2.jpg]]
+[[File:Pll-ss-1.png]]
@@ Line 23: / Line 23: @@
 This takes the input clock speed of 12MHz and multiplies it up to 80MHz to provide the maximum clock frequency for the device which equates to 40MIPs.
-[[File:PLLConf3.jpg]]
+[[File:Pll-ss-2.png]]

← Older revision		Revision as of 08:24, 2 July 2019
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−	~~<sidebar>Sidebar: Flowcode Help Overview:ChipSpecific</sidebar>~~
	A lot of the devices have an inbuilt PLL or phase locked loop which can be used to provide a variable frequency from a fixed source oscillator such as a crystal.		A lot of the devices have an inbuilt PLL or phase locked loop which can be used to provide a variable frequency from a fixed source oscillator such as a crystal.

@@ Line 8: / Line 8: @@
 The device datasheet should detail if a PLL is available to the device.
-Some devices are very easy to configure and expose all the settings for the PLL via the configuration options. An example of this is the PIC18F2455 family which features a PLL to provide the functionality of boosting the input clock speed to 48MHz which is compatible with full speed USB communications. Here we have specified a 4MHz input clock speed and configured the oscillator to use the PLL multiplied version of the HS oscillator.
+Some devices are very easy to configure and expose all the settings for the PLL via the configuration options. An example of this is the PIC18F2455 family which features a PLL to provide the functionality of boosting the input clock speed to 48MHz which is compatible with full speed USB communications. Here we have specified a 4MHz input clock speed and configured the oscillator to use the PLL multiplied version of the HS (HighSpeed) oscillator.
 [[File:PLLConf1.jpg]]

← Older revision		Revision as of 17:12, 7 March 2014
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−	<sidebar>Sidebar: ~~Advanced Features~~</sidebar>	+	<sidebar>Sidebar: Flowcode Help Overview:ChipSpecific</sidebar>
	A lot of the devices have an inbuilt PLL or phase locked loop which can be used to provide a variable frequency from a fixed source oscillator such as a crystal.		A lot of the devices have an inbuilt PLL or phase locked loop which can be used to provide a variable frequency from a fixed source oscillator such as a crystal.

← Older revision		Revision as of 14:03, 6 November 2013
Line 1:		Line 1:
		+	<sidebar>Sidebar: Advanced Features</sidebar>
	A lot of the devices have an inbuilt PLL or phase locked loop which can be used to provide a variable frequency from a fixed source oscillator such as a crystal.		A lot of the devices have an inbuilt PLL or phase locked loop which can be used to provide a variable frequency from a fixed source oscillator such as a crystal.

← Older revision		Revision as of 11:40, 6 November 2013
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−	Here is an example of a much more complicated PLL where there is a large calculation using several parameters that determines the overall output frequency as seen on the dsPIC33FJ128GP802. This takes the input clock speed of 12MHz and multiplies it up to 80MHz to provide the maximum clock frequency for the device of 40MIPs.	+	Here is an example of a much more complicated PLL where there is a large calculation using several parameters that determines the overall output frequency as seen on the dsPIC33FJ128GP802.
		+
		+	This takes the input clock speed of 12MHz and multiplies it up to 80MHz to provide the maximum clock frequency for the device which equates to 40MIPs.

	[[File:PLLConf3.jpg]]		[[File:PLLConf3.jpg]]

← Older revision		Revision as of 11:39, 6 November 2013
Line 19:		Line 19:


−	Here is an example of a much more complicated PLL where there is a large calculation using several parameters that determines the overall output frequency as seen on the dsPIC33FJ128GP802.	+	Here is an example of a much more complicated PLL where there is a large calculation using several parameters that determines the overall output frequency as seen on the dsPIC33FJ128GP802. This takes the input clock speed of 12MHz and multiplies it up to 80MHz to provide the maximum clock frequency for the device of 40MIPs.

	[[File:PLLConf3.jpg]]		[[File:PLLConf3.jpg]]

← Older revision		Revision as of 11:37, 6 November 2013
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	[[File:PLLConf3.jpg]]		[[File:PLLConf3.jpg]]
		+
		+
		+	Here is the PLL calculation plus information shown in the dsPIC33FJ128GP802 device datasheet.
		+
		+	[[File:PLLConf4.jpg]]

← Older revision	Revision as of 11:05, 6 November 2013
(No difference)