In the output I notice:
I couldn't see any way to change this from within Flowcode - but by editing sdkconfig in the project directory - I changedW (312) spi_flash: Detected size(4096k) larger than the size in the binary image header(2048k). Using the size in the binary image header.
Code: Select all
CONFIG_ESPTOOLPY_FLASHSIZE_2MB=y
# CONFIG_ESPTOOLPY_FLASHSIZE_4MB is not set
Code: Select all
# CONFIG_ESPTOOLPY_FLASHSIZE_2MB is not set
CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y
Code: Select all
uart.initialise()
print("Hello World\r\n"
and then either nothing or
Loop
empty or delay(1 ms)
end loop
I did set the 'Auto Clear Watchdog' in project options.E (10333) task_wdt: Task watchdog got triggered. The following tasks did not reset the watchdog in time:
E (10333) task_wdt: - IDLE0 (CPU 0)
E (10333) task_wdt: Tasks currently running:
E (10333) task_wdt: CPU 0: main
E (10333) task_wdt: CPU 1: IDLE1
E (10333) task_wdt: Print CPU 0 (current core) backtrace
If the loop contains a print then this works AOK..
Also at the start of program run I get a fair bit of info printed :
Which I'm happy with in a development system - but is there a way to 'turn it off' in a 'release' version? --- I suspect some editing of sdkconfig is the answer - but would be very good for it to be done automagically from FC??ets Jun 8 2016 00:22:57
rst:0x1 (POWERON_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
configsip: 0, SPIWP:0xee
clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
mode:DIO, clock div:2
load:0x3fff0030,len:4
load:0x3fff0034,len:6848
ho 0 tail 12 room 4
load:0x40078000,len:13108
load:0x40080400,len:3900
entry 0x40080688
I (31) boot: ESP-IDF -128-NOTFOUND 2nd stage bootloader
I (31) boot: compile time 19:52:25
I (31) boot: chip revision: 1
I (34) boot_comm: chip revision: 1, min. bootloader chip revision: 0
I (41) boot.esp32: SPI Speed : 40MHz
I (46) boot.esp32: SPI Mode : DIO
I (50) boot.esp32: SPI Flash Size : 2MB
I (55) boot: Enabling RNG early entropy source...
I (60) boot: Partition Table:
I (64) boot: ## Label Usage Type ST Offset Length
I (71) boot: 0 nvs WiFi data 01 02 00009000 00006000
I (79) boot: 1 phy_init RF data 01 01 0000f000 00001000
I (86) boot: 2 factory factory app 00 00 00010000 00100000
I (94) boot: End of partition table
I (98) boot_comm: chip revision: 1, min. application chip revision: 0
I (105) esp_image: segment 0: paddr=0x00010020 vaddr=0x3f400020 size=0x07ee8 ( 32488) map
I (126) esp_image: segment 1: paddr=0x00017f10 vaddr=0x3ffbdb60 size=0x02128 ( 8488) load
.....
Martin