Matrix - Electronic Circuits and Components | A555TimerCircuits / Introduction: 555 Timer

<^< 555 Timer Circuits | Course Index | Astable Pulse Generator >^>(:nl:)

The 555 timer is without doubt one of the most versatile integrated circuit chips ever produced. Not only is it a neat mixture of analogue and digital circuitry but its applications are virtually limitless in the world of digital pulse generation. In order to understand how timer circuits operate, it is worth spending a few moments studying the internal circuitry of the 555 even though at this stage you may not have covered sufficient material to understand all aspects of the 555 operation. (R-S bistables are covered in Digital Electronics).

Essentially, the 555 comprises two operational amplifiers (used as comparators) together with an R-S bistable logic element. In addition, an inverting buffer is incorporated so that a considerable current can be delivered to a load.

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The series chain of resistors, R'_1_', R'_2_' and R'_3_', all have identical values which results in the supply voltage being divided equally across the three resistors. Thus, with no external connections, the voltage at the inverting input of IC'_1_' is one-third of the supply voltage, V'_CC_', whilst that at the non-inverting input of IC'_2_' is two-thirds of the supply voltage, V'_CC_'. To put this into context, if V'_CC_' is 9V, 3V will appear across each resistor, the upper comparator will have 6V at its inverting input whilst the lower comparator will have 3V at its non-inverting input. >><< >>id=box2 class=toggle center<<

These two operational amplifiers are used as comparators. The upper comparator, IC'_1_', is connected to the Reset input of the bistable whilst the lower comparator, IC'_2_', is connected to the Set input of the bistable. The bistable will thus be Set or Reset according to the difference in the voltages that appear between the inverting and non-inverting inputs of the two comparators. We will see how this works a little later. >><< >>id=box3 class=toggle center<<

This R-S bistable element is used as a latch. The bistable can be triggered into the set state (in which case goes low) by applying a pulse to the Set input or the reset state (in which case goes high) by applying a pulse to the Reset input. >><< >>id=box4 class=toggle center<<

The transistor, TR'_1_', is used to discharge an external capacitor connected between pin-7 and 0V. When the output of the bistable goes high, TR'_1_' is turned on (conducting) and discharges the external capacitor with current flowing from collector to emitter. When the output is low, TR'_1_' is in the off (non-conducting) state and no current flows from collector to emitter. >><< >>id=box5 class=toggle center<<

This inverting buffer is incorporated so that an appreciable current can be delivered to an external load connected to pin-3. It's worth noting that, unlike standard TTL logic devices, the 555 timer can both source and sink current. When sourcing current, the 555's output (pin-3) is in the high state and current will then flow out of the output pin into the load and down to 0V. When sinking current, the 555's output (pin-3) is in the low state in which case current will flow from the positive supply (+V'_CC_') through the load and into the output (pin-3). >><<

Resistor Chain
Operational Amplifiers
R-S Bistable
Transistor
Inverter

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